From 9d737af35126c3a857e1c6a3356ab3879e92b6eb Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 20 Apr 2022 19:16:47 +0200 Subject: riscv: Add a option to specify the JTAG TAP tunnel IR (#690) * riscv: Add a option to specify the JTAG TAP IR used to access the bscan tunnel. Change-Id: Ice8798823313e2177e75473e62b06e7da74bbba2 Signed-off-by: Charles Papon * risc-v: Add litex doc about the set_bscan_tunnel_ir command Change-Id: I1237213f32886d20fc7d60d5ca1e2124953eaeda Signed-off-by: Dolu1990 * risc-v: remove tunnel ir length assert when ir is set by the user Change-Id: I2b33fc6205f37461ff1bd15601b460a2467ea32b Signed-off-by: Dolu1990 * Open riscv: Add a option to specify the JTAG TAP tunnel IR Typo Co-authored-by: Tim Newsome * riscv: Add a option to specify the JTAG TAP tunnel IR typo Co-authored-by: Tim Newsome Co-authored-by: Tim Newsome --- doc/openocd.texi | 5 +++++ src/target/riscv/riscv.c | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index a4fa684..1870287 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -10624,6 +10624,11 @@ tunneled DR scan consists of: @end deffn +@deffn {Command} {riscv set_bscan_tunnel_ir} value +Allows the use_bscan_tunnel feature to target non Xilinx device by +specifying the JTAG TAP IR used to access the bscan tunnel. +@end deffn + @deffn {Command} {riscv set_maskisr} [@option{off}|@option{steponly}] Selects whether interrupts will be disabled when single stepping. The default configuration is @option{off}. This feature is only useful on hardware that always steps into interrupts and doesn't support dcsr.stepie=0. diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 484db74..bde85b5 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -129,6 +129,7 @@ struct scan_field select_idcode = { bscan_tunnel_type_t bscan_tunnel_type; int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */ +static int bscan_tunnel_ir_id; /* IR ID of the JTAG TAP to access the tunnel. Valid when not 0 */ static const uint8_t bscan_zero[4] = {0}; static const uint8_t bscan_one[4] = {1}; @@ -450,8 +451,12 @@ static int riscv_init_target(struct command_context *cmd_ctx, select_idcode.num_bits = target->tap->ir_length; if (bscan_tunnel_ir_width != 0) { - assert(target->tap->ir_length >= 6); - uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6); + uint32_t ir_user4_raw = bscan_tunnel_ir_id; + /* Provide a default value which target some Xilinx FPGA USER4 IR */ + if (ir_user4_raw == 0) { + assert(target->tap->ir_length >= 6); + ir_user4_raw = 0x23 << (target->tap->ir_length - 6); + } ir_user4[0] = (uint8_t)ir_user4_raw; ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8); ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8); @@ -2913,6 +2918,24 @@ COMMAND_HANDLER(riscv_use_bscan_tunnel) return ERROR_OK; } +COMMAND_HANDLER(riscv_set_bscan_tunnel_ir) +{ + int ir_id = 0; + + if (CMD_ARGC > 1) { + LOG_ERROR("Command takes at most one arguments"); + return ERROR_COMMAND_SYNTAX_ERROR; + } else if (CMD_ARGC == 1) { + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], ir_id); + } + + LOG_INFO("Bscan tunnel IR 0x%x selected", ir_id); + + bscan_tunnel_ir_id = ir_id; + return ERROR_OK; +} + + COMMAND_HANDLER(riscv_set_maskisr) { struct target *target = get_current_target(CMD_CTX); @@ -3348,6 +3371,15 @@ static const struct command_registration riscv_exec_command_handlers[] = { "1: DATA_REGISTER}" }, { + .name = "set_bscan_tunnel_ir", + .handler = riscv_set_bscan_tunnel_ir, + .mode = COMMAND_ANY, + .usage = "value", + .help = "Specify the JTAG TAP IR used to access the bscan tunnel. " + "By default it is 0x23 << (ir_length - 6), which map some " + "Xilinx FPGA (IR USER4)" + }, + { .name = "set_maskisr", .handler = riscv_set_maskisr, .mode = COMMAND_EXEC, -- cgit v1.1