From 8ecc2888cf219454527d77a7d355fdbe12c319f9 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Sun, 25 Apr 2021 07:53:26 +0100 Subject: cortex_m: use unsigned int for FPB and DWT quantifiers related quantifiers are: - fp_num_lit - fp_num_code - dwt_num_comp - dwt_comp_available Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6185 Tested-by: jenkins Reviewed-by: Tomas Vanek --- src/target/cortex_m.c | 59 ++++++++++++++++++++++++--------------------------- src/target/cortex_m.h | 8 +++---- 2 files changed, 32 insertions(+), 35 deletions(-) diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 2b38b4a..982f550 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -285,7 +285,6 @@ static int cortex_m_enable_fpb(struct target *target) static int cortex_m_endreset_event(struct target *target) { - int i; int retval; uint32_t dcb_demcr; struct cortex_m_common *cortex_m = target_to_cm(target); @@ -343,14 +342,14 @@ static int cortex_m_endreset_event(struct target *target) cortex_m->fpb_enabled = true; /* Restore FPB registers */ - for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) { + for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) { retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); if (retval != ERROR_OK) return retval; } /* Restore DWT registers */ - for (i = 0; i < cortex_m->dwt_num_comp; i++) { + for (unsigned int i = 0; i < cortex_m->dwt_num_comp; i++) { retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, dwt_list[i].comp); if (retval != ERROR_OK) @@ -1266,7 +1265,7 @@ static int cortex_m_deassert_reset(struct target *target) int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; - int fp_num = 0; + unsigned int fp_num = 0; struct cortex_m_common *cortex_m = target_to_cm(target); struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list; @@ -1353,7 +1352,7 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi struct cortex_m_common *cortex_m = target_to_cm(target); struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list; - if (!breakpoint->set) { + if (breakpoint->set <= 0) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } @@ -1366,8 +1365,8 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi breakpoint->set); if (breakpoint->type == BKPT_HARD) { - int fp_num = breakpoint->set - 1; - if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) { + unsigned int fp_num = breakpoint->set - 1; + if (fp_num >= cortex_m->fp_num_code) { LOG_DEBUG("Invalid FP Comparator number in breakpoint"); return ERROR_OK; } @@ -1413,7 +1412,7 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { - int dwt_num = 0; + unsigned int dwt_num = 0; struct cortex_m_common *cortex_m = target_to_cm(target); /* REVISIT Don't fully trust these "not used" records ... users @@ -1498,21 +1497,20 @@ static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *w { struct cortex_m_common *cortex_m = target_to_cm(target); struct cortex_m_dwt_comparator *comparator; - int dwt_num; - if (!watchpoint->set) { + if (watchpoint->set <= 0) { LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id); return ERROR_OK; } - dwt_num = watchpoint->set - 1; + unsigned int dwt_num = watchpoint->set - 1; LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", watchpoint->unique_id, dwt_num, (unsigned) watchpoint->address); - if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) { + if (dwt_num >= cortex_m->dwt_num_comp) { LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } @@ -1851,7 +1849,7 @@ static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target uint32_t dwtcr; struct reg_cache *cache; struct cortex_m_dwt_comparator *comparator; - int reg, i; + int reg; target_read_u32(target, DWT_CTRL, &dwtcr); LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr); @@ -1893,7 +1891,7 @@ fail1: dwt_base_regs + reg); comparator = cm->dwt_comparator_list; - for (i = 0; i < cm->dwt_num_comp; i++, comparator++) { + for (unsigned int i = 0; i < cm->dwt_num_comp; i++, comparator++) { int j; comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; @@ -1964,7 +1962,6 @@ int cortex_m_examine(struct target *target) { int retval; uint32_t cpuid, fpcr, mvfr0, mvfr1; - int i; struct cortex_m_common *cortex_m = target_to_cm(target); struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap; struct armv7m_common *armv7m = target_to_armv7m(target); @@ -2000,23 +1997,23 @@ int cortex_m_examine(struct target *target) return retval; /* Get CPU Type */ - i = (cpuid >> 4) & 0xf; + unsigned int core = (cpuid >> 4) & 0xf; /* Check if it is an ARMv8-M core */ armv7m->arm.is_armv8m = true; switch (cpuid & ARM_CPUID_PARTNO_MASK) { case CORTEX_M23_PARTNO: - i = 23; + core = 23; break; case CORTEX_M33_PARTNO: - i = 33; + core = 33; break; case CORTEX_M35P_PARTNO: - i = 35; + core = 35; break; case CORTEX_M55_PARTNO: - i = 55; + core = 55; break; default: armv7m->arm.is_armv8m = false; @@ -2025,9 +2022,9 @@ int cortex_m_examine(struct target *target) LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected", - i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); + core, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); cortex_m->maskints_erratum = false; - if (i == 7) { + if (core == 7) { uint8_t rev, patch; rev = (cpuid >> 20) & 0xf; patch = (cpuid >> 0) & 0xf; @@ -2041,28 +2038,28 @@ int cortex_m_examine(struct target *target) /* VECTRESET is supported only on ARMv7-M cores */ cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m; - if (i == 4) { + if (core == 4) { target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); /* test for floating point feature on Cortex-M4 */ if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { - LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); + LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", core); armv7m->fp_feature = FPV4_SP; } - } else if (i == 7 || i == 33 || i == 35 || i == 55) { + } else if (core == 7 || core == 33 || core == 35 || core == 55) { target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); /* test for floating point features on Cortex-M7 */ if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) { - LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i); + LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", core); armv7m->fp_feature = FPV5_SP; } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) { - LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i); + LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", core); armv7m->fp_feature = FPV5_DP; } - } else if (i == 0) { + } else if (core == 0) { /* Cortex-M0 does not support unaligned memory access */ armv7m->arm.is_armv6m = true; } @@ -2074,11 +2071,11 @@ int cortex_m_examine(struct target *target) if (!armv7m->stlink) { - if (i == 3 || i == 4) + if (core == 3 || core == 4) /* Cortex-M3/M4 have 4096 bytes autoincrement range, * s. ARM IHI 0031C: MEM-AP 7.2.2 */ armv7m->debug_ap->tar_autoincr_block = (1 << 12); - else if (i == 7) + else if (core == 7) /* Cortex-M7 has only 1024 bytes autoincrement range */ armv7m->debug_ap->tar_autoincr_block = (1 << 10); } @@ -2119,7 +2116,7 @@ int cortex_m_examine(struct target *target) cortex_m->fp_num_code + cortex_m->fp_num_lit, sizeof(struct cortex_m_fp_comparator)); cortex_m->fpb_enabled = fpcr & 1; - for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) { + for (unsigned int i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) { cortex_m->fp_comparator_list[i].type = (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 1e2197b..0f221ff 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -196,15 +196,15 @@ struct cortex_m_common { uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */ /* Flash Patch and Breakpoint (FPB) */ - int fp_num_lit; - int fp_num_code; + unsigned int fp_num_lit; + unsigned int fp_num_code; int fp_rev; bool fpb_enabled; struct cortex_m_fp_comparator *fp_comparator_list; /* Data Watchpoint and Trace (DWT) */ - int dwt_num_comp; - int dwt_comp_available; + unsigned int dwt_num_comp; + unsigned int dwt_comp_available; uint32_t dwt_devarch; struct cortex_m_dwt_comparator *dwt_comparator_list; struct reg_cache *dwt_cache; -- cgit v1.1 From 5ba8e365d9f02b7cb4a316959e0c8b39274f9d83 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 26 Apr 2021 14:22:06 +0200 Subject: telnet: allow hiding selected commands during auto-completion We have TCL procedure and commands that we do not want to show in the list of auto-completion. E.g. TCL wrappers for deprecated commands, internal procedures that are not supposed to be exposed to user, or even commands that the user decides to hide. Create a TCL procedure to be called by telnet auto-complete code in place of the hard-coded TCL command. The procedure will run the same command and will filter-out the unwanted command names. Initialize the list of commands to be filtered-out with the name of the TCL procedure above, as it is considered as internal. Change-Id: I2d83bbf8194502368c589c85cccb617e69128c69 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6194 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI --- src/server/startup.tcl | 17 +++++++++++++++++ src/server/telnet_server.c | 2 +- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/server/startup.tcl b/src/server/startup.tcl index dd1b31e..04a1cc0 100644 --- a/src/server/startup.tcl +++ b/src/server/startup.tcl @@ -19,3 +19,20 @@ proc prevent_cps {} { proc POST {args} { prevent_cps } proc Host: {args} { prevent_cps } + +# list of commands we don't want to appear in autocomplete +lappend _telnet_autocomplete_skip _telnet_autocomplete_helper + +# helper for telnet autocomplete +proc _telnet_autocomplete_helper pattern { + set cmds [info commands $pattern] + + # skip matches in variable '_telnet_autocomplete_skip' + foreach skip $::_telnet_autocomplete_skip { + foreach n [lsearch -all -regexp $cmds "^$skip\$"] { + set cmds [lreplace $cmds $n $n] + } + } + + return [lsort $cmds] +} diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c index d5e0353..acb57ef 100644 --- a/src/server/telnet_server.c +++ b/src/server/telnet_server.c @@ -470,7 +470,7 @@ static void telnet_auto_complete(struct connection *connection) query[usr_cmd_len] = '\0'; /* filter commands */ - char *query_cmd = alloc_printf("lsort [info commands {%s*}]", query); + char *query_cmd = alloc_printf("_telnet_autocomplete_helper {%s*}", query); if (!query_cmd) { LOG_ERROR("Out of memory"); -- cgit v1.1 From 223b79ebe21d53a21c85289349232fe7b8dca564 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 26 Apr 2021 14:44:48 +0200 Subject: telnet/auto-complete: hide deprecated and internal commands For both: - TCL proc that redirect deprecated commands to the new commands, - TCL proc used internally and not supposed to be exposed to user, add their name to the list of commands that should be hide by the telnet auto-complete. Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6195 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI --- src/flash/startup.tcl | 1 + src/jtag/startup.tcl | 12 ++++++++++++ src/server/startup.tcl | 3 +++ src/target/startup.tcl | 6 ++++++ 4 files changed, 22 insertions(+) diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl index 7d9dbc7..0a26da0 100644 --- a/src/flash/startup.tcl +++ b/src/flash/startup.tcl @@ -6,6 +6,7 @@ # optional args: verify, reset, exit and address # +lappend _telnet_autocomplete_skip program_error proc program_error {description exit} { if {$exit == 1} { echo $description diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl index f1e69e5..c1eb2b2 100644 --- a/src/jtag/startup.tcl +++ b/src/jtag/startup.tcl @@ -119,6 +119,7 @@ proc jtag_ntrst_assert_width args { # # FIXME phase these aids out after some releases # +lappend _telnet_autocomplete_skip jtag_reset proc jtag_reset args { echo "DEPRECATED! use 'adapter \[de\]assert' not 'jtag_reset'" switch $args { @@ -135,51 +136,61 @@ proc jtag_reset args { } } +lappend _telnet_autocomplete_skip adapter_khz proc adapter_khz args { echo "DEPRECATED! use 'adapter speed' not 'adapter_khz'" eval adapter speed $args } +lappend _telnet_autocomplete_skip adapter_name proc adapter_name args { echo "DEPRECATED! use 'adapter name' not 'adapter_name'" eval adapter name $args } +lappend _telnet_autocomplete_skip adapter_nsrst_delay proc adapter_nsrst_delay args { echo "DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'" eval adapter srst delay $args } +lappend _telnet_autocomplete_skip adapter_nsrst_assert_width proc adapter_nsrst_assert_width args { echo "DEPRECATED! use 'adapter srst pulse_width' not 'adapter_nsrst_assert_width'" eval adapter srst pulse_width $args } +lappend _telnet_autocomplete_skip interface proc interface args { echo "DEPRECATED! use 'adapter driver' not 'interface'" eval adapter driver $args } +lappend _telnet_autocomplete_skip interface_transports proc interface_transports args { echo "DEPRECATED! use 'adapter transports' not 'interface_transports'" eval adapter transports $args } +lappend _telnet_autocomplete_skip interface_list proc interface_list args { echo "DEPRECATED! use 'adapter list' not 'interface_list'" eval adapter list $args } +lappend _telnet_autocomplete_skip ftdi_location proc ftdi_location args { echo "DEPRECATED! use 'adapter usb location' not 'ftdi_location'" eval adapter usb location $args } +lappend _telnet_autocomplete_skip xds110_serial proc xds110_serial args { echo "DEPRECATED! use 'xds110 serial' not 'xds110_serial'" eval xds110 serial $args } +lappend _telnet_autocomplete_skip xds110_supply_voltage proc xds110_supply_voltage args { echo "DEPRECATED! use 'xds110 supply' not 'xds110_supply_voltage'" eval xds110 supply $args @@ -189,6 +200,7 @@ proc hla {cmd args} { tailcall "hla $cmd" {*}$args } +lappend _telnet_autocomplete_skip "hla newtap" proc "hla newtap" {args} { echo "DEPRECATED! use 'swj_newdap' not 'hla newtap'" eval swj_newdap $args diff --git a/src/server/startup.tcl b/src/server/startup.tcl index 04a1cc0..447b57c 100644 --- a/src/server/startup.tcl +++ b/src/server/startup.tcl @@ -9,6 +9,9 @@ proc ocd_gdb_restart {target_id} { reset halt } +lappend _telnet_autocomplete_skip prevent_cps +lappend _telnet_autocomplete_skip POST +lappend _telnet_autocomplete_skip Host: proc prevent_cps {} { echo "Possible SECURITY ATTACK detected." echo "It looks like somebody is sending POST or Host: commands to OpenOCD." diff --git a/src/target/startup.tcl b/src/target/startup.tcl index f128d3b..cee0366 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -208,31 +208,37 @@ proc init_board {} { } # smp_on/smp_off were already DEPRECATED in v0.11.0 through http://openocd.zylin.com/4615 +lappend _telnet_autocomplete_skip "aarch64 smp_on" proc "aarch64 smp_on" {args} { echo "DEPRECATED! use 'aarch64 smp on' not 'aarch64 smp_on'" eval aarch64 smp on $args } +lappend _telnet_autocomplete_skip "aarch64 smp_off" proc "aarch64 smp_off" {args} { echo "DEPRECATED! use 'aarch64 smp off' not 'aarch64 smp_off'" eval aarch64 smp off $args } +lappend _telnet_autocomplete_skip "cortex_a smp_on" proc "cortex_a smp_on" {args} { echo "DEPRECATED! use 'cortex_a smp on' not 'cortex_a smp_on'" eval cortex_a smp on $args } +lappend _telnet_autocomplete_skip "cortex_a smp_off" proc "cortex_a smp_off" {args} { echo "DEPRECATED! use 'cortex_a smp off' not 'cortex_a smp_off'" eval cortex_a smp off $args } +lappend _telnet_autocomplete_skip "mips_m4k smp_on" proc "mips_m4k smp_on" {args} { echo "DEPRECATED! use 'mips_m4k smp on' not 'mips_m4k smp_on'" eval mips_m4k smp on $args } +lappend _telnet_autocomplete_skip "mips_m4k smp_off" proc "mips_m4k smp_off" {args} { echo "DEPRECATED! use 'mips_m4k smp off' not 'mips_m4k smp_off'" eval mips_m4k smp off $args -- cgit v1.1 From 82b6a41117fa99e760681d9f31163e7b68357e71 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Fri, 19 Mar 2021 14:13:07 +0100 Subject: startup.tcl: prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Modify the script startup.tcl compiled-in OpenOCD binary to comply with the new jimtcl. Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6158 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Tomas Vanek --- src/jtag/startup.tcl | 5 +++-- src/target/startup.tcl | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl index c1eb2b2..3060c5c 100644 --- a/src/jtag/startup.tcl +++ b/src/jtag/startup.tcl @@ -81,9 +81,10 @@ proc srst_asserted {} { # measure actual JTAG clock proc measure_clk {} { set start_time [ms]; - set iterations 10000000; + set iterations 10000000; runtest $iterations; - echo "Running at more than [expr $iterations.0 / ([ms]-$start_time)] kHz"; + set speed [expr "$iterations.0 / ([ms] - $start_time)"] + echo "Running at more than $speed kHz"; } add_help_text measure_clk "Runs a test to measure the JTAG clk. Useful with RCLK / RTCK." diff --git a/src/target/startup.tcl b/src/target/startup.tcl index cee0366..54a3942 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -1,7 +1,7 @@ # Defines basic Tcl procs for OpenOCD target module proc new_target_name { } { - return [target number [expr [target count] - 1 ]] + return [target number [expr {[target count] - 1}]] } global in_process_reset @@ -16,7 +16,7 @@ proc ocd_process_reset { MODE } { } set in_process_reset 1 - set success [expr [catch {ocd_process_reset_inner $MODE} result]==0] + set success [expr {[catch {ocd_process_reset_inner $MODE} result] == 0}] set in_process_reset 0 if {$success} { -- cgit v1.1 From f5657aa76e795e4ed5b13a9f5df943181a123e49 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 10 Apr 2021 01:23:57 +0200 Subject: tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. In the TCL scripts distributed with OpenOCD there are 1700+ lines that should be modified before switching to jimtcl 0.81. Apply the script below on every script in tcl folder. It fixes more than 92% of the lines %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- #!/usr/bin/perl -Wpi my $re_sym = qr{[a-z_][a-z0-9_]*}i; my $re_var = qr{(?:\$|\$::)$re_sym}; my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i; my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)}; my $re_op = qr{<<|>>|[+\-*/&|]}; my $re_expr = qr{( (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item) \s*$re_op\s* (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\)) )}x; # [expr [dict get $regsC100 SYM] + HEXNUM] s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/; # [ expr (EXPR) ] # [ expr EXPR ] # note: $re_expr captures '$3' s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/; s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/; %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6159 Tested-by: jenkins Reviewed-by: Tomas Vanek --- tcl/bitsbytes.tcl | 18 +- tcl/board/at91cap7a-stk-sdram.cfg | 2 +- tcl/board/at91sam9261-ek.cfg | 30 +- tcl/board/at91sam9263-ek.cfg | 32 +- tcl/board/dm355evm.cfg | 44 +- tcl/board/dm365evm.cfg | 12 +- tcl/board/embedded-artists_lpc2478-32.cfg | 2 +- tcl/board/icnova_imx53_sodimm.cfg | 130 ++--- tcl/board/imx31pdk.cfg | 2 +- tcl/board/imx53-m53evk.cfg | 130 ++--- tcl/board/imx53loco.cfg | 130 ++--- tcl/board/mcb1700.cfg | 2 +- tcl/chip/atmel/at91/aic.tcl | 40 +- tcl/chip/atmel/at91/at91_pmc.cfg | 198 +++---- tcl/chip/atmel/at91/at91_rstc.cfg | 38 +- tcl/chip/atmel/at91/at91_wdt.cfg | 30 +- tcl/chip/atmel/at91/at91sam9261_matrix.cfg | 82 +-- tcl/chip/atmel/at91/at91sam9263_matrix.cfg | 208 +++---- tcl/chip/atmel/at91/at91sam9_init.cfg | 28 +- tcl/chip/atmel/at91/at91sam9_sdramc.cfg | 92 +-- tcl/chip/atmel/at91/at91sam9_smc.cfg | 40 +- tcl/chip/atmel/at91/rtt.tcl | 10 +- tcl/chip/atmel/at91/usarts.tcl | 26 +- tcl/chip/st/spear/quirk_no_srst.tcl | 4 +- tcl/chip/st/spear/spear3xx_ddr.tcl | 2 +- tcl/chip/st/stm32/stm32_rcc.tcl | 20 +- tcl/chip/st/stm32/stm32_regs.tcl | 130 ++--- tcl/cpu/arc/em.tcl | 2 +- tcl/cpu/arc/hs.tcl | 2 +- tcl/cpu/arc/v2.tcl | 4 +- tcl/fpga/xilinx-dna.cfg | 2 +- tcl/fpga/xilinx-xadc.cfg | 6 +- tcl/mem_helper.tcl | 2 +- tcl/memory.tcl | 8 +- tcl/mmr_helpers.tcl | 8 +- tcl/target/am335x.cfg | 4 +- tcl/target/am437x.cfg | 904 ++++++++++++++--------------- tcl/target/ampere_emag.cfg | 2 +- tcl/target/bluenrg-x.cfg | 4 +- tcl/target/c100config.tcl | 38 +- tcl/target/c100helper.tcl | 38 +- tcl/target/c100regs.tcl | 386 ++++++------ tcl/target/davinci.cfg | 200 +++---- tcl/target/fm4_mb9bf.cfg | 2 +- tcl/target/fm4_s6e2cc.cfg | 2 +- tcl/target/icepick.cfg | 2 +- tcl/target/imx.cfg | 2 +- tcl/target/ixp42x.cfg | 4 +- tcl/target/omap4430.cfg | 2 +- tcl/target/omap4460.cfg | 2 +- tcl/target/or1k.cfg | 2 +- tcl/target/pic32mx.cfg | 2 +- tcl/target/psoc5lp.cfg | 8 +- tcl/target/snps_em_sk_fpga.cfg | 2 +- tcl/target/snps_hsdk.cfg | 18 +- tcl/target/stm32h7x.cfg | 8 +- tcl/target/ti_dm355.cfg | 2 +- tcl/target/ti_dm365.cfg | 2 +- tcl/target/u8500.cfg | 4 +- tcl/test/selftest.cfg | 6 +- tcl/tools/memtest.tcl | 30 +- 61 files changed, 1596 insertions(+), 1596 deletions(-) diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl index 52ca83d..5f9cae1 100644 --- a/tcl/bitsbytes.tcl +++ b/tcl/bitsbytes.tcl @@ -5,30 +5,30 @@ # Creat helper variables ... # BIT0.. BIT31 -for { set x 0 } { $x < 32 } { set x [expr $x + 1]} { +for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} { set vn [format "BIT%d" $x] global $vn - set $vn [expr (1 << $x)] + set $vn [expr {1 << $x}] } # Create K bytes values # __1K ... to __2048K -for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} { +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { set vn [format "__%dK" $x] global $vn - set $vn [expr (1024 * $x)] + set $vn [expr {1024 * $x}] } # Create M bytes values # __1M ... to __2048K -for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} { +for { set x 1 } { $x < 2048 } { set x [expr {$x * 2}]} { set vn [format "__%dM" $x] global $vn - set $vn [expr (1024 * 1024 * $x)] + set $vn [expr {1024 * 1024 * $x}] } proc create_mask { MSB LSB } { - return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)] + return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}] } # Cut Bits $MSB to $LSB out of this value. @@ -52,8 +52,8 @@ proc normalize_bitfield { VALUE MSB LSB } { proc show_normalize_bitfield { VALUE MSB LSB } { set m [create_mask $MSB $LSB] - set mr [expr $VALUE & $m] - set sr [expr $mr >> $LSB] + set mr [expr {$VALUE & $m}] + set sr [expr {$mr >> $LSB}] echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr] return $sr } diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg index 8395ba3..8a371e0 100644 --- a/tcl/board/at91cap7a-stk-sdram.cfg +++ b/tcl/board/at91cap7a-stk-sdram.cfg @@ -38,7 +38,7 @@ proc peek32 {address} { # Wait for an expression to be true with a timeout proc wait_state {expression} { - for {set i 0} {$i < 1000} {set i [expr $i + 1]} { + for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} { if {[uplevel 1 $expression] == 0} { return } diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg index 3963e93..d6e8c2d 100644 --- a/tcl/board/at91sam9261-ek.cfg +++ b/tcl/board/at91sam9261-ek.cfg @@ -30,29 +30,29 @@ proc at91sam9261ek_reset_init { } { ;# set master_pll_mul 13 set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA - set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)] + set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] ;# SDRAMC_CR - Configuration register set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (2 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (3 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg index 645b1a7..b88efa9 100644 --- a/tcl/board/at91sam9263-ek.cfg +++ b/tcl/board/at91sam9263-ek.cfg @@ -25,10 +25,10 @@ proc at91sam9263ek_reset_init { } { set config(master_pll_mul) 171 set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable - set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value - set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt - set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt + set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt set config(wdt_mr_val) $val @@ -37,22 +37,22 @@ proc at91sam9263ek_reset_init { } { set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA set val [expr $::AT91_MATRIX_EBI0_DBPUC] - set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)] - set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)] + set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] + set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] set config(matrix_ebicsa_val) $val ;# SDRAMC_CR - Configuration register set val [expr $::AT91_SDRAMC_NC_9] - set val [expr ($val | $::AT91_SDRAMC_NR_13)] - set val [expr ($val | $::AT91_SDRAMC_NB_4)] - set val [expr ($val | $::AT91_SDRAMC_CAS_3)] - set val [expr ($val | $::AT91_SDRAMC_DBW_32)] - set val [expr ($val | (1 << 8))] ;# Write Recovery Delay - set val [expr ($val | (7 << 12))] ;# Row Cycle Delay - set val [expr ($val | (2 << 16))] ;# Row Precharge Delay - set val [expr ($val | (2 << 20))] ;# Row to Column Delay - set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay - set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay + set val [expr {$val | $::AT91_SDRAMC_NR_13}] + set val [expr {$val | $::AT91_SDRAMC_NB_4}] + set val [expr {$val | $::AT91_SDRAMC_CAS_3}] + set val [expr {$val | $::AT91_SDRAMC_DBW_32}] + set val [expr {$val | (1 << 8)}] ;# Write Recovery Delay + set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay + set val [expr {$val | (2 << 16)}] ;# Row Precharge Delay + set val [expr {$val | (2 << 20)}] ;# Row to Column Delay + set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay + set val [expr {$val | (1 << 28)}] ;# Exit Self Refresh to Active Delay set config(sdram_cr_val) $val diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 0c971e9..1e35b68 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -80,7 +80,7 @@ proc dm355evm_init {} { # VTPIOCR impedance calibration set addr [dict get $dm355 sysbase] - set addr [expr $addr + 0x70] + set addr [expr {$addr + 0x70}] # clear CLR, LOCK, PWRDN; wait a clock; set CLR mmw $addr 0 0x20c0 @@ -108,24 +108,24 @@ proc dm355evm_init {} { set addr [dict get $dm355 ddr_emif] # DDRPHYCR1 - mww [expr $addr + 0xe4] 0x50006404 + mww [expr {$addr + 0xe4}] 0x50006404 # PBBPR -- burst priority - mww [expr $addr + 0x20] 0xfe + mww [expr {$addr + 0x20}] 0xfe # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM* - mmw [expr $addr + 0x08] 0x00800000 0 - mmw [expr $addr + 0x08] 0x0013c632 0x03870fff + mmw [expr {$addr + 0x08}] 0x00800000 0 + mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff # SDTIMR0, SDTIMR1 - mww [expr $addr + 0x10] 0x2a923249 - mww [expr $addr + 0x14] 0x4c17c763 + mww [expr {$addr + 0x10}] 0x2a923249 + mww [expr {$addr + 0x14}] 0x4c17c763 # SDCR -- relock SDTIM* - mmw [expr $addr + 0x08] 0 0x00008000 + mmw [expr {$addr + 0x08}] 0 0x00008000 # SDRCR -- refresh rate (171 MHz * 7.8usec) - mww [expr $addr + 0x0c] 1336 + mww [expr {$addr + 0x0c}] 1336 ######################## # ASYNC EMIF @@ -138,13 +138,13 @@ proc dm355evm_init {} { #set nand_timings 0x0400008c # AWCCR - mww [expr $addr + 0x04] 0xff + mww [expr {$addr + 0x04}] 0xff # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte) - mww [expr $addr + 0x10] $nand_timings + mww [expr {$addr + 0x10}] $nand_timings # CS1 == dm9000 Ethernet - mww [expr $addr + 0x14] 0x00a00505 + mww [expr {$addr + 0x14}] 0x00a00505 # NANDFCR -- only CS0 has NAND - mww [expr $addr + 0x60] 0x01 + mww [expr {$addr + 0x60}] 0x01 # default: both chipselects to the NAND socket are used nand probe 0 @@ -156,27 +156,27 @@ proc dm355evm_init {} { set addr [dict get $dm355 uart0] # PWREMU_MGNT -- rx + tx in reset - mww [expr $addr + 0x30] 0 + mww [expr {$addr + 0x30}] 0 # DLL, DLH -- 115200 baud - mwb [expr $addr + 0x20] 0x0d - mwb [expr $addr + 0x24] 0x00 + mwb [expr {$addr + 0x20}] 0x0d + mwb [expr {$addr + 0x24}] 0x00 # FCR - clear and disable FIFOs - mwb [expr $addr + 0x08] 0x07 - mwb [expr $addr + 0x08] 0x00 + mwb [expr {$addr + 0x08}] 0x07 + mwb [expr {$addr + 0x08}] 0x00 # IER - disable IRQs - mwb [expr $addr + 0x04] 0x00 + mwb [expr {$addr + 0x04}] 0x00 # LCR - 8-N-1 - mwb [expr $addr + 0x0c] 0x03 + mwb [expr {$addr + 0x0c}] 0x03 # MCR - no flow control or loopback - mwb [expr $addr + 0x10] 0x00 + mwb [expr {$addr + 0x10}] 0x00 # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt - mww [expr $addr + 0x30] 0xe001 + mww [expr {$addr + 0x30}] 0xe001 ######################## diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg index 3b29dd8..8c7f8c0 100644 --- a/tcl/board/dm365evm.cfg +++ b/tcl/board/dm365evm.cfg @@ -56,10 +56,10 @@ if { $CS0 == "NAND" } { #set nand_timings 0x0400008c # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes) - mww [expr $a_emif + 0x10] $nand_timings + mww [expr {$a_emif + 0x10}] $nand_timings # NANDFCR -- CS0 has NAND - mww [expr $a_emif + 0x60] 0x01 + mww [expr {$a_emif + 0x60}] 0x01 } proc flashprobe {} { nand probe 0 @@ -80,10 +80,10 @@ if { $CS0 == "NAND" } { davinci_pinmux $dm365 2 0x00000055 # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes) - mww [expr $a_emif + 0x10] 0x00000001 + mww [expr {$a_emif + 0x10}] 0x00000001 # ONENANDCTRL -- CS0 has OneNAND, enable sync reads - mww [expr $a_emif + 0x5c] 0x0441 + mww [expr {$a_emif + 0x5c}] 0x0441 } proc flashprobe {} { } } @@ -133,11 +133,11 @@ proc dm365evm_init {} { set a_emif [dict get $dm365 a_emif] # AWCCR - mww [expr $a_emif + 0x04] 0xff + mww [expr {$a_emif + 0x04}] 0xff # CS0 == NAND or OneNAND cs0_setup $a_emif # CS1 == CPLD - mww [expr $a_emif + 0x14] 0x00a00505 + mww [expr {$a_emif + 0x14}] 0x00a00505 # FIXME setup UART0 diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg index 8ef9179..abf0a5f 100644 --- a/tcl/board/embedded-artists_lpc2478-32.cfg +++ b/tcl/board/embedded-artists_lpc2478-32.cfg @@ -26,7 +26,7 @@ proc init_board {} { global _CHIPNAME # A working area will help speeding the flash programming - $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0 + $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0 # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB) flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg index af98188..0a161f6 100644 --- a/tcl/board/icnova_imx53_sodimm.cfg +++ b/tcl/board/icnova_imx53_sodimm.cfg @@ -45,7 +45,7 @@ proc sodimm_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -79,7 +79,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -93,10 +93,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -104,22 +104,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -127,52 +127,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -187,68 +187,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg index 2dce157..6c19654 100644 --- a/tcl/board/imx31pdk.cfg +++ b/tcl/board/imx31pdk.cfg @@ -6,7 +6,7 @@ $_TARGETNAME configure -event reset-init { imx31pdk_init } proc self_test {} { echo "Running 100 iterations of test." dump_image /ram/test 0x80000000 0x40000 - for {set i 0} {$i < 100} {set i [expr $i+1]} { + for {set i 0} {$i < 100} {set i [expr {$i+1}]} { echo "Iteration $i" reset init mww 0x80000000 0x12345678 0x10000 diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg index b529c49..6f4964e 100644 --- a/tcl/board/imx53-m53evk.cfg +++ b/tcl/board/imx53-m53evk.cfg @@ -44,7 +44,7 @@ proc m53evk_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -75,7 +75,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -89,10 +89,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -100,22 +100,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -123,52 +123,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -183,68 +183,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg index 91c2601..e1bc44d 100644 --- a/tcl/board/imx53loco.cfg +++ b/tcl/board/imx53loco.cfg @@ -46,7 +46,7 @@ proc loco_init { } { ; # ARM errata ID #468414 set tR [arm mrc 15 0 1 0 1] - arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit + arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit init_l2cc init_aips @@ -80,7 +80,7 @@ proc init_l2cc { } { ; #orr r0, r0, #(1 << 22) /* disable write allocate */ ; #mcr 15, 1, r0, c9, c0, 2 - arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<<22)] + arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}] } @@ -94,10 +94,10 @@ proc init_aips { } { set VAL 0x77777777 # dap apsel 1 - mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL - mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL + mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL # dap apsel 0 } @@ -105,22 +105,22 @@ proc init_aips { } { proc init_clock { } { global AIPS1_BASE_ADDR global AIPS2_BASE_ADDR - set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000] + set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}] set CLKCTL_CCSR 0x0C set CLKCTL_CBCDR 0x14 set CLKCTL_CBCMR 0x18 - set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000] - set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000] - set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000] - set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000] + set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}] + set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}] + set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}] + set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}] set CLKCTL_CSCMR1 0x1C set CLKCTL_CDHIPR 0x48 - set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000] + set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}] set CLKCTL_CSCDR1 0x24 set CLKCTL_CCDR 0x04 ; # Switch ARM to step clock - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4 return echo "not returned" @@ -128,52 +128,52 @@ proc init_clock { } { setup_pll $PLL3_BASE_ADDR 400 ; # Switch peripheral to PLL3 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)] - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}] + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL2_BASE_ADDR 400 ; # Switch peripheral to PLL2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}] - mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] ; # make sure change is effective - while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 } + while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } setup_pll $PLL3_BASE_ADDR 216 setup_pll $PLL4_BASE_ADDR 455 ; # Set the platform clock dividers - mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124 + mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124 - mww [expr $CCM_BASE_ADDR + 0x10] 0 + mww [expr {$CCM_BASE_ADDR + 0x10}] 0 ; # Switch ARM back to PLL 1. - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] ; # Restore the default values in the Gate registers - mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF + mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF - mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000 + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000 ; # for cko - for ARM div by 8 - mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0] + mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}] } @@ -188,68 +188,68 @@ proc setup_pll { PLL_ADDR CLK } { set PLL_DP_HFS_MFN 0x24 if {$CLK == 1000} { - set DP_OP [expr (10 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (12 - 1)] + set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {12 - 1}] set DP_MFN 5 } elseif {$CLK == 850} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 41 } elseif {$CLK == 800} { - set DP_OP [expr (8 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 700} { - set DP_OP [expr (7 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 7 } elseif {$CLK == 600} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 1 } elseif {$CLK == 665} { - set DP_OP [expr (6 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (96 - 1)] + set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {96 - 1}] set DP_MFN 89 } elseif {$CLK == 532} { - set DP_OP [expr (5 << 4) + ((1 - 1) << 0)] - set DP_MFD [expr (24 - 1)] + set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}] + set DP_MFD [expr {24 - 1}] set DP_MFN 13 } elseif {$CLK == 455} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (48 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {48 - 1}] set DP_MFN 71 } elseif {$CLK == 400} { - set DP_OP [expr (8 << 4) + ((2 - 1) << 0)] - set DP_MFD [expr (3 - 1)] + set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}] + set DP_MFD [expr {3 - 1}] set DP_MFN 1 } elseif {$CLK == 216} { - set DP_OP [expr (6 << 4) + ((3 - 1) << 0)] - set DP_MFD [expr (4 - 1)] + set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}] + set DP_MFD [expr {4 - 1}] set DP_MFN 3 } else { error "Error (setup_dll): clock not found!" } - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2 + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2 - mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP - mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD - mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN + mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN - mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232 - while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 } + mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 + while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } } proc CPU_2_BE_32 { L } { - return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)] + return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}] } diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg index 01080a0..a5e1902 100644 --- a/tcl/board/mcb1700.cfg +++ b/tcl/board/mcb1700.cfg @@ -55,7 +55,7 @@ $_TARGETNAME configure -event reset-init { # # global MCB1700_CCLK - adapter speed [expr $MCB1700_CCLK / 8] + adapter speed [expr {$MCB1700_CCLK / 8}] # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select # "User Flash Mode" where interrupt vectors are _not_ remapped, diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl index ba0f2a9..b0b1002 100644 --- a/tcl/chip/atmel/at91/aic.tcl +++ b/tcl/chip/atmel/at91/aic.tcl @@ -1,38 +1,38 @@ -set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ] +set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ] global AIC_SMR -set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ] +set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ] global AIC_SVR -set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ] +set AIC_IVR [expr {$AT91C_BASE_AIC + 0x00000100} ] global AIC_IVR -set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ] +set AIC_FVR [expr {$AT91C_BASE_AIC + 0x00000104} ] global AIC_FVR -set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ] +set AIC_ISR [expr {$AT91C_BASE_AIC + 0x00000108} ] global AIC_ISR -set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ] +set AIC_IPR [expr {$AT91C_BASE_AIC + 0x0000010C} ] global AIC_IPR -set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ] +set AIC_IMR [expr {$AT91C_BASE_AIC + 0x00000110} ] global AIC_IMR -set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ] +set AIC_CISR [expr {$AT91C_BASE_AIC + 0x00000114} ] global AIC_CISR -set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ] +set AIC_IECR [expr {$AT91C_BASE_AIC + 0x00000120} ] global AIC_IECR -set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ] +set AIC_IDCR [expr {$AT91C_BASE_AIC + 0x00000124} ] global AIC_IDCR -set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ] +set AIC_ICCR [expr {$AT91C_BASE_AIC + 0x00000128} ] global AIC_ICCR -set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ] +set AIC_ISCR [expr {$AT91C_BASE_AIC + 0x0000012C} ] global AIC_ISCR -set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ] +set AIC_EOICR [expr {$AT91C_BASE_AIC + 0x00000130} ] global AIC_EOICR -set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ] +set AIC_SPU [expr {$AT91C_BASE_AIC + 0x00000134} ] global AIC_SPU -set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ] +set AIC_DCR [expr {$AT91C_BASE_AIC + 0x00000138} ] global AIC_DCR -set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ] +set AIC_FFER [expr {$AT91C_BASE_AIC + 0x00000140} ] global AIC_FFER -set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ] +set AIC_FFDR [expr {$AT91C_BASE_AIC + 0x00000144} ] global AIC_FFDR -set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ] +set AIC_FFSR [expr {$AT91C_BASE_AIC + 0x00000148} ] global AIC_FFSR @@ -54,7 +54,7 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } { proc show_AIC { } { global AIC_SMR - if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] { + if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] { error [format "%s (%s)" $msg AIC_SMR] } echo "AIC_SMR: Mode & Type" @@ -71,7 +71,7 @@ proc show_AIC { } { incr x } global AIC_SVR - if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] { + if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] { error [format "%s (%s)" $msg AIC_SVR] } echo "AIC_SVR: Vectors" diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg index 88b1370..0233cb4 100644 --- a/tcl/chip/atmel/at91/at91_pmc.cfg +++ b/tcl/chip/atmel/at91/at91_pmc.cfg @@ -1,113 +1,113 @@ -set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register -set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register +set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register +set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register -set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register -set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock -set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only] -set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] -set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only] -set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only] -set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only] -set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only] -set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only] -set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0 -set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1 -set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2 -set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3 -set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only] -set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only] +set AT91_PMC_SCSR [expr {$AT91_PMC + 0x08}] ;# System Clock Status Register +set AT91_PMC_PCK [expr {1 << 0}] ;# Processor Clock +set AT91RM9200_PMC_UDP [expr {1 << 1}] ;# USB Devcice Port Clock [AT91RM9200 only] +set AT91RM9200_PMC_MCKUDP [expr {1 << 2}] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] +set AT91CAP9_PMC_DDR [expr {1 << 2}] ;# DDR Clock [CAP9 revC & some SAM9 only] +set AT91RM9200_PMC_UHP [expr {1 << 4}] ;# USB Host Port Clock [AT91RM9200 only] +set AT91SAM926x_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91SAM926x only] +set AT91CAP9_PMC_UHP [expr {1 << 6}] ;# USB Host Port Clock [AT91CAP9 only] +set AT91SAM926x_PMC_UDP [expr {1 << 7}] ;# USB Devcice Port Clock [AT91SAM926x only] +set AT91_PMC_PCK0 [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1 [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2 [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3 [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_HCK0 [expr {1 << 16}] ;# AHB Clock (USB host) [AT91SAM9261 only] +set AT91_PMC_HCK1 [expr {1 << 17}] ;# AHB Clock (LCD) [AT91SAM9261 only] -set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register -set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register -set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register +set AT91_PMC_PCER [expr {$AT91_PMC + 0x10}] ;# Peripheral Clock Enable Register +set AT91_PMC_PCDR [expr {$AT91_PMC + 0x14}] ;# Peripheral Clock Disable Register +set AT91_PMC_PCSR [expr {$AT91_PMC + 0x18}] ;# Peripheral Clock Status Register -set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9] -set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable -set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time -set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable -set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time +set AT91_CKGR_UCKR [expr {$AT91_PMC + 0x1C}] ;# UTMI Clock Register [some SAM9, CAP9] +set AT91_PMC_UPLLEN [expr {1 << 16}] ;# UTMI PLL Enable +set AT91_PMC_UPLLCOUNT [expr {0xf << 20}] ;# UTMI PLL Start-up Time +set AT91_PMC_BIASEN [expr {1 << 24}] ;# UTMI BIAS Enable +set AT91_PMC_BIASCOUNT [expr {0xf << 28}] ;# UTMI BIAS Start-up Time -set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL] -set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable -set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9] -set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time +set AT91_CKGR_MOR [expr {$AT91_PMC + 0x20}] ;# Main Oscillator Register [not on SAM9RL] +set AT91_PMC_MOSCEN [expr {1 << 0}] ;# Main Oscillator Enable +set AT91_PMC_OSCBYPASS [expr {1 << 1}] ;# Oscillator Bypass [SAM9x, CAP9] +set AT91_PMC_OSCOUNT [expr {0xff << 8}] ;# Main Oscillator Start-up Time -set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register -set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency -set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready +set AT91_CKGR_MCFR [expr {$AT91_PMC + 0x24}] ;# Main Clock Frequency Register +set AT91_PMC_MAINF [expr {0xffff << 0}] ;# Main Clock Frequency +set AT91_PMC_MAINRDY [expr {1 << 16}] ;# Main Clock Ready -set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register -set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register -set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider -set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter -set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range -set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier -set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only) -set AT91_PMC_USBDIV_1 [expr (0 << 28)] -set AT91_PMC_USBDIV_2 [expr (1 << 28)] -set AT91_PMC_USBDIV_4 [expr (2 << 28)] -set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only) -set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register +set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register +set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register +set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider +set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter +set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range +set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier +set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only) +set AT91_PMC_USBDIV_1 [expr {0 << 28}] +set AT91_PMC_USBDIV_2 [expr {1 << 28}] +set AT91_PMC_USBDIV_4 [expr {2 << 28}] +set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only) +set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register -set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register -set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection -set AT91_PMC_CSS_SLOW [expr (0 << 0)] -set AT91_PMC_CSS_MAIN [expr (1 << 0)] -set AT91_PMC_CSS_PLLA [expr (2 << 0)] -set AT91_PMC_CSS_PLLB [expr (3 << 0)] -set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only] -set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler -set AT91_PMC_PRES_1 [expr (0 << 2)] -set AT91_PMC_PRES_2 [expr (1 << 2)] -set AT91_PMC_PRES_4 [expr (2 << 2)] -set AT91_PMC_PRES_8 [expr (3 << 2)] -set AT91_PMC_PRES_16 [expr (4 << 2)] -set AT91_PMC_PRES_32 [expr (5 << 2)] -set AT91_PMC_PRES_64 [expr (6 << 2)] -set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division -set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only] -set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)] -set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)] -set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)] -set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only] -set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)] -set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)] -set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only] -set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only] -set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only] -set AT91_PMC_PDIV_1 [expr (0 << 12)] -set AT91_PMC_PDIV_2 [expr (1 << 12)] -set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only] -set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)] -set AT91_PMC_PLLADIV2_ON [expr (1 << 12)] +set AT91_PMC_MCKR [expr {$AT91_PMC + 0x30}] ;# Master Clock Register +set AT91_PMC_CSS [expr {3 << 0}] ;# Master Clock Selection +set AT91_PMC_CSS_SLOW [expr {0 << 0}] +set AT91_PMC_CSS_MAIN [expr {1 << 0}] +set AT91_PMC_CSS_PLLA [expr {2 << 0}] +set AT91_PMC_CSS_PLLB [expr {3 << 0}] +set AT91_PMC_CSS_UPLL [expr {3 << 0}] ;# [some SAM9 only] +set AT91_PMC_PRES [expr {7 << 2}] ;# Master Clock Prescaler +set AT91_PMC_PRES_1 [expr {0 << 2}] +set AT91_PMC_PRES_2 [expr {1 << 2}] +set AT91_PMC_PRES_4 [expr {2 << 2}] +set AT91_PMC_PRES_8 [expr {3 << 2}] +set AT91_PMC_PRES_16 [expr {4 << 2}] +set AT91_PMC_PRES_32 [expr {5 << 2}] +set AT91_PMC_PRES_64 [expr {6 << 2}] +set AT91_PMC_MDIV [expr {3 << 8}] ;# Master Clock Division +set AT91RM9200_PMC_MDIV_1 [expr {0 << 8}] ;# [AT91RM9200 only] +set AT91RM9200_PMC_MDIV_2 [expr {1 << 8}] +set AT91RM9200_PMC_MDIV_3 [expr {2 << 8}] +set AT91RM9200_PMC_MDIV_4 [expr {3 << 8}] +set AT91SAM9_PMC_MDIV_1 [expr {0 << 8}] ;# [SAM9,CAP9 only] +set AT91SAM9_PMC_MDIV_2 [expr {1 << 8}] +set AT91SAM9_PMC_MDIV_4 [expr {2 << 8}] +set AT91SAM9_PMC_MDIV_6 [expr {3 << 8}] ;# [some SAM9 only] +set AT91SAM9_PMC_MDIV_3 [expr {3 << 8}] ;# [some SAM9 only] +set AT91_PMC_PDIV [expr {1 << 12}] ;# Processor Clock Division [some SAM9 only] +set AT91_PMC_PDIV_1 [expr {0 << 12}] +set AT91_PMC_PDIV_2 [expr {1 << 12}] +set AT91_PMC_PLLADIV2 [expr {1 << 12}] ;# PLLA divisor by 2 [some SAM9 only] +set AT91_PMC_PLLADIV2_OFF [expr {0 << 12}] +set AT91_PMC_PLLADIV2_ON [expr {1 << 12}] -set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only] -set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection -set AT91_PMC_USBS_PLLA [expr (0 << 0)] -set AT91_PMC_USBS_UPLL [expr (1 << 0)] -set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock +set AT91_PMC_USB [expr {$AT91_PMC + 0x38}] ;# USB Clock Register [some SAM9 only] +set AT91_PMC_USBS [expr {0x1 << 0}] ;# USB OHCI Input clock selection +set AT91_PMC_USBS_PLLA [expr {0 << 0}] +set AT91_PMC_USBS_UPLL [expr {1 << 0}] +set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock ;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers -set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection -set AT91_PMC_CSSMCK_CSS [expr (0 << 8)] -set AT91_PMC_CSSMCK_MCK [expr (1 << 8)] +set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection +set AT91_PMC_CSSMCK_CSS [expr {0 << 8}] +set AT91_PMC_CSSMCK_MCK [expr {1 << 8}] -set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register -set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register -set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register -set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag -set AT91_PMC_LOCKA [expr (1 << 1)] ;# PLLA Lock -set AT91_PMC_LOCKB [expr (1 << 2)] ;# PLLB Lock -set AT91_PMC_MCKRDY [expr (1 << 3)] ;# Master Clock -set AT91_PMC_LOCKU [expr (1 << 6)] ;# UPLL Lock [some SAM9, AT91CAP9 only] -set AT91_PMC_OSCSEL [expr (1 << 7)] ;# Slow Clock Oscillator [AT91CAP9 revC only] -set AT91_PMC_PCK0RDY [expr (1 << 8)] ;# Programmable Clock 0 -set AT91_PMC_PCK1RDY [expr (1 << 9)] ;# Programmable Clock 1 -set AT91_PMC_PCK2RDY [expr (1 << 10)] ;# Programmable Clock 2 -set AT91_PMC_PCK3RDY [expr (1 << 11)] ;# Programmable Clock 3 -set AT91_PMC_IMR [expr ($AT91_PMC + 0x6c)] ;# Interrupt Mask Register +set AT91_PMC_IER [expr {$AT91_PMC + 0x60}] ;# Interrupt Enable Register +set AT91_PMC_IDR [expr {$AT91_PMC + 0x64}] ;# Interrupt Disable Register +set AT91_PMC_SR [expr {$AT91_PMC + 0x68}] ;# Status Register +set AT91_PMC_MOSCS [expr {1 << 0}] ;# MOSCS Flag +set AT91_PMC_LOCKA [expr {1 << 1}] ;# PLLA Lock +set AT91_PMC_LOCKB [expr {1 << 2}] ;# PLLB Lock +set AT91_PMC_MCKRDY [expr {1 << 3}] ;# Master Clock +set AT91_PMC_LOCKU [expr {1 << 6}] ;# UPLL Lock [some SAM9, AT91CAP9 only] +set AT91_PMC_OSCSEL [expr {1 << 7}] ;# Slow Clock Oscillator [AT91CAP9 revC only] +set AT91_PMC_PCK0RDY [expr {1 << 8}] ;# Programmable Clock 0 +set AT91_PMC_PCK1RDY [expr {1 << 9}] ;# Programmable Clock 1 +set AT91_PMC_PCK2RDY [expr {1 << 10}] ;# Programmable Clock 2 +set AT91_PMC_PCK3RDY [expr {1 << 11}] ;# Programmable Clock 3 +set AT91_PMC_IMR [expr {$AT91_PMC + 0x6c}] ;# Interrupt Mask Register -set AT91_PMC_PROT [expr ($AT91_PMC + 0xe4)] ;# Protect Register [AT91CAP9 revC only] +set AT91_PMC_PROT [expr {$AT91_PMC + 0xe4}] ;# Protect Register [AT91CAP9 revC only] set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code -set AT91_PMC_VER [expr ($AT91_PMC + 0xfc)] ;# PMC Module Version [AT91CAP9 only] +set AT91_PMC_VER [expr {$AT91_PMC + 0xfc}] ;# PMC Module Version [AT91CAP9 only] diff --git a/tcl/chip/atmel/at91/at91_rstc.cfg b/tcl/chip/atmel/at91/at91_rstc.cfg index ed60822..6673fe6 100644 --- a/tcl/chip/atmel/at91/at91_rstc.cfg +++ b/tcl/chip/atmel/at91/at91_rstc.cfg @@ -1,21 +1,21 @@ -set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register -set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset -set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset -set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset -set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password +set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register +set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset +set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset +set AT91_RSTC_EXTRST [expr {1 << 3}] ;# External Reset +set AT91_RSTC_KEY [expr {0xa5 << 24}] ;# KEY Password -set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register -set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status -set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type -set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)] -set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)] -set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)] -set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)] -set AT91_RSTC_RSTTYP_USER [expr (4 << 8)] -set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level -set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress +set AT91_RSTC_SR [expr {$AT91_RSTC + 0x04}] ;# Reset Controller Status Register +set AT91_RSTC_URSTS [expr {1 << 0}] ;# User Reset Status +set AT91_RSTC_RSTTYP [expr {7 << 8}] ;# Reset Type +set AT91_RSTC_RSTTYP_GENERAL [expr {0 << 8}] +set AT91_RSTC_RSTTYP_WAKEUP [expr {1 << 8}] +set AT91_RSTC_RSTTYP_WATCHDOG [expr {2 << 8}] +set AT91_RSTC_RSTTYP_SOFTWARE [expr {3 << 8}] +set AT91_RSTC_RSTTYP_USER [expr {4 << 8}] +set AT91_RSTC_NRSTL [expr {1 << 16}] ;# NRST Pin Level +set AT91_RSTC_SRCMP [expr {1 << 17}] ;# Software Reset Command in Progress -set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register -set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable -set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable -set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length +set AT91_RSTC_MR [expr {$AT91_RSTC + 0x08}] ;# Reset Controller Mode Register +set AT91_RSTC_URSTEN [expr {1 << 0}] ;# User Reset Enable +set AT91_RSTC_URSTIEN [expr {1 << 4}] ;# User Reset Interrupt Enable +set AT91_RSTC_ERSTL [expr {0xf << 8}] ;# External Reset Length diff --git a/tcl/chip/atmel/at91/at91_wdt.cfg b/tcl/chip/atmel/at91/at91_wdt.cfg index a263cc7..9b4e817 100644 --- a/tcl/chip/atmel/at91/at91_wdt.cfg +++ b/tcl/chip/atmel/at91/at91_wdt.cfg @@ -1,17 +1,17 @@ -set AT91_WDT_CR [expr ($AT91_WDT + 0x00)] ;# Watchdog Control Register -set AT91_WDT_WDRSTT [expr (1 << 0)] ;# Restart -set AT91_WDT_KEY [expr (0xa5 << 24)] ;# KEY Password +set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register +set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart +set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password -set AT91_WDT_MR [expr ($AT91_WDT + 0x04)] ;# Watchdog Mode Register -set AT91_WDT_WDV [expr (0xfff << 0)] ;# Counter Value -set AT91_WDT_WDFIEN [expr (1 << 12)] ;# Fault Interrupt Enable -set AT91_WDT_WDRSTEN [expr (1 << 13)] ;# Reset Processor -set AT91_WDT_WDRPROC [expr (1 << 14)] ;# Timer Restart -set AT91_WDT_WDDIS [expr (1 << 15)] ;# Watchdog Disable -set AT91_WDT_WDD [expr (0xfff << 16)] ;# Delta Value -set AT91_WDT_WDDBGHLT [expr (1 << 28)] ;# Debug Halt -set AT91_WDT_WDIDLEHLT [expr (1 << 29)] ;# Idle Halt +set AT91_WDT_MR [expr {$AT91_WDT + 0x04}] ;# Watchdog Mode Register +set AT91_WDT_WDV [expr {0xfff << 0}] ;# Counter Value +set AT91_WDT_WDFIEN [expr {1 << 12}] ;# Fault Interrupt Enable +set AT91_WDT_WDRSTEN [expr {1 << 13}] ;# Reset Processor +set AT91_WDT_WDRPROC [expr {1 << 14}] ;# Timer Restart +set AT91_WDT_WDDIS [expr {1 << 15}] ;# Watchdog Disable +set AT91_WDT_WDD [expr {0xfff << 16}] ;# Delta Value +set AT91_WDT_WDDBGHLT [expr {1 << 28}] ;# Debug Halt +set AT91_WDT_WDIDLEHLT [expr {1 << 29}] ;# Idle Halt -set AT91_WDT_SR [expr ($AT91_WDT + 0x08)] ;# Watchdog Status Register -set AT91_WDT_WDUNF [expr (1 << 0)] ;# Watchdog Underflow -set AT91_WDT_WDERR [expr (1 << 1)] ;# Watchdog Error +set AT91_WDT_SR [expr {$AT91_WDT + 0x08}] ;# Watchdog Status Register +set AT91_WDT_WDUNF [expr {1 << 0}] ;# Watchdog Underflow +set AT91_WDT_WDERR [expr {1 << 1}] ;# Watchdog Error diff --git a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg index dc8de23..238e658 100644 --- a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg +++ b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg @@ -1,46 +1,46 @@ -set AT91_MATRIX_MCFG [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register # -set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) -set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) +set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register # +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) -set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x04)] ;# Slave Configuration Register 0 -set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x08)] ;# Slave Configuration Register 1 -set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x0C)] ;# Slave Configuration Register 2 -set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x10)] ;# Slave Configuration Register 3 -set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x14)] ;# Slave Configuration Register 4 -set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst -set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type -set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)] -set AT91_MATRIX_FIXED_DEFMSTR [expr (7 << 18)] ;# Fixed Index of Default Master +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x04}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x08}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x0C}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x10}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x14}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {7 << 18}] ;# Fixed Index of Default Master -set AT91_MATRIX_TCR [expr ($AT91_MATRIX + 0x24)] ;# TCM Configuration Register -set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block -set AT91_MATRIX_ITCM_0 [expr (0 << 0)] -set AT91_MATRIX_ITCM_16 [expr (5 << 0)] -set AT91_MATRIX_ITCM_32 [expr (6 << 0)] -set AT91_MATRIX_ITCM_64 [expr (7 << 0)] -set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block -set AT91_MATRIX_DTCM_0 [expr (0 << 4)] -set AT91_MATRIX_DTCM_16 [expr (5 << 4)] -set AT91_MATRIX_DTCM_32 [expr (6 << 4)] -set AT91_MATRIX_DTCM_64 [expr (7 << 4)] +set AT91_MATRIX_TCR [expr {$AT91_MATRIX + 0x24}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_ITCM_64 [expr {7 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] +set AT91_MATRIX_DTCM_64 [expr {7 << 4}] -set AT91_MATRIX_EBICSA [expr ($AT91_MATRIX + 0x30)] ;# EBI Chip Select Assignment Register -set AT91_MATRIX_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignment -set AT91_MATRIX_CS3A_SMC [expr (0 << 3)] -set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment -set AT91_MATRIX_CS4A_SMC [expr (0 << 4)] -set AT91_MATRIX_CS4A_SMC_CF1 [expr (1 << 4)] -set AT91_MATRIX_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment -set AT91_MATRIX_CS5A_SMC [expr (0 << 5)] -set AT91_MATRIX_CS5A_SMC_CF2 [expr (1 << 5)] -set AT91_MATRIX_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBICSA [expr {$AT91_MATRIX + 0x30}] ;# EBI Chip Select Assignment Register +set AT91_MATRIX_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_USBPUCR [expr ($AT91_MATRIX + 0x34)] ;# USB Pad Pull-Up Control Register -set AT91_MATRIX_USBPUCR_PUON [expr (1 << 30)] ;# USB Device PAD Pull-up Enable +set AT91_MATRIX_USBPUCR [expr {$AT91_MATRIX + 0x34}] ;# USB Pad Pull-Up Control Register +set AT91_MATRIX_USBPUCR_PUON [expr {1 << 30}] ;# USB Device PAD Pull-up Enable diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg index f287cd9..b4a07d3 100644 --- a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg +++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg @@ -1,110 +1,110 @@ -set AT91_MATRIX_MCFG0 [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register 0 -set AT91_MATRIX_MCFG1 [expr ($AT91_MATRIX + 0x04)] ;# Master Configuration Register 1 -set AT91_MATRIX_MCFG2 [expr ($AT91_MATRIX + 0x08)] ;# Master Configuration Register 2 -set AT91_MATRIX_MCFG3 [expr ($AT91_MATRIX + 0x0C)] ;# Master Configuration Register 3 -set AT91_MATRIX_MCFG4 [expr ($AT91_MATRIX + 0x10)] ;# Master Configuration Register 4 -set AT91_MATRIX_MCFG5 [expr ($AT91_MATRIX + 0x14)] ;# Master Configuration Register 5 -set AT91_MATRIX_MCFG6 [expr ($AT91_MATRIX + 0x18)] ;# Master Configuration Register 6 -set AT91_MATRIX_MCFG7 [expr ($AT91_MATRIX + 0x1C)] ;# Master Configuration Register 7 -set AT91_MATRIX_MCFG8 [expr ($AT91_MATRIX + 0x20)] ;# Master Configuration Register 8 -set AT91_MATRIX_ULBT [expr (7 << 0)] ;# Undefined Length Burst Type -set AT91_MATRIX_ULBT_INFINITE [expr (0 << 0)] -set AT91_MATRIX_ULBT_SINGLE [expr (1 << 0)] -set AT91_MATRIX_ULBT_FOUR [expr (2 << 0)] -set AT91_MATRIX_ULBT_EIGHT [expr (3 << 0)] -set AT91_MATRIX_ULBT_SIXTEEN [expr (4 << 0)] +set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0 +set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1 +set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2 +set AT91_MATRIX_MCFG3 [expr {$AT91_MATRIX + 0x0C}] ;# Master Configuration Register 3 +set AT91_MATRIX_MCFG4 [expr {$AT91_MATRIX + 0x10}] ;# Master Configuration Register 4 +set AT91_MATRIX_MCFG5 [expr {$AT91_MATRIX + 0x14}] ;# Master Configuration Register 5 +set AT91_MATRIX_MCFG6 [expr {$AT91_MATRIX + 0x18}] ;# Master Configuration Register 6 +set AT91_MATRIX_MCFG7 [expr {$AT91_MATRIX + 0x1C}] ;# Master Configuration Register 7 +set AT91_MATRIX_MCFG8 [expr {$AT91_MATRIX + 0x20}] ;# Master Configuration Register 8 +set AT91_MATRIX_ULBT [expr {7 << 0}] ;# Undefined Length Burst Type +set AT91_MATRIX_ULBT_INFINITE [expr {0 << 0}] +set AT91_MATRIX_ULBT_SINGLE [expr {1 << 0}] +set AT91_MATRIX_ULBT_FOUR [expr {2 << 0}] +set AT91_MATRIX_ULBT_EIGHT [expr {3 << 0}] +set AT91_MATRIX_ULBT_SIXTEEN [expr {4 << 0}] -set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x40)] ;# Slave Configuration Register 0 -set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x44)] ;# Slave Configuration Register 1 -set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x48)] ;# Slave Configuration Register 2 -set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x4C)] ;# Slave Configuration Register 3 -set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x50)] ;# Slave Configuration Register 4 -set AT91_MATRIX_SCFG5 [expr ($AT91_MATRIX + 0x54)] ;# Slave Configuration Register 5 -set AT91_MATRIX_SCFG6 [expr ($AT91_MATRIX + 0x58)] ;# Slave Configuration Register 6 -set AT91_MATRIX_SCFG7 [expr ($AT91_MATRIX + 0x5C)] ;# Slave Configuration Register 7 -set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst -set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type -set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)] -set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)] -set AT91_MATRIX_FIXED_DEFMSTR [expr (0xf << 18)] ;# Fixed Index of Default Master -set AT91_MATRIX_ARBT [expr (3 << 24)] ;# Arbitration Type -set AT91_MATRIX_ARBT_ROUND_ROBIN [expr (0 << 24)] -set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)] +set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x40}] ;# Slave Configuration Register 0 +set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x44}] ;# Slave Configuration Register 1 +set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x48}] ;# Slave Configuration Register 2 +set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x4C}] ;# Slave Configuration Register 3 +set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x50}] ;# Slave Configuration Register 4 +set AT91_MATRIX_SCFG5 [expr {$AT91_MATRIX + 0x54}] ;# Slave Configuration Register 5 +set AT91_MATRIX_SCFG6 [expr {$AT91_MATRIX + 0x58}] ;# Slave Configuration Register 6 +set AT91_MATRIX_SCFG7 [expr {$AT91_MATRIX + 0x5C}] ;# Slave Configuration Register 7 +set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst +set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type +set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}] +set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}] +set AT91_MATRIX_FIXED_DEFMSTR [expr {0xf << 18}] ;# Fixed Index of Default Master +set AT91_MATRIX_ARBT [expr {3 << 24}] ;# Arbitration Type +set AT91_MATRIX_ARBT_ROUND_ROBIN [expr {0 << 24}] +set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr {1 << 24}] -set AT91_MATRIX_PRAS0 [expr ($AT91_MATRIX + 0x80)] ;# Priority Register A for Slave 0 -set AT91_MATRIX_PRBS0 [expr ($AT91_MATRIX + 0x84)] ;# Priority Register B for Slave 0 -set AT91_MATRIX_PRAS1 [expr ($AT91_MATRIX + 0x88)] ;# Priority Register A for Slave 1 -set AT91_MATRIX_PRBS1 [expr ($AT91_MATRIX + 0x8C)] ;# Priority Register B for Slave 1 -set AT91_MATRIX_PRAS2 [expr ($AT91_MATRIX + 0x90)] ;# Priority Register A for Slave 2 -set AT91_MATRIX_PRBS2 [expr ($AT91_MATRIX + 0x94)] ;# Priority Register B for Slave 2 -set AT91_MATRIX_PRAS3 [expr ($AT91_MATRIX + 0x98)] ;# Priority Register A for Slave 3 -set AT91_MATRIX_PRBS3 [expr ($AT91_MATRIX + 0x9C)] ;# Priority Register B for Slave 3 -set AT91_MATRIX_PRAS4 [expr ($AT91_MATRIX + 0xA0)] ;# Priority Register A for Slave 4 -set AT91_MATRIX_PRBS4 [expr ($AT91_MATRIX + 0xA4)] ;# Priority Register B for Slave 4 -set AT91_MATRIX_PRAS5 [expr ($AT91_MATRIX + 0xA8)] ;# Priority Register A for Slave 5 -set AT91_MATRIX_PRBS5 [expr ($AT91_MATRIX + 0xAC)] ;# Priority Register B for Slave 5 -set AT91_MATRIX_PRAS6 [expr ($AT91_MATRIX + 0xB0)] ;# Priority Register A for Slave 6 -set AT91_MATRIX_PRBS6 [expr ($AT91_MATRIX + 0xB4)] ;# Priority Register B for Slave 6 -set AT91_MATRIX_PRAS7 [expr ($AT91_MATRIX + 0xB8)] ;# Priority Register A for Slave 7 -set AT91_MATRIX_PRBS7 [expr ($AT91_MATRIX + 0xBC)] ;# Priority Register B for Slave 7 -set AT91_MATRIX_M0PR [expr (3 << 0)] ;# Master 0 Priority -set AT91_MATRIX_M1PR [expr (3 << 4)] ;# Master 1 Priority -set AT91_MATRIX_M2PR [expr (3 << 8)] ;# Master 2 Priority -set AT91_MATRIX_M3PR [expr (3 << 12)] ;# Master 3 Priority -set AT91_MATRIX_M4PR [expr (3 << 16)] ;# Master 4 Priority -set AT91_MATRIX_M5PR [expr (3 << 20)] ;# Master 5 Priority -set AT91_MATRIX_M6PR [expr (3 << 24)] ;# Master 6 Priority -set AT91_MATRIX_M7PR [expr (3 << 28)] ;# Master 7 Priority -set AT91_MATRIX_M8PR [expr (3 << 0)] ;# Master 8 Priority (in Register B) +set AT91_MATRIX_PRAS0 [expr {$AT91_MATRIX + 0x80}] ;# Priority Register A for Slave 0 +set AT91_MATRIX_PRBS0 [expr {$AT91_MATRIX + 0x84}] ;# Priority Register B for Slave 0 +set AT91_MATRIX_PRAS1 [expr {$AT91_MATRIX + 0x88}] ;# Priority Register A for Slave 1 +set AT91_MATRIX_PRBS1 [expr {$AT91_MATRIX + 0x8C}] ;# Priority Register B for Slave 1 +set AT91_MATRIX_PRAS2 [expr {$AT91_MATRIX + 0x90}] ;# Priority Register A for Slave 2 +set AT91_MATRIX_PRBS2 [expr {$AT91_MATRIX + 0x94}] ;# Priority Register B for Slave 2 +set AT91_MATRIX_PRAS3 [expr {$AT91_MATRIX + 0x98}] ;# Priority Register A for Slave 3 +set AT91_MATRIX_PRBS3 [expr {$AT91_MATRIX + 0x9C}] ;# Priority Register B for Slave 3 +set AT91_MATRIX_PRAS4 [expr {$AT91_MATRIX + 0xA0}] ;# Priority Register A for Slave 4 +set AT91_MATRIX_PRBS4 [expr {$AT91_MATRIX + 0xA4}] ;# Priority Register B for Slave 4 +set AT91_MATRIX_PRAS5 [expr {$AT91_MATRIX + 0xA8}] ;# Priority Register A for Slave 5 +set AT91_MATRIX_PRBS5 [expr {$AT91_MATRIX + 0xAC}] ;# Priority Register B for Slave 5 +set AT91_MATRIX_PRAS6 [expr {$AT91_MATRIX + 0xB0}] ;# Priority Register A for Slave 6 +set AT91_MATRIX_PRBS6 [expr {$AT91_MATRIX + 0xB4}] ;# Priority Register B for Slave 6 +set AT91_MATRIX_PRAS7 [expr {$AT91_MATRIX + 0xB8}] ;# Priority Register A for Slave 7 +set AT91_MATRIX_PRBS7 [expr {$AT91_MATRIX + 0xBC}] ;# Priority Register B for Slave 7 +set AT91_MATRIX_M0PR [expr {3 << 0}] ;# Master 0 Priority +set AT91_MATRIX_M1PR [expr {3 << 4}] ;# Master 1 Priority +set AT91_MATRIX_M2PR [expr {3 << 8}] ;# Master 2 Priority +set AT91_MATRIX_M3PR [expr {3 << 12}] ;# Master 3 Priority +set AT91_MATRIX_M4PR [expr {3 << 16}] ;# Master 4 Priority +set AT91_MATRIX_M5PR [expr {3 << 20}] ;# Master 5 Priority +set AT91_MATRIX_M6PR [expr {3 << 24}] ;# Master 6 Priority +set AT91_MATRIX_M7PR [expr {3 << 28}] ;# Master 7 Priority +set AT91_MATRIX_M8PR [expr {3 << 0}] ;# Master 8 Priority (in Register B) -set AT91_MATRIX_MRCR [expr ($AT91_MATRIX + 0x100)] ;# Master Remap Control Register -set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) -set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) -set AT91_MATRIX_RCB2 [expr (1 << 2)] -set AT91_MATRIX_RCB3 [expr (1 << 3)] -set AT91_MATRIX_RCB4 [expr (1 << 4)] -set AT91_MATRIX_RCB5 [expr (1 << 5)] -set AT91_MATRIX_RCB6 [expr (1 << 6)] -set AT91_MATRIX_RCB7 [expr (1 << 7)] -set AT91_MATRIX_RCB8 [expr (1 << 8)] +set AT91_MATRIX_MRCR [expr {$AT91_MATRIX + 0x100}] ;# Master Remap Control Register +set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) +set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master) +set AT91_MATRIX_RCB2 [expr {1 << 2}] +set AT91_MATRIX_RCB3 [expr {1 << 3}] +set AT91_MATRIX_RCB4 [expr {1 << 4}] +set AT91_MATRIX_RCB5 [expr {1 << 5}] +set AT91_MATRIX_RCB6 [expr {1 << 6}] +set AT91_MATRIX_RCB7 [expr {1 << 7}] +set AT91_MATRIX_RCB8 [expr {1 << 8}] -set AT91_MATRIX_TCMR [expr ($AT91_MATRIX + 0x114)] ;# TCM Configuration Register -set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block -set AT91_MATRIX_ITCM_0 [expr (0 << 0)] -set AT91_MATRIX_ITCM_16 [expr (5 << 0)] -set AT91_MATRIX_ITCM_32 [expr (6 << 0)] -set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block -set AT91_MATRIX_DTCM_0 [expr (0 << 4)] -set AT91_MATRIX_DTCM_16 [expr (5 << 4)] -set AT91_MATRIX_DTCM_32 [expr (6 << 4)] +set AT91_MATRIX_TCMR [expr {$AT91_MATRIX + 0x114}] ;# TCM Configuration Register +set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block +set AT91_MATRIX_ITCM_0 [expr {0 << 0}] +set AT91_MATRIX_ITCM_16 [expr {5 << 0}] +set AT91_MATRIX_ITCM_32 [expr {6 << 0}] +set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block +set AT91_MATRIX_DTCM_0 [expr {0 << 4}] +set AT91_MATRIX_DTCM_16 [expr {5 << 4}] +set AT91_MATRIX_DTCM_32 [expr {6 << 4}] -set AT91_MATRIX_EBI0CSA [expr ($AT91_MATRIX + 0x120)] ;# EBI0 Chip Select Assignment Register -set AT91_MATRIX_EBI0_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_EBI0_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_EBI0_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignmen -set AT91_MATRIX_EBI0_CS3A_SMC [expr (0 << 3)] -set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_EBI0_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment -set AT91_MATRIX_EBI0_CS4A_SMC [expr (0 << 4)] -set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr (1 << 4)] -set AT91_MATRIX_EBI0_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment -set AT91_MATRIX_EBI0_CS5A_SMC [expr (0 << 5)] -set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr (1 << 5)] -set AT91_MATRIX_EBI0_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_EBI0_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection -set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr (0 << 16)] -set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr (1 << 16)] +set AT91_MATRIX_EBI0CSA [expr {$AT91_MATRIX + 0x120}] ;# EBI0 Chip Select Assignment Register +set AT91_MATRIX_EBI0_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI0_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI0_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignmen +set AT91_MATRIX_EBI0_CS3A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI0_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment +set AT91_MATRIX_EBI0_CS4A_SMC [expr {0 << 4}] +set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr {1 << 4}] +set AT91_MATRIX_EBI0_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment +set AT91_MATRIX_EBI0_CS5A_SMC [expr {0 << 5}] +set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr {1 << 5}] +set AT91_MATRIX_EBI0_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI0_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr {1 << 16}] -set AT91_MATRIX_EBI1CSA [expr ($AT91_MATRIX + 0x124)] ;# EBI1 Chip Select Assignment Register -set AT91_MATRIX_EBI1_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment -set AT91_MATRIX_EBI1_CS1A_SMC [expr (0 << 1)] -set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr (1 << 1)] -set AT91_MATRIX_EBI1_CS2A [expr (1 << 3)] ;# Chip Select 3 Assignment -set AT91_MATRIX_EBI1_CS2A_SMC [expr (0 << 3)] -set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr (1 << 3)] -set AT91_MATRIX_EBI1_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration -set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection -set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)] -set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)] +set AT91_MATRIX_EBI1CSA [expr {$AT91_MATRIX + 0x124}] ;# EBI1 Chip Select Assignment Register +set AT91_MATRIX_EBI1_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment +set AT91_MATRIX_EBI1_CS1A_SMC [expr {0 << 1}] +set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr {1 << 1}] +set AT91_MATRIX_EBI1_CS2A [expr {1 << 3}] ;# Chip Select 3 Assignment +set AT91_MATRIX_EBI1_CS2A_SMC [expr {0 << 3}] +set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr {1 << 3}] +set AT91_MATRIX_EBI1_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration +set AT91_MATRIX_EBI1_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection +set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr {0 << 16}] +set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr {1 << 16}] diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg index 2d78d24..688cb1f 100644 --- a/tcl/chip/atmel/at91/at91sam9_init.cfg +++ b/tcl/chip/atmel/at91/at91sam9_init.cfg @@ -12,8 +12,8 @@ proc at91sam9_reset_start { } { halt wait_halt 10000 set rstc_mr_val [expr $::AT91_RSTC_KEY] - set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))] - set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)] + set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}] + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset. } @@ -21,14 +21,14 @@ proc at91sam9_reset_init { config } { mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog - set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))] + set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}] mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc. while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 } set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog - set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)] - set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)] + set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}] + set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}] set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)] set pllar_val [expr ($pllar_val | $config(master_pll_div))] @@ -37,9 +37,9 @@ proc at91sam9_reset_init { config } { ;# PCK/2 = MCK Master Clock from PLLA set mckr_val [expr $::AT91_PMC_CSS_PLLA] - set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)] - set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)] - set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)] + set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}] + set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}] + set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}] mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 } @@ -51,19 +51,19 @@ proc at91sam9_reset_init { config } { arm7_9 fast_memory_access enable set rstc_mr_val [expr ($::AT91_RSTC_KEY)] - set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)] + set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable if { [info exists config(sdram_piod)] } { - set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)] - set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)] - set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)] + set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}] + set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}] mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] mww $asr_addr 0xffff0000 } else { - set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)] - set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)] + set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}] + set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}] mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16] mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16] } diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg index dbca497..7b09369 100644 --- a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg +++ b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg @@ -1,7 +1,7 @@ # SDRAM Controller (SDRAMC) registers -set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register -set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode +set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register +set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode set AT91_SDRAMC_MODE_NORMAL 0 set AT91_SDRAMC_MODE_NOP 1 set AT91_SDRAMC_MODE_PRECHARGE 2 @@ -10,57 +10,57 @@ set AT91_SDRAMC_MODE_REFRESH 4 set AT91_SDRAMC_MODE_EXT_LMR 5 set AT91_SDRAMC_MODE_DEEP 6 -set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register -set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter +set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register +set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter -set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register -set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits -set AT91_SDRAMC_NC_8 [expr (0 << 0)] -set AT91_SDRAMC_NC_9 [expr (1 << 0)] -set AT91_SDRAMC_NC_10 [expr (2 << 0)] -set AT91_SDRAMC_NC_11 [expr (3 << 0)] -set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits -set AT91_SDRAMC_NR_11 [expr (0 << 2)] -set AT91_SDRAMC_NR_12 [expr (1 << 2)] -set AT91_SDRAMC_NR_13 [expr (2 << 2)] -set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks -set AT91_SDRAMC_NB_2 [expr (0 << 4)] -set AT91_SDRAMC_NB_4 [expr (1 << 4)] -set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency -set AT91_SDRAMC_CAS_1 [expr (1 << 5)] -set AT91_SDRAMC_CAS_2 [expr (2 << 5)] -set AT91_SDRAMC_CAS_3 [expr (3 << 5)] -set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width -set AT91_SDRAMC_DBW_32 [expr (0 << 7)] -set AT91_SDRAMC_DBW_16 [expr (1 << 7)] -set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay -set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay -set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay -set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay -set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay -set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay +set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register +set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits +set AT91_SDRAMC_NC_8 [expr {0 << 0}] +set AT91_SDRAMC_NC_9 [expr {1 << 0}] +set AT91_SDRAMC_NC_10 [expr {2 << 0}] +set AT91_SDRAMC_NC_11 [expr {3 << 0}] +set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits +set AT91_SDRAMC_NR_11 [expr {0 << 2}] +set AT91_SDRAMC_NR_12 [expr {1 << 2}] +set AT91_SDRAMC_NR_13 [expr {2 << 2}] +set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks +set AT91_SDRAMC_NB_2 [expr {0 << 4}] +set AT91_SDRAMC_NB_4 [expr {1 << 4}] +set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency +set AT91_SDRAMC_CAS_1 [expr {1 << 5}] +set AT91_SDRAMC_CAS_2 [expr {2 << 5}] +set AT91_SDRAMC_CAS_3 [expr {3 << 5}] +set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width +set AT91_SDRAMC_DBW_32 [expr {0 << 7}] +set AT91_SDRAMC_DBW_16 [expr {1 << 7}] +set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay +set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay +set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay +set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay +set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay +set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay -set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register -set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations +set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register +set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations set AT91_SDRAMC_LPCB_DISABLE 0 set AT91_SDRAMC_LPCB_SELF_REFRESH 1 set AT91_SDRAMC_LPCB_POWER_DOWN 2 set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh -set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh -set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength -set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled -set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)] -set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)] -set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)] +set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh +set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh +set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength +set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled +set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}] +set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}] +set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}] -set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register -set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register -set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register -set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register -set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status +set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register +set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register +set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register +set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register +set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status -set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register -set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type +set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register +set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type set AT91_SDRAMC_MD_SDRAM 0 set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 diff --git a/tcl/chip/atmel/at91/at91sam9_smc.cfg b/tcl/chip/atmel/at91/at91sam9_smc.cfg index 7dc7638..3a76d14 100644 --- a/tcl/chip/atmel/at91/at91sam9_smc.cfg +++ b/tcl/chip/atmel/at91/at91sam9_smc.cfg @@ -1,20 +1,20 @@ -set AT91_SMC_READMODE [expr (1 << 0)] ;# Read Mode -set AT91_SMC_WRITEMODE [expr (1 << 1)] ;# Write Mode -set AT91_SMC_EXNWMODE [expr (3 << 4)] ;# NWAIT Mode -set AT91_SMC_EXNWMODE_DISABLE [expr (0 << 4)] -set AT91_SMC_EXNWMODE_FROZEN [expr (2 << 4)] -set AT91_SMC_EXNWMODE_READY [expr (3 << 4)] -set AT91_SMC_BAT [expr (1 << 8)] ;# Byte Access Type -set AT91_SMC_BAT_SELECT [expr (0 << 8)] -set AT91_SMC_BAT_WRITE [expr (1 << 8)] -set AT91_SMC_DBW [expr (3 << 12)] ;# Data Bus Width */ -set AT91_SMC_DBW_8 [expr (0 << 12)] -set AT91_SMC_DBW_16 [expr (1 << 12)] -set AT91_SMC_DBW_32 [expr (2 << 12)] -set AT91_SMC_TDFMODE [expr (1 << 20)] ;# TDF Optimization - Enabled -set AT91_SMC_PMEN [expr (1 << 24)] ;# Page Mode Enabled -set AT91_SMC_PS [expr (3 << 28)] ;# Page Size -set AT91_SMC_PS_4 [expr (0 << 28)] -set AT91_SMC_PS_8 [expr (1 << 28)] -set AT91_SMC_PS_16 [expr (2 << 28)] -set AT91_SMC_PS_32 [expr (3 << 28)] +set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode +set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode +set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode +set AT91_SMC_EXNWMODE_DISABLE [expr {0 << 4}] +set AT91_SMC_EXNWMODE_FROZEN [expr {2 << 4}] +set AT91_SMC_EXNWMODE_READY [expr {3 << 4}] +set AT91_SMC_BAT [expr {1 << 8}] ;# Byte Access Type +set AT91_SMC_BAT_SELECT [expr {0 << 8}] +set AT91_SMC_BAT_WRITE [expr {1 << 8}] +set AT91_SMC_DBW [expr {3 << 12}] ;# Data Bus Width */ +set AT91_SMC_DBW_8 [expr {0 << 12}] +set AT91_SMC_DBW_16 [expr {1 << 12}] +set AT91_SMC_DBW_32 [expr {2 << 12}] +set AT91_SMC_TDFMODE [expr {1 << 20}] ;# TDF Optimization - Enabled +set AT91_SMC_PMEN [expr {1 << 24}] ;# Page Mode Enabled +set AT91_SMC_PS [expr {3 << 28}] ;# Page Size +set AT91_SMC_PS_4 [expr {0 << 28}] +set AT91_SMC_PS_8 [expr {1 << 28}] +set AT91_SMC_PS_16 [expr {2 << 28}] +set AT91_SMC_PS_32 [expr {3 << 28}] diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl index 2dd74fa..3e3d414 100644 --- a/tcl/chip/atmel/at91/rtt.tcl +++ b/tcl/chip/atmel/at91/rtt.tcl @@ -1,15 +1,15 @@ -set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00] -set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04] -set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08] -set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c] +set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}] +set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}] +set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}] +set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}] global RTTC_RTMR global RTTC_RTAR global RTTC_RTVR global RTTC_RTSR proc show_RTTC_RTMR_helper { NAME ADDR VAL } { - set rtpres [expr $VAL & 0x0ffff] + set rtpres [expr {$VAL & 0x0ffff}] global BIT16 BIT17 if { $rtpres == 0 } { set rtpres 65536; diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl index ecc4f60..95aced8 100644 --- a/tcl/chip/atmel/at91/usarts.tcl +++ b/tcl/chip/atmel/at91/usarts.tcl @@ -1,20 +1,20 @@ # the DBGU and USARTs are 'almost' indentical' -set DBGU_CR [expr $AT91C_BASE_DBGU + 0x00000000] -set DBGU_MR [expr $AT91C_BASE_DBGU + 0x00000004] -set DBGU_IER [expr $AT91C_BASE_DBGU + 0x00000008] -set DBGU_IDR [expr $AT91C_BASE_DBGU + 0x0000000C] -set DBGU_IMR [expr $AT91C_BASE_DBGU + 0x00000010] -set DBGU_CSR [expr $AT91C_BASE_DBGU + 0x00000014] -set DBGU_RHR [expr $AT91C_BASE_DBGU + 0x00000018] -set DBGU_THR [expr $AT91C_BASE_DBGU + 0x0000001C] -set DBGU_BRGR [expr $AT91C_BASE_DBGU + 0x00000020] +set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}] +set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}] +set DBGU_IER [expr {$AT91C_BASE_DBGU + 0x00000008}] +set DBGU_IDR [expr {$AT91C_BASE_DBGU + 0x0000000C}] +set DBGU_IMR [expr {$AT91C_BASE_DBGU + 0x00000010}] +set DBGU_CSR [expr {$AT91C_BASE_DBGU + 0x00000014}] +set DBGU_RHR [expr {$AT91C_BASE_DBGU + 0x00000018}] +set DBGU_THR [expr {$AT91C_BASE_DBGU + 0x0000001C}] +set DBGU_BRGR [expr {$AT91C_BASE_DBGU + 0x00000020}] # no RTOR # no TTGR # no FIDI # no NER -set DBGU_CIDR [expr $AT91C_BASE_DBGU + 0x00000040] -set DBGU_EXID [expr $AT91C_BASE_DBGU + 0x00000044] -set DBGU_FNTR [expr $AT91C_BASE_DBGU + 0x00000048] +set DBGU_CIDR [expr {$AT91C_BASE_DBGU + 0x00000040}] +set DBGU_EXID [expr {$AT91C_BASE_DBGU + 0x00000044}] +set DBGU_FNTR [expr {$AT91C_BASE_DBGU + 0x00000048}] set USx_CR 0x00000000 @@ -54,7 +54,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } { 2 { set s "Force=0" } 3 { set s "Force=1" } * { - set $x [expr $x & 6] + set $x [expr {$x & 6}] switch -exact $x { 4 { set s "None" } 6 { set s "Multidrop Mode" } diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl index fd02d07..515fb58 100644 --- a/tcl/chip/st/spear/quirk_no_srst.tcl +++ b/tcl/chip/st/spear/quirk_no_srst.tcl @@ -38,8 +38,8 @@ proc sp_reset_deassert_post {} { poll on echo "====> Press reset button on the board <====" - for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} { - echo -n "$bar([expr $i & 3])\r" + for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} { + echo -n "$bar([expr {$i & 3}])\r" sleep 200 } diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl index a9787d1..22fe06e 100644 --- a/tcl/chip/st/spear/spear3xx_ddr.tcl +++ b/tcl/chip/st/spear/spear3xx_ddr.tcl @@ -28,7 +28,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} { if { $ddr_chips == 2 } { echo [format \ "Double chip DDR memory. Total memory size 0x%08x byte" \ - [expr 2 * $ddr_size]] + [expr {2 * $ddr_size}]] } else { echo [format \ "Single chip DDR memory. Memory size 0x%08x byte" \ diff --git a/tcl/chip/st/stm32/stm32_rcc.tcl b/tcl/chip/st/stm32/stm32_rcc.tcl index 07718b6..fa652a2 100644 --- a/tcl/chip/st/stm32/stm32_rcc.tcl +++ b/tcl/chip/st/stm32/stm32_rcc.tcl @@ -1,14 +1,14 @@ -set RCC_CR [expr $RCC_BASE + 0x00] -set RCC_CFGR [expr $RCC_BASE + 0x04] -set RCC_CIR [expr $RCC_BASE + 0x08] -set RCC_APB2RSTR [expr $RCC_BASE + 0x0c] -set RCC_APB1RSTR [expr $RCC_BASE + 0x10] -set RCC_AHBENR [expr $RCC_BASE + 0x14] -set RCC_APB2ENR [expr $RCC_BASE + 0x18] -set RCC_APB1ENR [expr $RCC_BASE + 0x1c] -set RCC_BDCR [expr $RCC_BASE + 0x20] -set RCC_CSR [expr $RCC_BASE + 0x24] +set RCC_CR [expr {$RCC_BASE + 0x00}] +set RCC_CFGR [expr {$RCC_BASE + 0x04}] +set RCC_CIR [expr {$RCC_BASE + 0x08}] +set RCC_APB2RSTR [expr {$RCC_BASE + 0x0c}] +set RCC_APB1RSTR [expr {$RCC_BASE + 0x10}] +set RCC_AHBENR [expr {$RCC_BASE + 0x14}] +set RCC_APB2ENR [expr {$RCC_BASE + 0x18}] +set RCC_APB1ENR [expr {$RCC_BASE + 0x1c}] +set RCC_BDCR [expr {$RCC_BASE + 0x20}] +set RCC_CSR [expr {$RCC_BASE + 0x24}] proc show_RCC_CR { } { diff --git a/tcl/chip/st/stm32/stm32_regs.tcl b/tcl/chip/st/stm32/stm32_regs.tcl index 0c1f625..6ae2f63 100644 --- a/tcl/chip/st/stm32/stm32_regs.tcl +++ b/tcl/chip/st/stm32/stm32_regs.tcl @@ -11,78 +11,78 @@ set FSMC_R_BASE 0xA0000000 # /*Peripheral memory map */ set APB1PERIPH_BASE [set PERIPH_BASE] -set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000] -set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000] +set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}] +set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}] -set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000] -set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400] -set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800] -set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00] -set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000] -set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400] -set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800] -set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00] -set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000] -set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800] -set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00] -set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400] -set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800] -set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00] -set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000] -set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400] -set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800] -set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400] -set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00] -set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000] -set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400] +set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}] +set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}] +set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}] +set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}] +set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}] +set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}] +set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}] +set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}] +set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}] +set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}] +set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}] +set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}] +set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}] +set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}] +set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}] +set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}] +set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}] +set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}] +set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}] +set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}] +set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}] -set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000] -set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400] -set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800] -set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00] -set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000] -set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400] -set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800] -set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00] -set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000] -set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400] -set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800] -set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00] -set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000] -set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400] -set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800] -set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00] +set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}] +set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}] +set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}] +set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}] +set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}] +set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}] +set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}] +set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}] +set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}] +set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}] +set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}] +set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}] +set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}] +set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}] +set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}] +set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}] -set SDIO_BASE [expr $PERIPH_BASE + 0x18000] +set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}] -set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000] -set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008] -set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C] -set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030] -set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044] -set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058] -set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C] -set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080] -set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400] -set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408] -set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C] -set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430] -set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444] -set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458] -set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000] -set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000] +set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}] +set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}] +set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}] +set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}] +set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}] +set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}] +set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}] +set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}] +set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}] +set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}] +set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}] +set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}] +set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}] +set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}] +set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}] +set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}] # /*Flash registers base address */ -set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000] +set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}] # /*Flash Option Bytes base address */ set OB_BASE 0x1FFFF800 # /*FSMC Bankx registers base address */ -set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000] -set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104] -set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060] -set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080] -set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0] +set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}] +set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}] +set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}] +set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}] +set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}] # /*Debug MCU registers base address */ set DBGMCU_BASE 0xE0042000 @@ -90,6 +90,6 @@ set DBGMCU_BASE 0xE0042000 # /*System Control Space memory map */ set SCS_BASE 0xE000E000 -set SysTick_BASE [expr $SCS_BASE + 0x0010] -set NVIC_BASE [expr $SCS_BASE + 0x0100] -set SCB_BASE [expr $SCS_BASE + 0x0D00] +set SysTick_BASE [expr {$SCS_BASE + 0x0010}] +set NVIC_BASE [expr {$SCS_BASE + 0x0100}] +set SCB_BASE [expr {$SCS_BASE + 0x0D00}] diff --git a/tcl/cpu/arc/em.tcl b/tcl/cpu/arc/em.tcl index f0455bb..595a351 100644 --- a/tcl/cpu/arc/em.tcl +++ b/tcl/cpu/arc/em.tcl @@ -27,6 +27,6 @@ proc arc_em_reset { {target ""} } { # This is specific to ARC EM. set debug [arc jtag get-aux-reg 5] if { !($debug & (1 << 20)) } { - arc jtag set-aux-reg 5 [expr $debug | (1 << 20)] + arc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}] } } diff --git a/tcl/cpu/arc/hs.tcl b/tcl/cpu/arc/hs.tcl index f39f2a7..181f993 100644 --- a/tcl/cpu/arc/hs.tcl +++ b/tcl/cpu/arc/hs.tcl @@ -48,7 +48,7 @@ proc arc_hs_reset { {target ""} } { $target arc jtag set-aux-reg 0x904 1 set l2_ctrl [$target arc jtag get-aux-reg 0x903] set l2_ctrl [$target arc jtag get-aux-reg 0x903] - while { [expr $l2_ctrl & 0x100] != 0 } { + while { [expr {$l2_ctrl & 0x100}] != 0 } { set l2_ctrl [$target arc jtag get-aux-reg 0x903] } } diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl index a3172c2..364e8af 100644 --- a/tcl/cpu/arc/v2.tcl +++ b/tcl/cpu/arc/v2.tcl @@ -41,7 +41,7 @@ proc arc_v2_examine_target { {target ""} } { # 0b01 - 4 actionpoints # 0b10 - 8 actionpoints # 0b11 - reserved. - set ap_num [expr 0x2 << ($ap_build_type & 3)] + set ap_num [expr {0x2 << ($ap_build_type & 3)}] # Expression on top may produce 16 action points - which is a # reserved value for now. if { $ap_num < 16 } { @@ -341,6 +341,6 @@ proc arc_v2_reset { {target ""} } { # to write directly via JTAG layer... set num_ap [arc num-actionpoints] for {set i 0} {$i < $num_ap} {incr i} { - arc jtag set-aux-reg [expr 0x222 + $i * 3] 0 + arc jtag set-aux-reg [expr {0x222 + $i * 3}] 0 } } diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg index a1d5ba3..a805673 100644 --- a/tcl/fpga/xilinx-dna.cfg +++ b/tcl/fpga/xilinx-dna.cfg @@ -30,7 +30,7 @@ proc xilinx_get_dna {tap chip} { # Print out the "Device DNA" in the same format that impact uses. proc xilinx_print_dna {dna} { - set dna [expr $dna >> 64 - 57] + set dna [expr {$dna >> 64 - 57}] echo [format "DNA = %057b (0x%016x)" $dna $dna] } diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg index d4be4f5..043e553 100644 --- a/tcl/fpga/xilinx-xadc.cfg +++ b/tcl/fpga/xilinx-xadc.cfg @@ -118,17 +118,17 @@ proc xadc_read {tap addr} { # convert 16 bit register code from ADC measurement on # external voltages (VAUX) to Volt proc xadc_volt {code} { - return [expr $code * 1./(1 << 16)] + return [expr {$code * 1./(1 << 16)}] } # convert 16 bit temperature measurement to Celsius proc xadc_temp {code} { - return [expr $code * 503.975/(1 << 16) - 273.15] + return [expr {$code * 503.975/(1 << 16) - 273.15}] } # convert 16 bit suppply voltage measurement to Volt proc xadc_sup {code} { - return [expr $code * 3./(1 << 16)] + return [expr {$code * 3./(1 << 16)}] } # perform a single channel measurement using default settings diff --git a/tcl/mem_helper.tcl b/tcl/mem_helper.tcl index 5955793..9ea285a 100644 --- a/tcl/mem_helper.tcl +++ b/tcl/mem_helper.tcl @@ -34,7 +34,7 @@ add_help_text mrb "Returns value of byte in memory." # $reg <== ((value & ~$clearbits) | $setbits) proc mmw {reg setbits clearbits} { set old [mrw $reg] - set new [expr ($old & ~$clearbits) | $setbits] + set new [expr {($old & ~$clearbits) | $setbits}] mww $reg $new } diff --git a/tcl/memory.tcl b/tcl/memory.tcl index 3066c11..c1e012d 100644 --- a/tcl/memory.tcl +++ b/tcl/memory.tcl @@ -43,9 +43,9 @@ set RWX_NO_ACCESS 0 set RWX_X_ONLY $BIT0 set RWX_W_ONLY $BIT1 set RWX_R_ONLY $BIT2 -set RWX_RW [expr $RWX_R_ONLY + $RWX_W_ONLY] -set RWX_R_X [expr $RWX_R_ONLY + $RWX_X_ONLY] -set RWX_RWX [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY] +set RWX_RW [expr {$RWX_R_ONLY + $RWX_W_ONLY}] +set RWX_R_X [expr {$RWX_R_ONLY + $RWX_X_ONLY}] +set RWX_RWX [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}] set UNKNOWN(0,RWX) $RWX_NO_ACCESS # WIDTH - access width @@ -54,7 +54,7 @@ set ACCESS_WIDTH_NONE 0 set ACCESS_WIDTH_8 $BIT0 set ACCESS_WIDTH_16 $BIT1 set ACCESS_WIDTH_32 $BIT2 -set ACCESS_WIDTH_ANY [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32] +set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}] set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE proc iswithin { ADDRESS BASE LEN } { diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl index e6b1c67..6b2c147 100644 --- a/tcl/mmr_helpers.tcl +++ b/tcl/mmr_helpers.tcl @@ -45,14 +45,14 @@ proc show_mmr32_bits { NAMES VAL } { for { set x 24 } { $x >= 0 } { incr x -8 } { echo -n " " for { set y 7 } { $y >= 0 } { incr y -1 } { - set s $MYNAMES([expr $x + $y]) - echo -n [format "%2d: %-*s | " [expr $x + $y] $w $s ] + set s $MYNAMES([expr {$x + $y}]) + echo -n [format "%2d: %-*s | " [expr {$x + $y}] $w $s ] } echo "" echo -n " " for { set y 7 } { $y >= 0 } { incr y -1 } { - echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr $w -1] ""] + echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr {$w -1}] ""] } echo "" } @@ -60,7 +60,7 @@ proc show_mmr32_bits { NAMES VAL } { proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } { - set width [expr (($MSB - $LSB + 1) + 7) / 4] + set width [expr {(($MSB - $LSB + 1) + 7) / 4}] set nval [show_normalize_bitfield $VAL $MSB $LSB ] set name0 [lindex $FIELDVALUES 0 ] if [ string compare $name0 _NUMBER_ ] { diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index 02d8c7e..efc773d 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -85,8 +85,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000 # FIXME: unify with target/am437x.cfg source [find mem_helper.tcl] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] proc disable_watchdog { } { global WDT1_WSPR global WDT1_W_PEND_WSPR diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index 8ce0941..e0813ca 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -5,432 +5,432 @@ source [find mem_helper.tcl] ## AM437x Registers ## ############################################################################### set PRCM_BASE_ADDR 0x44df0000 -set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000] -set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004] -set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008] -set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c] -set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010] -set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300] -set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304] -set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314] -set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324] -set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400] -set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404] -set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410] -set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414] -set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424] -set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524] -set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010] -set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014] -set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800] -set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820] -set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900] -set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920] -set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00] -set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20] -set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28] -set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30] -set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38] -set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40] -set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48] -set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00] -set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20] -set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28] -set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30] -set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38] -set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40] -set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48] -set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50] -set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58] -set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60] -set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68] -set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20] -set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24] -set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c] -set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38] -set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c] -set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40] -set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48] -set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c] -set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60] -set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64] -set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c] -set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70] -set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88] -set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c] -set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0] -set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4] -set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac] -set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0] -set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8] -set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8] -set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc] -set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0] -set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4] -set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec] -set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0] -set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04] -set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08] -set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c] -set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14] -set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20] -set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24] -set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c] -set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30] -set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48] -set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c] -set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60] -set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64] -set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c] -set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70] -set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84] -set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88] -set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c] -set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0] -set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4] -set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100] -set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104] -set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108] -set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200] -set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204] -set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208] -set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c] -set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210] -set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214] -set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218] -set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c] -set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220] -set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224] -set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228] -set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c] -set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230] -set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234] -set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238] -set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c] -set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240] -set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244] -set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248] -set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250] -set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260] -set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300] -set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320] -set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400] -set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420] -set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500] -set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520] -set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800] -set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820] -set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828] -set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830] -set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838] -set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840] -set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848] -set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850] -set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858] -set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860] -set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868] -set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870] -set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878] -set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880] -set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888] -set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890] -set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898] -set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0] -set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8] -set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00] -set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20] -set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28] -set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38] -set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40] -set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48] -set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58] -set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60] -set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68] -set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00] -set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20] -set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00] -set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20] -set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28] -set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30] -set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38] -set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40] -set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48] -set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50] -set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58] -set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60] -set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68] -set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78] -set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80] -set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88] -set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90] -set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98] -set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0] -set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8] -set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0] -set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8] -set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0] -set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8] -set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0] -set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0] -set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8] -set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0] -set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00] -set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08] -set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10] -set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18] -set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20] -set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28] -set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30] -set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38] -set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40] -set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48] -set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50] -set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58] -set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60] -set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68] -set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70] -set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78] -set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80] -set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88] -set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90] -set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98] -set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0] -set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8] -set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0] -set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00] -set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20] -set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28] -set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30] -set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38] -set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200] -set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220] -set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300] -set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320] -set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400] -set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420] +set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}] +set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}] +set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}] +set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}] +set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}] +set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}] +set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}] +set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}] +set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}] +set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}] +set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}] +set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}] +set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}] +set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}] +set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}] +set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}] +set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}] +set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}] +set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}] +set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}] +set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}] +set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}] +set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}] +set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}] +set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}] +set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}] +set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}] +set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}] +set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}] +set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}] +set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}] +set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}] +set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}] +set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}] +set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}] +set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}] +set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}] +set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}] +set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}] +set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}] +set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}] +set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}] +set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}] +set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}] +set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}] +set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}] +set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}] +set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}] +set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}] +set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}] +set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}] +set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}] +set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}] +set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}] +set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}] +set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}] +set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}] +set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}] +set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}] +set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}] +set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}] +set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}] +set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}] +set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}] +set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}] +set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}] +set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}] +set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}] +set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}] +set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}] +set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}] +set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}] +set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}] +set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}] +set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}] +set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}] +set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}] +set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}] +set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}] +set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}] +set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}] +set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}] +set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}] +set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}] +set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}] +set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}] +set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}] +set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}] +set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}] +set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}] +set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}] +set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}] +set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}] +set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}] +set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}] +set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}] +set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}] +set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}] +set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}] +set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}] +set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}] +set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}] +set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}] +set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}] +set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}] +set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}] +set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}] +set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}] +set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}] +set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}] +set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}] +set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}] +set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}] +set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}] +set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}] +set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}] +set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}] +set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}] +set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}] +set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}] +set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}] +set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}] +set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}] +set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}] +set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}] +set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}] +set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}] +set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}] +set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}] +set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}] +set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}] +set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}] +set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}] +set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}] +set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}] +set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}] +set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}] +set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}] +set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}] +set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}] +set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}] +set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}] +set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}] +set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}] +set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}] +set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}] +set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}] +set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}] +set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}] +set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}] +set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}] +set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}] +set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}] +set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}] +set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}] +set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}] +set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}] +set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}] +set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}] +set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}] +set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}] +set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}] +set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}] +set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}] +set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}] +set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}] +set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}] +set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}] +set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}] +set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}] +set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}] +set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}] +set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}] +set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}] +set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}] +set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}] +set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}] +set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}] +set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}] +set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}] +set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}] +set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}] +set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}] +set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}] +set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}] +set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}] +set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}] +set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}] +set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}] +set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}] +set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}] +set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}] +set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}] +set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}] +set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}] +set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}] +set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}] +set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}] +set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}] +set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}] +set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}] +set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}] +set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}] set CONTROL_BASE_ADDR 0x44e10000 -set CONTROL_STATUS [expr $CONTROL_BASE_ADDR + 0x0040] -set DEVICE_ID [expr $CONTROL_BASE_ADDR + 0x0600] -set DEV_FEATURE [expr $CONTROL_BASE_ADDR + 0x0604] -set DEV_ATTRIBUTE [expr $CONTROL_BASE_ADDR + 0x0610] -set MAC_ID0_LO [expr $CONTROL_BASE_ADDR + 0x0630] -set MAC_ID0_HI [expr $CONTROL_BASE_ADDR + 0x0634] -set MAC_ID1_LO [expr $CONTROL_BASE_ADDR + 0x0638] -set MAC_ID1_HI [expr $CONTROL_BASE_ADDR + 0x063c] -set USB_VID_PID [expr $CONTROL_BASE_ADDR + 0x07f4] -set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr $CONTROL_BASE_ADDR + 0x0964] -set CONTROL_CONF_SPI4_CS0 [expr $CONTROL_BASE_ADDR + 0x0a5c] -set CONTROL_CONF_SPI2_SCLK [expr $CONTROL_BASE_ADDR + 0x0a60] -set CONTROL_CONF_SPI2_D0 [expr $CONTROL_BASE_ADDR + 0x0a64] -set CONTROL_CONF_XDMA_EVENT_INTR0 [expr $CONTROL_BASE_ADDR + 0x0a70] -set CONTROL_CONF_XDMA_EVENT_INTR1 [expr $CONTROL_BASE_ADDR + 0x0a74] -set CONTROL_CONF_GPMC_A0 [expr $CONTROL_BASE_ADDR + 0x0840] -set DDR_IO_CTRL [expr $CONTROL_BASE_ADDR + 0x0e04] -set VTP_CTRL_REG [expr $CONTROL_BASE_ADDR + 0x0e0c] -set VREF_CTRL [expr $CONTROL_BASE_ADDR + 0x0e14] -set DDR_CKE_CTRL [expr $CONTROL_BASE_ADDR + 0x131c] -set DDR_ADDRCTRL_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1404] -set DDR_ADDRCTRL_WD0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1408] -set DDR_ADDRCTRL_WD1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x140c] -set DDR_DATA0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1440] -set DDR_DATA1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1444] -set DDR_DATA2_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1448] -set DDR_DATA3_IOCTRL [expr $CONTROL_BASE_ADDR + 0x144c] -set EMIF_SDRAM_CONFIG_EXT [expr $CONTROL_BASE_ADDR + 0x1460] -set EMIF_SDRAM_STATUS_EXT [expr $CONTROL_BASE_ADDR + 0x1464] +set CONTROL_STATUS [expr {$CONTROL_BASE_ADDR + 0x0040}] +set DEVICE_ID [expr {$CONTROL_BASE_ADDR + 0x0600}] +set DEV_FEATURE [expr {$CONTROL_BASE_ADDR + 0x0604}] +set DEV_ATTRIBUTE [expr {$CONTROL_BASE_ADDR + 0x0610}] +set MAC_ID0_LO [expr {$CONTROL_BASE_ADDR + 0x0630}] +set MAC_ID0_HI [expr {$CONTROL_BASE_ADDR + 0x0634}] +set MAC_ID1_LO [expr {$CONTROL_BASE_ADDR + 0x0638}] +set MAC_ID1_HI [expr {$CONTROL_BASE_ADDR + 0x063c}] +set USB_VID_PID [expr {$CONTROL_BASE_ADDR + 0x07f4}] +set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr {$CONTROL_BASE_ADDR + 0x0964}] +set CONTROL_CONF_SPI4_CS0 [expr {$CONTROL_BASE_ADDR + 0x0a5c}] +set CONTROL_CONF_SPI2_SCLK [expr {$CONTROL_BASE_ADDR + 0x0a60}] +set CONTROL_CONF_SPI2_D0 [expr {$CONTROL_BASE_ADDR + 0x0a64}] +set CONTROL_CONF_XDMA_EVENT_INTR0 [expr {$CONTROL_BASE_ADDR + 0x0a70}] +set CONTROL_CONF_XDMA_EVENT_INTR1 [expr {$CONTROL_BASE_ADDR + 0x0a74}] +set CONTROL_CONF_GPMC_A0 [expr {$CONTROL_BASE_ADDR + 0x0840}] +set DDR_IO_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e04}] +set VTP_CTRL_REG [expr {$CONTROL_BASE_ADDR + 0x0e0c}] +set VREF_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e14}] +set DDR_CKE_CTRL [expr {$CONTROL_BASE_ADDR + 0x131c}] +set DDR_ADDRCTRL_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1404}] +set DDR_ADDRCTRL_WD0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1408}] +set DDR_ADDRCTRL_WD1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x140c}] +set DDR_DATA0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1440}] +set DDR_DATA1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1444}] +set DDR_DATA2_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1448}] +set DDR_DATA3_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x144c}] +set EMIF_SDRAM_CONFIG_EXT [expr {$CONTROL_BASE_ADDR + 0x1460}] +set EMIF_SDRAM_STATUS_EXT [expr {$CONTROL_BASE_ADDR + 0x1464}] set GPIO0_BASE_ADDR 0x44e07000 -set GPIO0_SYSCONFIG [expr $GPIO0_BASE_ADDR + 0x0010] -set GPIO0_SYSSTATUS [expr $GPIO0_BASE_ADDR + 0x0114] -set GPIO0_CTRL [expr $GPIO0_BASE_ADDR + 0x0130] -set GPIO0_OE [expr $GPIO0_BASE_ADDR + 0x0134] -set GPIO0_CLEARDATAOUT [expr $GPIO0_BASE_ADDR + 0x0190] -set GPIO0_SETDATAOUT [expr $GPIO0_BASE_ADDR + 0x0194] +set GPIO0_SYSCONFIG [expr {$GPIO0_BASE_ADDR + 0x0010}] +set GPIO0_SYSSTATUS [expr {$GPIO0_BASE_ADDR + 0x0114}] +set GPIO0_CTRL [expr {$GPIO0_BASE_ADDR + 0x0130}] +set GPIO0_OE [expr {$GPIO0_BASE_ADDR + 0x0134}] +set GPIO0_CLEARDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0190}] +set GPIO0_SETDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0194}] set GPIO5_BASE_ADDR 0x48322000 -set GPIO5_SYSCONFIG [expr $GPIO5_BASE_ADDR + 0x0010] -set GPIO5_SYSSTATUS [expr $GPIO5_BASE_ADDR + 0x0114] -set GPIO5_CTRL [expr $GPIO5_BASE_ADDR + 0x0130] -set GPIO5_OE [expr $GPIO5_BASE_ADDR + 0x0134] -set GPIO5_CLEARDATAOUT [expr $GPIO5_BASE_ADDR + 0x0190] -set GPIO5_SETDATAOUT [expr $GPIO5_BASE_ADDR + 0x0194] +set GPIO5_SYSCONFIG [expr {$GPIO5_BASE_ADDR + 0x0010}] +set GPIO5_SYSSTATUS [expr {$GPIO5_BASE_ADDR + 0x0114}] +set GPIO5_CTRL [expr {$GPIO5_BASE_ADDR + 0x0130}] +set GPIO5_OE [expr {$GPIO5_BASE_ADDR + 0x0134}] +set GPIO5_CLEARDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0190}] +set GPIO5_SETDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0194}] set GPIO1_BASE_ADDR 0x4804c000 -set GPIO1_SYSCONFIG [expr $GPIO1_BASE_ADDR + 0x0010] -set GPIO1_SYSSTATUS [expr $GPIO1_BASE_ADDR + 0x0114] -set GPIO1_CTRL [expr $GPIO1_BASE_ADDR + 0x0130] -set GPIO1_OE [expr $GPIO1_BASE_ADDR + 0x0134] -set GPIO1_CLEARDATAOUT [expr $GPIO1_BASE_ADDR + 0x0190] -set GPIO1_SETDATAOUT [expr $GPIO1_BASE_ADDR + 0x0194] +set GPIO1_SYSCONFIG [expr {$GPIO1_BASE_ADDR + 0x0010}] +set GPIO1_SYSSTATUS [expr {$GPIO1_BASE_ADDR + 0x0114}] +set GPIO1_CTRL [expr {$GPIO1_BASE_ADDR + 0x0130}] +set GPIO1_OE [expr {$GPIO1_BASE_ADDR + 0x0134}] +set GPIO1_CLEARDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0190}] +set GPIO1_SETDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0194}] set EMIF_BASE_ADDR 0x4c000000 -set EMIF_STATUS [expr $EMIF_BASE_ADDR + 0x0004] -set EMIF_SDRAM_CONFIG [expr $EMIF_BASE_ADDR + 0x0008] -set EMIF_SDRAM_CONFIG_2 [expr $EMIF_BASE_ADDR + 0x000c] -set EMIF_SDRAM_REF_CTRL [expr $EMIF_BASE_ADDR + 0x0010] -set EMIF_SDRAM_REF_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x0014] -set EMIF_SDRAM_TIM_1 [expr $EMIF_BASE_ADDR + 0x0018] -set EMIF_SDRAM_TIM_1_SHDW [expr $EMIF_BASE_ADDR + 0x001c] -set EMIF_SDRAM_TIM_2 [expr $EMIF_BASE_ADDR + 0x0020] -set EMIF_SDRAM_TIM_2_SHDW [expr $EMIF_BASE_ADDR + 0x0024] -set EMIF_SDRAM_TIM_3 [expr $EMIF_BASE_ADDR + 0x0028] -set EMIF_SDRAM_TIM_3_SHDW [expr $EMIF_BASE_ADDR + 0x002c] -set EMIF_LPDDR2_NVM_TIM [expr $EMIF_BASE_ADDR + 0x0030] -set EMIF_LPDDR2_NVM_TIM_SHDW [expr $EMIF_BASE_ADDR + 0x0034] -set EMIF_PWR_MGMT_CTRL [expr $EMIF_BASE_ADDR + 0x0038] -set EMIF_PWR_MGMT_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x003c] -set EMIF_LPDDR2_MODE_REG_DATA [expr $EMIF_BASE_ADDR + 0x0040] -set EMIF_LPDDR2_MODE_REG_CFG [expr $EMIF_BASE_ADDR + 0x0050] -set EMIF_OCP_CONFIG [expr $EMIF_BASE_ADDR + 0x0054] -set EMIF_OCP_CFG_VAL_1 [expr $EMIF_BASE_ADDR + 0x0058] -set EMIF_OCP_CFG_VAL_2 [expr $EMIF_BASE_ADDR + 0x005c] -set EMIF_IODFT_TLGC [expr $EMIF_BASE_ADDR + 0x0060] -set EMIF_IODFT_CTRL_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0064] -set EMIF_IODFT_ADDR_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0068] -set EMIF_IODFT_DATA_MISR_RSLT_1 [expr $EMIF_BASE_ADDR + 0x006c] -set EMIF_IODFT_DATA_MISR_RSLT_2 [expr $EMIF_BASE_ADDR + 0x0070] -set EMIF_IODFT_DATA_MISR_RSLT_3 [expr $EMIF_BASE_ADDR + 0x0074] -set EMIF_PERF_CNT_1 [expr $EMIF_BASE_ADDR + 0x0080] -set EMIF_PERF_CNT_2 [expr $EMIF_BASE_ADDR + 0x0084] -set EMIF_PERF_CNT_CFG [expr $EMIF_BASE_ADDR + 0x0088] -set EMIF_PERF_CNT_SEL [expr $EMIF_BASE_ADDR + 0x008c] -set EMIF_PERF_CNT_TIM [expr $EMIF_BASE_ADDR + 0x0090] -set EMIF_MISC_REG [expr $EMIF_BASE_ADDR + 0x0094] -set EMIF_DLL_CALIB_CTRL [expr $EMIF_BASE_ADDR + 0x0098] -set EMIF_DLL_CALIB_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x009c] -set EMIF_IRQ_EOI [expr $EMIF_BASE_ADDR + 0x00a0] -set EMIF_IRQSTATUS_RAW_SYS [expr $EMIF_BASE_ADDR + 0x00a4] -set EMIF_IRQSTATUS_SYS [expr $EMIF_BASE_ADDR + 0x00ac] -set EMIF_IRQENABLE_SET_SYS [expr $EMIF_BASE_ADDR + 0x00b4] -set EMIF_IRQENABLE_CLR_SYS [expr $EMIF_BASE_ADDR + 0x00bc] -set EMIF_ZQ_CONFIG [expr $EMIF_BASE_ADDR + 0x00c8] -set EMIF_TEMP_ALERT_CONFIG [expr $EMIF_BASE_ADDR + 0x00cc] -set EMIF_OCP_ERR_LOG [expr $EMIF_BASE_ADDR + 0x00d0] -set EMIF_RDWR_LVL_RMP_WIN [expr $EMIF_BASE_ADDR + 0x00d4] -set EMIF_RDWR_LVL_RMP_CTRL [expr $EMIF_BASE_ADDR + 0x00d8] -set EMIF_RDWR_LVL_CTRL [expr $EMIF_BASE_ADDR + 0x00dc] -set EMIF_DDR_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x00e4] -set EMIF_DDR_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x00e8] -set EMIF_DDR_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x00ec] -set EMIF_PRI_COS_MAP [expr $EMIF_BASE_ADDR + 0x0100] -set EMIF_CONNID_COS_1_MAP [expr $EMIF_BASE_ADDR + 0x0104] -set EMIF_CONNID_COS_2_MAP [expr $EMIF_BASE_ADDR + 0x0108] -set ECC_CTRL [expr $EMIF_BASE_ADDR + 0x0110] -set ECC_ADDR_RNG_1 [expr $EMIF_BASE_ADDR + 0x0114] -set ECC_ADDR_RNG_2 [expr $EMIF_BASE_ADDR + 0x0118] -set EMIF_RD_WR_EXEC_THRSH [expr $EMIF_BASE_ADDR + 0x0120] -set COS_CONFIG [expr $EMIF_BASE_ADDR + 0x0124] - -set PHY_STATUS_1 [expr $EMIF_BASE_ADDR + 0x0144] -set PHY_STATUS_2 [expr $EMIF_BASE_ADDR + 0x0148] -set PHY_STATUS_3 [expr $EMIF_BASE_ADDR + 0x014c] -set PHY_STATUS_4 [expr $EMIF_BASE_ADDR + 0x0150] -set PHY_STATUS_5 [expr $EMIF_BASE_ADDR + 0x0154] -set PHY_STATUS_6 [expr $EMIF_BASE_ADDR + 0x0158] -set PHY_STATUS_7 [expr $EMIF_BASE_ADDR + 0x015c] -set PHY_STATUS_8 [expr $EMIF_BASE_ADDR + 0x0160] -set PHY_STATUS_9 [expr $EMIF_BASE_ADDR + 0x0164] -set PHY_STATUS_10 [expr $EMIF_BASE_ADDR + 0x0168] -set PHY_STATUS_11 [expr $EMIF_BASE_ADDR + 0x016c] -set PHY_STATUS_12 [expr $EMIF_BASE_ADDR + 0x0170] -set PHY_STATUS_13 [expr $EMIF_BASE_ADDR + 0x0174] -set PHY_STATUS_14 [expr $EMIF_BASE_ADDR + 0x0178] -set PHY_STATUS_15 [expr $EMIF_BASE_ADDR + 0x017c] -set PHY_STATUS_16 [expr $EMIF_BASE_ADDR + 0x0180] -set PHY_STATUS_17 [expr $EMIF_BASE_ADDR + 0x0184] -set PHY_STATUS_18 [expr $EMIF_BASE_ADDR + 0x0188] -set PHY_STATUS_19 [expr $EMIF_BASE_ADDR + 0x018c] -set PHY_STATUS_20 [expr $EMIF_BASE_ADDR + 0x0190] -set PHY_STATUS_21 [expr $EMIF_BASE_ADDR + 0x0194] -set PHY_STATUS_22 [expr $EMIF_BASE_ADDR + 0x0198] -set PHY_STATUS_23 [expr $EMIF_BASE_ADDR + 0x019c] -set PHY_STATUS_24 [expr $EMIF_BASE_ADDR + 0x01a0] -set PHY_STATUS_25 [expr $EMIF_BASE_ADDR + 0x01a4] -set PHY_STATUS_26 [expr $EMIF_BASE_ADDR + 0x01a8] -set PHY_STATUS_27 [expr $EMIF_BASE_ADDR + 0x01ac] -set PHY_STATUS_28 [expr $EMIF_BASE_ADDR + 0x01b0] - -set EXT_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x0200] -set EXT_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x0204] -set EXT_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x0208] -set EXT_PHY_CTRL_2_SHDW [expr $EMIF_BASE_ADDR + 0x020c] -set EXT_PHY_CTRL_3 [expr $EMIF_BASE_ADDR + 0x0210] -set EXT_PHY_CTRL_3_SHDW [expr $EMIF_BASE_ADDR + 0x0214] -set EXT_PHY_CTRL_4 [expr $EMIF_BASE_ADDR + 0x0218] -set EXT_PHY_CTRL_4_SHDW [expr $EMIF_BASE_ADDR + 0x021c] -set EXT_PHY_CTRL_5 [expr $EMIF_BASE_ADDR + 0x0220] -set EXT_PHY_CTRL_5_SHDW [expr $EMIF_BASE_ADDR + 0x0224] -set EXT_PHY_CTRL_6 [expr $EMIF_BASE_ADDR + 0x0228] -set EXT_PHY_CTRL_6_SHDW [expr $EMIF_BASE_ADDR + 0x022c] -set EXT_PHY_CTRL_7 [expr $EMIF_BASE_ADDR + 0x0230] -set EXT_PHY_CTRL_7_SHDW [expr $EMIF_BASE_ADDR + 0x0234] -set EXT_PHY_CTRL_8 [expr $EMIF_BASE_ADDR + 0x0238] -set EXT_PHY_CTRL_8_SHDW [expr $EMIF_BASE_ADDR + 0x023c] -set EXT_PHY_CTRL_9 [expr $EMIF_BASE_ADDR + 0x0240] -set EXT_PHY_CTRL_9_SHDW [expr $EMIF_BASE_ADDR + 0x0244] -set EXT_PHY_CTRL_10 [expr $EMIF_BASE_ADDR + 0x0248] -set EXT_PHY_CTRL_10_SHDW [expr $EMIF_BASE_ADDR + 0x024c] -set EXT_PHY_CTRL_11 [expr $EMIF_BASE_ADDR + 0x0250] -set EXT_PHY_CTRL_11_SHDW [expr $EMIF_BASE_ADDR + 0x0254] -set EXT_PHY_CTRL_12 [expr $EMIF_BASE_ADDR + 0x0258] -set EXT_PHY_CTRL_12_SHDW [expr $EMIF_BASE_ADDR + 0x025c] -set EXT_PHY_CTRL_13 [expr $EMIF_BASE_ADDR + 0x0260] -set EXT_PHY_CTRL_13_SHDW [expr $EMIF_BASE_ADDR + 0x0264] -set EXT_PHY_CTRL_14 [expr $EMIF_BASE_ADDR + 0x0268] -set EXT_PHY_CTRL_14_SHDW [expr $EMIF_BASE_ADDR + 0x026c] -set EXT_PHY_CTRL_15 [expr $EMIF_BASE_ADDR + 0x0270] -set EXT_PHY_CTRL_15_SHDW [expr $EMIF_BASE_ADDR + 0x0274] -set EXT_PHY_CTRL_16 [expr $EMIF_BASE_ADDR + 0x0278] -set EXT_PHY_CTRL_16_SHDW [expr $EMIF_BASE_ADDR + 0x027c] -set EXT_PHY_CTRL_17 [expr $EMIF_BASE_ADDR + 0x0280] -set EXT_PHY_CTRL_17_SHDW [expr $EMIF_BASE_ADDR + 0x0284] -set EXT_PHY_CTRL_18 [expr $EMIF_BASE_ADDR + 0x0288] -set EXT_PHY_CTRL_18_SHDW [expr $EMIF_BASE_ADDR + 0x028c] -set EXT_PHY_CTRL_19 [expr $EMIF_BASE_ADDR + 0x0290] -set EXT_PHY_CTRL_19_SHDW [expr $EMIF_BASE_ADDR + 0x0294] -set EXT_PHY_CTRL_20 [expr $EMIF_BASE_ADDR + 0x0298] -set EXT_PHY_CTRL_20_SHDW [expr $EMIF_BASE_ADDR + 0x029c] -set EXT_PHY_CTRL_21 [expr $EMIF_BASE_ADDR + 0x02a0] -set EXT_PHY_CTRL_21_SHDW [expr $EMIF_BASE_ADDR + 0x02a4] -set EXT_PHY_CTRL_22 [expr $EMIF_BASE_ADDR + 0x02a8] -set EXT_PHY_CTRL_22_SHDW [expr $EMIF_BASE_ADDR + 0x02ac] -set EXT_PHY_CTRL_23 [expr $EMIF_BASE_ADDR + 0x02b0] -set EXT_PHY_CTRL_23_SHDW [expr $EMIF_BASE_ADDR + 0x02b4] -set EXT_PHY_CTRL_24 [expr $EMIF_BASE_ADDR + 0x02b8] -set EXT_PHY_CTRL_24_SHDW [expr $EMIF_BASE_ADDR + 0x02bc] -set EXT_PHY_CTRL_25 [expr $EMIF_BASE_ADDR + 0x02c0] -set EXT_PHY_CTRL_25_SHDW [expr $EMIF_BASE_ADDR + 0x02c4] -set EXT_PHY_CTRL_26 [expr $EMIF_BASE_ADDR + 0x02c8] -set EXT_PHY_CTRL_26_SHDW [expr $EMIF_BASE_ADDR + 0x02cc] -set EXT_PHY_CTRL_27 [expr $EMIF_BASE_ADDR + 0x02d0] -set EXT_PHY_CTRL_27_SHDW [expr $EMIF_BASE_ADDR + 0x02d4] -set EXT_PHY_CTRL_28 [expr $EMIF_BASE_ADDR + 0x02d8] -set EXT_PHY_CTRL_28_SHDW [expr $EMIF_BASE_ADDR + 0x02dc] -set EXT_PHY_CTRL_29 [expr $EMIF_BASE_ADDR + 0x02e0] -set EXT_PHY_CTRL_29_SHDW [expr $EMIF_BASE_ADDR + 0x02e4] -set EXT_PHY_CTRL_30 [expr $EMIF_BASE_ADDR + 0x02e8] -set EXT_PHY_CTRL_30_SHDW [expr $EMIF_BASE_ADDR + 0x02ec] -set EXT_PHY_CTRL_31 [expr $EMIF_BASE_ADDR + 0x02f0] -set EXT_PHY_CTRL_31_SHDW [expr $EMIF_BASE_ADDR + 0x02f4] -set EXT_PHY_CTRL_32 [expr $EMIF_BASE_ADDR + 0x02f8] -set EXT_PHY_CTRL_32_SHDW [expr $EMIF_BASE_ADDR + 0x02fc] -set EXT_PHY_CTRL_33 [expr $EMIF_BASE_ADDR + 0x0300] -set EXT_PHY_CTRL_33_SHDW [expr $EMIF_BASE_ADDR + 0x0304] -set EXT_PHY_CTRL_34 [expr $EMIF_BASE_ADDR + 0x0308] -set EXT_PHY_CTRL_34_SHDW [expr $EMIF_BASE_ADDR + 0x030c] -set EXT_PHY_CTRL_35 [expr $EMIF_BASE_ADDR + 0x0310] -set EXT_PHY_CTRL_35_SHDW [expr $EMIF_BASE_ADDR + 0x0314] -set EXT_PHY_CTRL_36 [expr $EMIF_BASE_ADDR + 0x0318] -set EXT_PHY_CTRL_36_SHDW [expr $EMIF_BASE_ADDR + 0x031c] +set EMIF_STATUS [expr {$EMIF_BASE_ADDR + 0x0004}] +set EMIF_SDRAM_CONFIG [expr {$EMIF_BASE_ADDR + 0x0008}] +set EMIF_SDRAM_CONFIG_2 [expr {$EMIF_BASE_ADDR + 0x000c}] +set EMIF_SDRAM_REF_CTRL [expr {$EMIF_BASE_ADDR + 0x0010}] +set EMIF_SDRAM_REF_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x0014}] +set EMIF_SDRAM_TIM_1 [expr {$EMIF_BASE_ADDR + 0x0018}] +set EMIF_SDRAM_TIM_1_SHDW [expr {$EMIF_BASE_ADDR + 0x001c}] +set EMIF_SDRAM_TIM_2 [expr {$EMIF_BASE_ADDR + 0x0020}] +set EMIF_SDRAM_TIM_2_SHDW [expr {$EMIF_BASE_ADDR + 0x0024}] +set EMIF_SDRAM_TIM_3 [expr {$EMIF_BASE_ADDR + 0x0028}] +set EMIF_SDRAM_TIM_3_SHDW [expr {$EMIF_BASE_ADDR + 0x002c}] +set EMIF_LPDDR2_NVM_TIM [expr {$EMIF_BASE_ADDR + 0x0030}] +set EMIF_LPDDR2_NVM_TIM_SHDW [expr {$EMIF_BASE_ADDR + 0x0034}] +set EMIF_PWR_MGMT_CTRL [expr {$EMIF_BASE_ADDR + 0x0038}] +set EMIF_PWR_MGMT_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x003c}] +set EMIF_LPDDR2_MODE_REG_DATA [expr {$EMIF_BASE_ADDR + 0x0040}] +set EMIF_LPDDR2_MODE_REG_CFG [expr {$EMIF_BASE_ADDR + 0x0050}] +set EMIF_OCP_CONFIG [expr {$EMIF_BASE_ADDR + 0x0054}] +set EMIF_OCP_CFG_VAL_1 [expr {$EMIF_BASE_ADDR + 0x0058}] +set EMIF_OCP_CFG_VAL_2 [expr {$EMIF_BASE_ADDR + 0x005c}] +set EMIF_IODFT_TLGC [expr {$EMIF_BASE_ADDR + 0x0060}] +set EMIF_IODFT_CTRL_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0064}] +set EMIF_IODFT_ADDR_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0068}] +set EMIF_IODFT_DATA_MISR_RSLT_1 [expr {$EMIF_BASE_ADDR + 0x006c}] +set EMIF_IODFT_DATA_MISR_RSLT_2 [expr {$EMIF_BASE_ADDR + 0x0070}] +set EMIF_IODFT_DATA_MISR_RSLT_3 [expr {$EMIF_BASE_ADDR + 0x0074}] +set EMIF_PERF_CNT_1 [expr {$EMIF_BASE_ADDR + 0x0080}] +set EMIF_PERF_CNT_2 [expr {$EMIF_BASE_ADDR + 0x0084}] +set EMIF_PERF_CNT_CFG [expr {$EMIF_BASE_ADDR + 0x0088}] +set EMIF_PERF_CNT_SEL [expr {$EMIF_BASE_ADDR + 0x008c}] +set EMIF_PERF_CNT_TIM [expr {$EMIF_BASE_ADDR + 0x0090}] +set EMIF_MISC_REG [expr {$EMIF_BASE_ADDR + 0x0094}] +set EMIF_DLL_CALIB_CTRL [expr {$EMIF_BASE_ADDR + 0x0098}] +set EMIF_DLL_CALIB_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x009c}] +set EMIF_IRQ_EOI [expr {$EMIF_BASE_ADDR + 0x00a0}] +set EMIF_IRQSTATUS_RAW_SYS [expr {$EMIF_BASE_ADDR + 0x00a4}] +set EMIF_IRQSTATUS_SYS [expr {$EMIF_BASE_ADDR + 0x00ac}] +set EMIF_IRQENABLE_SET_SYS [expr {$EMIF_BASE_ADDR + 0x00b4}] +set EMIF_IRQENABLE_CLR_SYS [expr {$EMIF_BASE_ADDR + 0x00bc}] +set EMIF_ZQ_CONFIG [expr {$EMIF_BASE_ADDR + 0x00c8}] +set EMIF_TEMP_ALERT_CONFIG [expr {$EMIF_BASE_ADDR + 0x00cc}] +set EMIF_OCP_ERR_LOG [expr {$EMIF_BASE_ADDR + 0x00d0}] +set EMIF_RDWR_LVL_RMP_WIN [expr {$EMIF_BASE_ADDR + 0x00d4}] +set EMIF_RDWR_LVL_RMP_CTRL [expr {$EMIF_BASE_ADDR + 0x00d8}] +set EMIF_RDWR_LVL_CTRL [expr {$EMIF_BASE_ADDR + 0x00dc}] +set EMIF_DDR_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x00e4}] +set EMIF_DDR_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x00e8}] +set EMIF_DDR_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x00ec}] +set EMIF_PRI_COS_MAP [expr {$EMIF_BASE_ADDR + 0x0100}] +set EMIF_CONNID_COS_1_MAP [expr {$EMIF_BASE_ADDR + 0x0104}] +set EMIF_CONNID_COS_2_MAP [expr {$EMIF_BASE_ADDR + 0x0108}] +set ECC_CTRL [expr {$EMIF_BASE_ADDR + 0x0110}] +set ECC_ADDR_RNG_1 [expr {$EMIF_BASE_ADDR + 0x0114}] +set ECC_ADDR_RNG_2 [expr {$EMIF_BASE_ADDR + 0x0118}] +set EMIF_RD_WR_EXEC_THRSH [expr {$EMIF_BASE_ADDR + 0x0120}] +set COS_CONFIG [expr {$EMIF_BASE_ADDR + 0x0124}] + +set PHY_STATUS_1 [expr {$EMIF_BASE_ADDR + 0x0144}] +set PHY_STATUS_2 [expr {$EMIF_BASE_ADDR + 0x0148}] +set PHY_STATUS_3 [expr {$EMIF_BASE_ADDR + 0x014c}] +set PHY_STATUS_4 [expr {$EMIF_BASE_ADDR + 0x0150}] +set PHY_STATUS_5 [expr {$EMIF_BASE_ADDR + 0x0154}] +set PHY_STATUS_6 [expr {$EMIF_BASE_ADDR + 0x0158}] +set PHY_STATUS_7 [expr {$EMIF_BASE_ADDR + 0x015c}] +set PHY_STATUS_8 [expr {$EMIF_BASE_ADDR + 0x0160}] +set PHY_STATUS_9 [expr {$EMIF_BASE_ADDR + 0x0164}] +set PHY_STATUS_10 [expr {$EMIF_BASE_ADDR + 0x0168}] +set PHY_STATUS_11 [expr {$EMIF_BASE_ADDR + 0x016c}] +set PHY_STATUS_12 [expr {$EMIF_BASE_ADDR + 0x0170}] +set PHY_STATUS_13 [expr {$EMIF_BASE_ADDR + 0x0174}] +set PHY_STATUS_14 [expr {$EMIF_BASE_ADDR + 0x0178}] +set PHY_STATUS_15 [expr {$EMIF_BASE_ADDR + 0x017c}] +set PHY_STATUS_16 [expr {$EMIF_BASE_ADDR + 0x0180}] +set PHY_STATUS_17 [expr {$EMIF_BASE_ADDR + 0x0184}] +set PHY_STATUS_18 [expr {$EMIF_BASE_ADDR + 0x0188}] +set PHY_STATUS_19 [expr {$EMIF_BASE_ADDR + 0x018c}] +set PHY_STATUS_20 [expr {$EMIF_BASE_ADDR + 0x0190}] +set PHY_STATUS_21 [expr {$EMIF_BASE_ADDR + 0x0194}] +set PHY_STATUS_22 [expr {$EMIF_BASE_ADDR + 0x0198}] +set PHY_STATUS_23 [expr {$EMIF_BASE_ADDR + 0x019c}] +set PHY_STATUS_24 [expr {$EMIF_BASE_ADDR + 0x01a0}] +set PHY_STATUS_25 [expr {$EMIF_BASE_ADDR + 0x01a4}] +set PHY_STATUS_26 [expr {$EMIF_BASE_ADDR + 0x01a8}] +set PHY_STATUS_27 [expr {$EMIF_BASE_ADDR + 0x01ac}] +set PHY_STATUS_28 [expr {$EMIF_BASE_ADDR + 0x01b0}] + +set EXT_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x0200}] +set EXT_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x0204}] +set EXT_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x0208}] +set EXT_PHY_CTRL_2_SHDW [expr {$EMIF_BASE_ADDR + 0x020c}] +set EXT_PHY_CTRL_3 [expr {$EMIF_BASE_ADDR + 0x0210}] +set EXT_PHY_CTRL_3_SHDW [expr {$EMIF_BASE_ADDR + 0x0214}] +set EXT_PHY_CTRL_4 [expr {$EMIF_BASE_ADDR + 0x0218}] +set EXT_PHY_CTRL_4_SHDW [expr {$EMIF_BASE_ADDR + 0x021c}] +set EXT_PHY_CTRL_5 [expr {$EMIF_BASE_ADDR + 0x0220}] +set EXT_PHY_CTRL_5_SHDW [expr {$EMIF_BASE_ADDR + 0x0224}] +set EXT_PHY_CTRL_6 [expr {$EMIF_BASE_ADDR + 0x0228}] +set EXT_PHY_CTRL_6_SHDW [expr {$EMIF_BASE_ADDR + 0x022c}] +set EXT_PHY_CTRL_7 [expr {$EMIF_BASE_ADDR + 0x0230}] +set EXT_PHY_CTRL_7_SHDW [expr {$EMIF_BASE_ADDR + 0x0234}] +set EXT_PHY_CTRL_8 [expr {$EMIF_BASE_ADDR + 0x0238}] +set EXT_PHY_CTRL_8_SHDW [expr {$EMIF_BASE_ADDR + 0x023c}] +set EXT_PHY_CTRL_9 [expr {$EMIF_BASE_ADDR + 0x0240}] +set EXT_PHY_CTRL_9_SHDW [expr {$EMIF_BASE_ADDR + 0x0244}] +set EXT_PHY_CTRL_10 [expr {$EMIF_BASE_ADDR + 0x0248}] +set EXT_PHY_CTRL_10_SHDW [expr {$EMIF_BASE_ADDR + 0x024c}] +set EXT_PHY_CTRL_11 [expr {$EMIF_BASE_ADDR + 0x0250}] +set EXT_PHY_CTRL_11_SHDW [expr {$EMIF_BASE_ADDR + 0x0254}] +set EXT_PHY_CTRL_12 [expr {$EMIF_BASE_ADDR + 0x0258}] +set EXT_PHY_CTRL_12_SHDW [expr {$EMIF_BASE_ADDR + 0x025c}] +set EXT_PHY_CTRL_13 [expr {$EMIF_BASE_ADDR + 0x0260}] +set EXT_PHY_CTRL_13_SHDW [expr {$EMIF_BASE_ADDR + 0x0264}] +set EXT_PHY_CTRL_14 [expr {$EMIF_BASE_ADDR + 0x0268}] +set EXT_PHY_CTRL_14_SHDW [expr {$EMIF_BASE_ADDR + 0x026c}] +set EXT_PHY_CTRL_15 [expr {$EMIF_BASE_ADDR + 0x0270}] +set EXT_PHY_CTRL_15_SHDW [expr {$EMIF_BASE_ADDR + 0x0274}] +set EXT_PHY_CTRL_16 [expr {$EMIF_BASE_ADDR + 0x0278}] +set EXT_PHY_CTRL_16_SHDW [expr {$EMIF_BASE_ADDR + 0x027c}] +set EXT_PHY_CTRL_17 [expr {$EMIF_BASE_ADDR + 0x0280}] +set EXT_PHY_CTRL_17_SHDW [expr {$EMIF_BASE_ADDR + 0x0284}] +set EXT_PHY_CTRL_18 [expr {$EMIF_BASE_ADDR + 0x0288}] +set EXT_PHY_CTRL_18_SHDW [expr {$EMIF_BASE_ADDR + 0x028c}] +set EXT_PHY_CTRL_19 [expr {$EMIF_BASE_ADDR + 0x0290}] +set EXT_PHY_CTRL_19_SHDW [expr {$EMIF_BASE_ADDR + 0x0294}] +set EXT_PHY_CTRL_20 [expr {$EMIF_BASE_ADDR + 0x0298}] +set EXT_PHY_CTRL_20_SHDW [expr {$EMIF_BASE_ADDR + 0x029c}] +set EXT_PHY_CTRL_21 [expr {$EMIF_BASE_ADDR + 0x02a0}] +set EXT_PHY_CTRL_21_SHDW [expr {$EMIF_BASE_ADDR + 0x02a4}] +set EXT_PHY_CTRL_22 [expr {$EMIF_BASE_ADDR + 0x02a8}] +set EXT_PHY_CTRL_22_SHDW [expr {$EMIF_BASE_ADDR + 0x02ac}] +set EXT_PHY_CTRL_23 [expr {$EMIF_BASE_ADDR + 0x02b0}] +set EXT_PHY_CTRL_23_SHDW [expr {$EMIF_BASE_ADDR + 0x02b4}] +set EXT_PHY_CTRL_24 [expr {$EMIF_BASE_ADDR + 0x02b8}] +set EXT_PHY_CTRL_24_SHDW [expr {$EMIF_BASE_ADDR + 0x02bc}] +set EXT_PHY_CTRL_25 [expr {$EMIF_BASE_ADDR + 0x02c0}] +set EXT_PHY_CTRL_25_SHDW [expr {$EMIF_BASE_ADDR + 0x02c4}] +set EXT_PHY_CTRL_26 [expr {$EMIF_BASE_ADDR + 0x02c8}] +set EXT_PHY_CTRL_26_SHDW [expr {$EMIF_BASE_ADDR + 0x02cc}] +set EXT_PHY_CTRL_27 [expr {$EMIF_BASE_ADDR + 0x02d0}] +set EXT_PHY_CTRL_27_SHDW [expr {$EMIF_BASE_ADDR + 0x02d4}] +set EXT_PHY_CTRL_28 [expr {$EMIF_BASE_ADDR + 0x02d8}] +set EXT_PHY_CTRL_28_SHDW [expr {$EMIF_BASE_ADDR + 0x02dc}] +set EXT_PHY_CTRL_29 [expr {$EMIF_BASE_ADDR + 0x02e0}] +set EXT_PHY_CTRL_29_SHDW [expr {$EMIF_BASE_ADDR + 0x02e4}] +set EXT_PHY_CTRL_30 [expr {$EMIF_BASE_ADDR + 0x02e8}] +set EXT_PHY_CTRL_30_SHDW [expr {$EMIF_BASE_ADDR + 0x02ec}] +set EXT_PHY_CTRL_31 [expr {$EMIF_BASE_ADDR + 0x02f0}] +set EXT_PHY_CTRL_31_SHDW [expr {$EMIF_BASE_ADDR + 0x02f4}] +set EXT_PHY_CTRL_32 [expr {$EMIF_BASE_ADDR + 0x02f8}] +set EXT_PHY_CTRL_32_SHDW [expr {$EMIF_BASE_ADDR + 0x02fc}] +set EXT_PHY_CTRL_33 [expr {$EMIF_BASE_ADDR + 0x0300}] +set EXT_PHY_CTRL_33_SHDW [expr {$EMIF_BASE_ADDR + 0x0304}] +set EXT_PHY_CTRL_34 [expr {$EMIF_BASE_ADDR + 0x0308}] +set EXT_PHY_CTRL_34_SHDW [expr {$EMIF_BASE_ADDR + 0x030c}] +set EXT_PHY_CTRL_35 [expr {$EMIF_BASE_ADDR + 0x0310}] +set EXT_PHY_CTRL_35_SHDW [expr {$EMIF_BASE_ADDR + 0x0314}] +set EXT_PHY_CTRL_36 [expr {$EMIF_BASE_ADDR + 0x0318}] +set EXT_PHY_CTRL_36_SHDW [expr {$EMIF_BASE_ADDR + 0x031c}] set WDT1_BASE_ADDR 0x44e35000 -set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034] -set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048] +set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}] +set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}] set RTC_BASE_ADDR 0x44e3e000 -set RTC_KICK0R [expr $RTC_BASE_ADDR + 0x6c] -set RTC_KICK1R [expr $RTC_BASE_ADDR + 0x70] +set RTC_KICK0R [expr {$RTC_BASE_ADDR + 0x6c}] +set RTC_KICK1R [expr {$RTC_BASE_ADDR + 0x70}] if { [info exists CHIPNAME] } { @@ -520,15 +520,15 @@ proc disable_watchdog { } { } proc ceil { x y } { - return [ expr ($x + $y - 1) / $y ] + return [ expr {($x + $y - 1) / $y} ] } proc device_type { } { global CONTROL_STATUS set tmp [ mrw $CONTROL_STATUS ] - set tmp [ expr $tmp & 0x700 ] - set tmp [ expr $tmp >> 8 ] + set tmp [ expr {$tmp & 0x700} ] + set tmp [ expr {$tmp >> 8} ] return $tmp } @@ -542,8 +542,8 @@ proc get_input_clock_frequency { } { } set freq [ mrw $CONTROL_STATUS ] - set freq [ expr $freq & 0x00c00000 ] - set freq [ expr $freq >> 22 ] + set freq [ expr {$freq & 0x00c00000} ] + set freq [ expr {$freq >> 22} ] switch $freq { 0 { @@ -578,12 +578,12 @@ proc mpu_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_MPU 0x4 while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_MPU $clksel - set div_m2 [ expr $div_m2 & (~0x1f) ] - set div_m2 [ expr $div_m2 | $M2 ] + set div_m2 [ expr {$div_m2 & (~0x1f)} ] + set div_m2 [ expr {$div_m2 | $M2} ] mww $CM_DIV_M2_DPLL_MPU $div_m2 mww $CM_CLKMODE_DPLL_MPU 0x7 @@ -605,8 +605,8 @@ proc core_pll_config { CLKIN N M M4 M5 M6 } { mww $CM_CLKMODE_DPLL_CORE 0x4 while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] mww $CM_CLKSEL_DPLL_CORE $clksel mww $CM_DIV_M4_DPLL_CORE $M4 mww $CM_DIV_M5_DPLL_CORE $M5 @@ -624,8 +624,8 @@ proc per_pll_config { CLKIN N M M2 } { global CM_DIV_M2_DPLL_PER global CM_IDLEST_DPLL_PER - set x [ expr $M * $CLKIN / 1000000 ] - set y [ expr ($N + 1) * 250 ] + set x [ expr {$M * $CLKIN / 1000000} ] + set y [ expr {($N + 1) * 250} ] set sd [ ceil $x $y ] set clksel [ mrw $CM_CLKSEL_DPLL_PER ] @@ -634,12 +634,12 @@ proc per_pll_config { CLKIN N M M2 } { mww $CM_CLKMODE_DPLL_PER 0x4 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { } - set clksel [ expr $clksel & (~0xff0fffff) ] - set clksel [ expr $clksel | ($M << 0x8) | $N ] - set clksel [ expr $clksel | ($sd << 24) ] + set clksel [ expr {$clksel & (~0xff0fffff)} ] + set clksel [ expr {$clksel | ($M << 0x8) | $N} ] + set clksel [ expr {$clksel | ($sd << 24)} ] mww $CM_CLKSEL_DPLL_PER $clksel - set div_m2 [ expr 0xffffff80 | $M2 ] + set div_m2 [ expr {0xffffff80 | $M2} ] mww $CM_CLKMODE_DPLL_PER 0x7 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { } @@ -660,11 +660,11 @@ proc ddr_pll_config { CLKIN N M M2 M4 } { mww $CM_CLKMODE_DPLL_DDR 0x4 while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { } - set clksel [ expr $clksel & (~0x7ffff) ] - set clksel [ expr $clksel | ($M << 8) | $N ] + set clksel [ expr {$clksel & (~0x7ffff)} ] + set clksel [ expr {$clksel | ($M << 8) | $N} ] mww $CM_CLKSEL_DPLL_DDR $clksel - set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ] + set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ] mww $CM_DIV_M2_DPLL_DDR $div_m2 mww $CM_DIV_M4_DPLL_DDR $M4 @@ -849,18 +849,18 @@ proc config_ddr_phy { } { set gatelvl_num_dq0 0x0f set wrlvl_num_dq0 0x0f - mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ] - mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] - mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ] + mww $EXT_PHY_CTRL_1 [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_1_SHDW [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ] + mww $EXT_PHY_CTRL_26 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_26_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_27_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_28_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_29_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] + mww $EXT_PHY_CTRL_30_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ] mww $EXT_PHY_CTRL_31 0x00 mww $EXT_PHY_CTRL_31_SHDW 0x00 mww $EXT_PHY_CTRL_32 0x00 @@ -873,14 +873,14 @@ proc config_ddr_phy { } { mww $EXT_PHY_CTRL_35_SHDW 0x00 mww $EXT_PHY_CTRL_22 0x00 mww $EXT_PHY_CTRL_22_SHDW 0x00 - mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ] - mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ] - mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ] - mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ] - mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] - mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ] + mww $EXT_PHY_CTRL_23 [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_23_SHDW [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ] + mww $EXT_PHY_CTRL_24 [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ] + mww $EXT_PHY_CTRL_24_SHDW [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ] + mww $EXT_PHY_CTRL_25 [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_25_SHDW [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ] + mww $EXT_PHY_CTRL_36 [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] + mww $EXT_PHY_CTRL_36_SHDW [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ] } proc config_ddr_timing { } { diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 7115a83..2e828de 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -78,7 +78,7 @@ for {set _i 0} {$_i < $_NUMCORES} {incr _i} { # Create and configure Cross Trigger Interface (CTI) - required for halt and resume set _CTINAME $_TARGETNAME.cti - cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr 0xFC020000 + ($_i << 20)] + cti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}] # Create the target target create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg index a9d321e..6647325 100644 --- a/tcl/target/bluenrg-x.cfg +++ b/tcl/target/bluenrg-x.cfg @@ -54,9 +54,9 @@ $_TARGETNAME configure -event halted { if {$_JTAG_IDCODE != 0x0201E041} { # Stop watchdog during halt, if enabled. Only Bluenrg-1/2 set WDOG_VALUE [mrw 0x40700008] - if [expr ($WDOG_VALUE & (1 << 1))] { + if [expr {$WDOG_VALUE & (1 << 1)}] { set WDOG_VALUE_SET 1 - mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)] + mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}] } } } diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index 53b2c5d..17639fd 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -111,23 +111,23 @@ proc setupGPIO {} { set GPIO_OE_REG [regs GPIO_OE_REG] # set GPIO29=GPIO17=1, GPIO5=0 - mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17] + mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}] # enable [as output] GPIO29,GPIO17,GPIO5 - mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5] + mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}] } proc highGPIO5 {} { echo "GPIO5 high" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=1 - mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0 + mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0 } proc lowGPIO5 {} { echo "GPIO5 low" set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG] # set GPIO5=0 - mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5] + mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}] } proc boardID {id} { @@ -163,7 +163,7 @@ proc ooma_board_detect {} { set tmp [mrw $GPIO_BOOTSTRAP_REG] echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] # extract the GPBP bits - set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3] + set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}] # display board ID echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt] @@ -226,13 +226,13 @@ proc configureDDR2regs_256M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } echo "done." @@ -294,16 +294,16 @@ proc configureDDR2regs_128M {} { set wr_dqs_shift 0x40 # start DDRC - mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)] + mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}] # wait int_status[2] (DRAM init complete) echo -n "Waiting for DDR2 controller to init..." - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] - while { [expr $tmp & 0x040000] == 0 } { + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] + while { [expr {$tmp & 0x040000}] == 0 } { sleep 1 - set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]] + set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]] } # This is not necessary - #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ] + #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ] echo "done." # do ddr2 training sequence @@ -341,14 +341,14 @@ proc setupUART0 {} { # Enable Divisor Latch access mmw $UART0_LCR $LCR_DLAB 0x0 # set the divisor to $tmp - mww $UART0_DLL [expr $tmp & 0xff] - mww $UART0_DLH [expr $tmp >> 8] + mww $UART0_DLL [expr {$tmp & 0xff}] + mww $UART0_DLH [expr {$tmp >> 8}] # Disable Divisor Latch access mmw $UART0_LCR 0x0 $LCR_DLAB # set the UART to 8N1 - mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0 + mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0 # reset FIFO - mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0 + mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0 # enable FFUART mww $UART0_IER $IER_UUE } @@ -372,7 +372,7 @@ proc putsUART0 {str} { set len [string length $str] while { $index < $len } { putcUART0 [string index $str $index] - set index [expr $index + 1] + set index [expr {$index + 1}] } } diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 725ba70..9b8256d 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -37,11 +37,11 @@ proc mr64bit {reg} { # write a 64-bit register (memory mapped) proc mw64bit {reg value} { - set high [expr $value >> 32] - set low [expr $value & 0xffffffff] + set high [expr {$value >> 32}] + set low [expr {$value & 0xffffffff}] #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low] mww $reg $low - mww [expr $reg+4] $high + mww [expr {$reg+4}] $high } @@ -122,7 +122,7 @@ proc showAmbaClk {} { set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. set x [expr ($value(0) & 0x0001F0000) >> 16] @@ -131,7 +131,7 @@ proc showAmbaClk {} { echo [format "y: %d" $y] set w [expr ($value(0) & 0x000000300) >> 8] echo [format "w: %d" $w] - echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -154,7 +154,7 @@ proc setupAmbaClk {} { set x [config x_amba] set y [config y_amba] - echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]] + echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]] #echo [format "setupAmbaClk: w= %d" $w] #echo [format "setupAmbaClk: x= %d" $x] #echo [format "setupAmbaClk: y= %d" $y] @@ -174,7 +174,7 @@ proc setupAmbaClk {} { sleep 1 # set X, W and X mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } @@ -197,7 +197,7 @@ proc showArmClk {} { set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { - echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]] + echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. set x [expr ($value(0) & 0x0001F0000) >> 16] @@ -206,7 +206,7 @@ proc showArmClk {} { echo [format "y: %d" $y] set w [expr ($value(0) & 0x000000300) >> 8] echo [format "w: %d" $w] - echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]] + echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } } @@ -228,7 +228,7 @@ proc setupArmClk {} { set x [config x_arm] set y [config y_arm] - echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]] + echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]] #echo [format "setupArmClk: w= %d" $w] #echo [format "setupArmaClk: x= %d" $x] #echo [format "setupArmaClk: y= %d" $y] @@ -248,7 +248,7 @@ proc setupArmClk {} { sleep 1 # set X, W and X mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF - mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0 + mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } @@ -281,11 +281,11 @@ proc setupDDR2 {} { # and not reset. mmw $BLOCK_RESET_REG 0x0 $DDR_RST - set M [expr 1024 * 1024] - set DDR_SZ_1024M [expr 1024 * $M] - set DDR_SZ_256M [expr 256 * $M] - set DDR_SZ_128M [expr 128 * $M] - set DDR_SZ_64M [expr 64 * $M] + set M [expr {1024 * 1024}] + set DDR_SZ_1024M [expr {1024 * $M}] + set DDR_SZ_256M [expr {256 * $M}] + set DDR_SZ_128M [expr {128 * $M}] + set DDR_SZ_64M [expr {64 * $M}] # ooma_board_detect returns DDR2 memory size set tmp [ooma_board_detect] if {$tmp == "128M"} { @@ -299,7 +299,7 @@ proc setupDDR2 {} { } # Memory setup register - mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR] + mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}] # disable ROM remap mww $MEMORY_CR 0x0 # Take DDR controller out of reset @@ -445,9 +445,9 @@ proc initC100 {} { mww [expr $APB_ACCESS_WS_REG] 0x40 # AHB init # // enable all 6 masters for ARAM - mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # // enable all 6 masters for EBUS - mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0 + mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 # ARAM init # // disable pipeline mode in ARAM diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl index a2c7a60..9304808 100644 --- a/tcl/target/c100regs.tcl +++ b/tcl/target/c100regs.tcl @@ -35,43 +35,43 @@ dict set regsC100 EXP_CS4_BASEADDR 0x30000000 dict set regsC100 DDR_BASEADDR 0x80000000 -dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000] -dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000] -dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000] -dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000] -dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000] -dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000] -dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000] -dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000] -dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000] -dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000] -dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000] -dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000] -dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000] -dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000] -dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000] -dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000] -dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000] -dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000] -dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000] -dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000] -dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000] -dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000] +dict set regsC100 TDM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}] +dict set regsC100 PHI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}] +dict set regsC100 TDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}] +dict set regsC100 ASA_DDR_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}] +dict set regsC100 ASA_ARAM_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}] +dict set regsC100 TIMER_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}] +dict set regsC100 ASD_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}] +dict set regsC100 GPIO_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}] +dict set regsC100 UART0_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}] +dict set regsC100 UART1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}] +dict set regsC100 SPI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}] +dict set regsC100 I2C_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}] +dict set regsC100 INTC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}] +dict set regsC100 CLKCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 PUI_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}] +dict set regsC100 GEMAC_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}] +dict set regsC100 IDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}] +dict set regsC100 MEMCORE_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}] +dict set regsC100 ASA_EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}] +dict set regsC100 ASA_AAB_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}] +dict set regsC100 GEMAC1_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}] +dict set regsC100 EBUS_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}] +dict set regsC100 MDMA_BASEADDR [expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}] #//////////////////////////////////////////////////////////// #// AHB block // #//////////////////////////////////////////////////////////// -dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00] -dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04] -dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08] -dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C] +dict set regsC100 ASA_ARAM_PRI_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}] +dict set regsC100 ASA_ARAM_TC_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}] +dict set regsC100 ASA_ARAM_TC_CR_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}] +dict set regsC100 ASA_ARAM_STAT_REG [expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}] -dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00] -dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04] -dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08] -dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C] +dict set regsC100 ASA_EBUS_PRI_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}] +dict set regsC100 ASA_EBUS_TC_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}] +dict set regsC100 ASA_EBUS_TC_CR_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}] +dict set regsC100 ASA_EBUS_STAT_REG [expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}] dict set regsC100 IDMA_MASTER 0 dict set regsC100 TDMA_MASTER 1 @@ -87,16 +87,16 @@ dict set regsC100 MDMA_MASTER 5 #define ARM1_PRIORITY(level) (level << 16) #define MDMA_PRIORITY(level) (level << 20) -dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18] -dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19] -dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20] -dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21] -dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22] -dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23] +dict set regsC100 ASA_TC_REQIDMAEN [expr {1<<18}] +dict set regsC100 ASA_TC_REQTDMEN [expr {1<<19}] +dict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}] +dict set regsC100 ASA_TC_REQARM0EN [expr {1<<21}] +dict set regsC100 ASA_TC_REQARM1EN [expr {1<<22}] +dict set regsC100 ASA_TC_REQMDMAEN [expr {1<<23}] dict set regsC100 MEMORY_BASE_ADDR 0x80000000 -dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10] -dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14] +dict set regsC100 MEMORY_MAX_ADDR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}] +dict set regsC100 MEMORY_CR [expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}] dict set regsC100 ROM_REMAP_EN 0x1 #define HAL_asb_priority(level) \ @@ -115,33 +115,33 @@ dict set regsC100 ROM_REMAP_EN 0x1 #// INTC block // #//////////////////////////////////////////////////////////// -dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18] +dict set regsC100 INTC_ARM1_CONTROL_REG [expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}] #//////////////////////////////////////////////////////////// #// TIMER block // #//////////////////////////////////////////////////////////// -dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00] -dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04] -dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08] -dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C] +dict set regsC100 TIMER0_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}] +dict set regsC100 TIMER0_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}] +dict set regsC100 TIMER1_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}] +dict set regsC100 TIMER1_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}] -dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18] -dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10] -dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14] -dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C] +dict set regsC100 TIMER2_CNTR_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}] +dict set regsC100 TIMER2_LBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}] +dict set regsC100 TIMER2_HBOUND_REG [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}] +dict set regsC100 TIMER2_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}] -dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20] -dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24] -dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28] -dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C] +dict set regsC100 TIMER3_LOBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}] +dict set regsC100 TIMER3_HIBND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}] +dict set regsC100 TIMER3_CTRL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}] +dict set regsC100 TIMER3_CURR_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}] -dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40] -dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50] -dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0] -dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4] -dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8] +dict set regsC100 TIMER_MASK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}] +dict set regsC100 TIMER_STATUS [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_ACK [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}] +dict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}] +dict set regsC100 TIMER_WDT_CONTROL [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}] +dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}] @@ -149,40 +149,40 @@ dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEAD #// EBUS block #//////////////////////////////////////////////////////////// -dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00] -dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04] -dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08] -dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C] -dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10] -dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14] -dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18] -dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C] -dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20] -dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24] -dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28] -dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C] -dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30] -dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34] -dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38] -dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C] -dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40] -dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44] -dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48] -dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C] -dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50] -dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54] -dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58] -dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C] -dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60] -dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64] -dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68] -dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C] - -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100] -dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104] -dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108] -dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C] +dict set regsC100 EX_SWRST_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}] +dict set regsC100 EX_CSEN_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}] +dict set regsC100 EX_CS0_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}] +dict set regsC100 EX_CS1_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}] +dict set regsC100 EX_CS2_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}] +dict set regsC100 EX_CS3_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}] +dict set regsC100 EX_CS4_SEG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}] +dict set regsC100 EX_CS0_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}] +dict set regsC100 EX_CS1_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}] +dict set regsC100 EX_CS2_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}] +dict set regsC100 EX_CS3_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}] +dict set regsC100 EX_CS4_CFG_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}] +dict set regsC100 EX_CS0_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}] +dict set regsC100 EX_CS1_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}] +dict set regsC100 EX_CS2_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}] +dict set regsC100 EX_CS3_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}] +dict set regsC100 EX_CS4_TMG1_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}] +dict set regsC100 EX_CS0_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}] +dict set regsC100 EX_CS1_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}] +dict set regsC100 EX_CS2_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}] +dict set regsC100 EX_CS3_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}] +dict set regsC100 EX_CS4_TMG2_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}] +dict set regsC100 EX_CS0_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}] +dict set regsC100 EX_CS1_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}] +dict set regsC100 EX_CS2_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}] +dict set regsC100 EX_CS3_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}] +dict set regsC100 EX_CS4_TMG3_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}] +dict set regsC100 EX_CLOCK_DIV_REG [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}] + +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_MFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}] +dict set regsC100 EX_CSFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}] +dict set regsC100 EX_WRFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}] +dict set regsC100 EX_RDFSM_REG [expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}] dict set regsC100 EX_CLK_EN 0x00000001 @@ -211,21 +211,21 @@ dict set regsC100 EX_RDY_EDGE 0x00000800 #//////////////////////////////////////////////////////////// # GPIO outputs register -dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00] +dict set regsC100 GPIO_OUTPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}] # GPIO Output Enable register -dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04] -dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08] -dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C] +dict set regsC100 GPIO_OE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}] +dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}] +dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}] # GPIO input register -dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10] -dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14] -dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18] -dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C] -dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30] -dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40] -dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38] -dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44] -dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50] +dict set regsC100 GPIO_INPUT_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}] +dict set regsC100 APB_ACCESS_WS_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}] +dict set regsC100 MUX_CONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}] +dict set regsC100 SYSCONF_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}] +dict set regsC100 GPIO_ARM_ID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}] +dict set regsC100 GPIO_BOOTSTRAP_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}] +dict set regsC100 GPIO_LOCK_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}] +dict set regsC100 GPIO_IOCTRL_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}] +dict set regsC100 GPIO_DEVID_REG [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}] dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001 dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002 @@ -258,31 +258,31 @@ dict set regsC100 GPIO_BOTH_EDGES 3 #// UART #//////////////////////////////////////////////////////////// -dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00] -dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04] -dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08] -dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C] -dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10] -dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14] -dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18] -dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C] - -dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00] -dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04] -dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08] -dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C] -dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10] -dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14] -dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18] -dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C] +dict set regsC100 UART0_RBR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_THR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_DLL [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}] +dict set regsC100 UART0_IER [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_DLH [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}] +dict set regsC100 UART0_IIR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_FCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}] +dict set regsC100 UART0_LCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}] +dict set regsC100 UART0_MCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}] +dict set regsC100 UART0_LSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}] +dict set regsC100 UART0_MSR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}] +dict set regsC100 UART0_SCR [expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}] + +dict set regsC100 UART1_RBR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_THR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_DLL [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}] +dict set regsC100 UART1_IER [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_DLH [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}] +dict set regsC100 UART1_IIR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_FCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}] +dict set regsC100 UART1_LCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}] +dict set regsC100 UART1_MCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}] +dict set regsC100 UART1_LSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}] +dict set regsC100 UART1_MSR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}] +dict set regsC100 UART1_SCR [expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}] # /* default */ dict set regsC100 LCR_CHAR_LEN_5 0x00 @@ -308,51 +308,51 @@ dict set regsC100 LCR_PSB 0x80 dict set regsC100 LCR_DLAB 0x80 #/* FIFO Error Status */ -dict set regsC100 LSR_FIFOE [expr 1 << 7] +dict set regsC100 LSR_FIFOE [expr {1 << 7}] #/* Transmitter Empty */ -dict set regsC100 LSR_TEMT [expr 1 << 6] +dict set regsC100 LSR_TEMT [expr {1 << 6}] #/* Transmit Data Request */ -dict set regsC100 LSR_TDRQ [expr 1 << 5] +dict set regsC100 LSR_TDRQ [expr {1 << 5}] #/* Break Interrupt */ -dict set regsC100 LSR_BI [expr 1 << 4] +dict set regsC100 LSR_BI [expr {1 << 4}] #/* Framing Error */ -dict set regsC100 LSR_FE [expr 1 << 3] +dict set regsC100 LSR_FE [expr {1 << 3}] #/* Parity Error */ -dict set regsC100 LSR_PE [expr 1 << 2] +dict set regsC100 LSR_PE [expr {1 << 2}] #/* Overrun Error */ -dict set regsC100 LSR_OE [expr 1 << 1] +dict set regsC100 LSR_OE [expr {1 << 1}] #/* Data Ready */ -dict set regsC100 LSR_DR [expr 1 << 0] +dict set regsC100 LSR_DR [expr {1 << 0}] #/* DMA Requests Enable */ -dict set regsC100 IER_DMAE [expr 1 << 7] +dict set regsC100 IER_DMAE [expr {1 << 7}] #/* UART Unit Enable */ -dict set regsC100 IER_UUE [expr 1 << 6] +dict set regsC100 IER_UUE [expr {1 << 6}] #/* NRZ coding Enable */ -dict set regsC100 IER_NRZE [expr 1 << 5] +dict set regsC100 IER_NRZE [expr {1 << 5}] #/* Receiver Time Out Interrupt Enable */ -dict set regsC100 IER_RTIOE [expr 1 << 4] +dict set regsC100 IER_RTIOE [expr {1 << 4}] #/* Modem Interrupt Enable */ -dict set regsC100 IER_MIE [expr 1 << 3] +dict set regsC100 IER_MIE [expr {1 << 3}] #/* Receiver Line Status Interrupt Enable */ -dict set regsC100 IER_RLSE [expr 1 << 2] +dict set regsC100 IER_RLSE [expr {1 << 2}] #/* Transmit Data request Interrupt Enable */ -dict set regsC100 IER_TIE [expr 1 << 1] +dict set regsC100 IER_TIE [expr {1 << 1}] #/* Receiver Data Available Interrupt Enable */ -dict set regsC100 IER_RAVIE [expr 1 << 0] +dict set regsC100 IER_RAVIE [expr {1 << 0}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES1 [expr 1 << 7] +dict set regsC100 IIR_FIFOES1 [expr {1 << 7}] #/* FIFO Mode Enable Status */ -dict set regsC100 IIR_FIFOES0 [expr 1 << 6] +dict set regsC100 IIR_FIFOES0 [expr {1 << 6}] #/* Time Out Detected */ -dict set regsC100 IIR_TOD [expr 1 << 3] +dict set regsC100 IIR_TOD [expr {1 << 3}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID2 [expr 1 << 2] +dict set regsC100 IIR_IID2 [expr {1 << 2}] #/* Interrupt Source Encoded */ -dict set regsC100 IIR_IID1 [expr 1 << 1] +dict set regsC100 IIR_IID1 [expr {1 << 1}] #/* Interrupt Pending (active low) */ -dict set regsC100 IIR_IP [expr 1 << 0] +dict set regsC100 IIR_IP [expr {1 << 0}] #/* UART 16550 FIFO Control Register */ dict set regsC100 FCR_FIFOEN 0x01 @@ -372,17 +372,17 @@ dict set regsC100 IER_TXTH 0x02 #// CLK + RESET block #//////////////////////////////////////////////////////////// -dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00] -dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04] -dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08] -dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C] -dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10] -dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14] -dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18] -dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C] -dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20] -dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24] -dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}] +dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}] +dict set regsC100 CLKCORE_PLL_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}] +dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}] +dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}] +dict set regsC100 CLKCORE_FSYNC_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}] +dict set regsC100 CLKCORE_CLK_PWR_DWN [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}] +dict set regsC100 CLKCORE_RNG_CNTRL [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}] +dict set regsC100 CLKCORE_RNG_STATUS [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}] +dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}] +dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}] dict set regsC100 ARM_PLL_BY_CTRL 0x80000000 dict set regsC100 ARM_AHB_BYP 0x04000000 @@ -429,8 +429,8 @@ dict set regsC100 FCLK_PLL_LOCK 0x00000001 #// reset block -dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100] -dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104] +dict set regsC100 BLOCK_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}] +dict set regsC100 CSP_RESET_REG [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}] dict set regsC100 RNG_RST 0x1000 dict set regsC100 IPSEC_RST 0x0800 @@ -451,42 +451,42 @@ dict set regsC100 PCI_RST 0x0001 #//////////////////////////////////////////////////////////////// dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000 -dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00] -dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08] -dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10] -dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18] -dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20] -dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28] -dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30] -dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38] -dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40] -dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48] -dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50] -dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58] -dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60] -dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68] -dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70] -dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78] -dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80] -dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88] -dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90] -dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98] -dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0] +dict set regsC100 DENALI_CTL_00_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}] +dict set regsC100 DENALI_CTL_01_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}] +dict set regsC100 DENALI_CTL_02_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}] +dict set regsC100 DENALI_CTL_03_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}] +dict set regsC100 DENALI_CTL_04_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}] +dict set regsC100 DENALI_CTL_05_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}] +dict set regsC100 DENALI_CTL_06_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}] +dict set regsC100 DENALI_CTL_07_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}] +dict set regsC100 DENALI_CTL_08_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}] +dict set regsC100 DENALI_CTL_09_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}] +dict set regsC100 DENALI_CTL_10_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}] +dict set regsC100 DENALI_CTL_11_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}] +dict set regsC100 DENALI_CTL_12_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}] +dict set regsC100 DENALI_CTL_13_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}] +dict set regsC100 DENALI_CTL_14_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}] +dict set regsC100 DENALI_CTL_15_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}] +dict set regsC100 DENALI_CTL_16_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}] +dict set regsC100 DENALI_CTL_17_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}] +dict set regsC100 DENALI_CTL_18_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}] +dict set regsC100 DENALI_CTL_19_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}] +dict set regsC100 DENALI_CTL_20_DATA [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}] # 32-bit value -dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44] +dict set regsC100 DENALI_READY_CHECK [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}] # 8-bit -dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D] +dict set regsC100 DENALI_WR_DQS [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}] # 8-bit -dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A] +dict set regsC100 DENALI_DQS_OUT [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F] +dict set regsC100 DENALI_DQS_DELAY0 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50] +dict set regsC100 DENALI_DQS_DELAY1 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51] +dict set regsC100 DENALI_DQS_DELAY2 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}] # 8-bit -dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52] +dict set regsC100 DENALI_DQS_DELAY3 [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}] # end of proc regsC100 diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 859a925..ef07856 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -22,53 +22,53 @@ source [find mem_helper.tcl] # PLL version 0x02: tested on dm355 # REVISIT: On dm6446/dm357 the PLLRST polarity is different. proc pll_v02_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator # NOTE: this assumes we should clear that bit - set pll_ctrl [expr $pll_ctrl & ~0x0100] + set pll_ctrl [expr {$pll_ctrl & ~0x0100}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 3 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 4 - wait at least 4 refclk cycles sleep 1 # 5 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 6 - set PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl | 0x0010] + set pll_ctrl [expr {$pll_ctrl | 0x0010}] mww $pll_ctrl_addr $pll_ctrl # 7 - clear PLLPWRDN (bit 1) - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 8 - clear PLLDIS (bit 4) - set pll_ctrl [expr $pll_ctrl & ~0x0010] + set pll_ctrl [expr {$pll_ctrl & ~0x0010}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm # NOTE: for dm355 PLL1, postdiv is controlled via MISC register - mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - optional: set plldiv1, plldiv2, ... @@ -78,47 +78,47 @@ proc pll_v02_setup {pll_addr mult config} { set go 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div set go 1 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div set go 1 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div set go 1 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div set go 1 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div set go 1 } if {$go != 0} { # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 # 11 - wait at least 5 usec for reset to finish # (assume covered by overheads including JTAG messaging) # 12 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 13 - wait at least 8000 refclk cycles for PLL to lock @@ -126,53 +126,53 @@ proc pll_v02_setup {pll_addr mult config} { sleep 3 # 14 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } # PLL version 0x03: tested on dm365 proc pll_v03_setup {pll_addr mult config} { - set pll_ctrl_addr [expr $pll_addr + 0x100] - set pll_secctrl_addr [expr $pll_addr + 0x108] + set pll_ctrl_addr [expr {$pll_addr + 0x100}] + set pll_secctrl_addr [expr {$pll_addr + 0x108}] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - power up the PLL - set pll_ctrl [expr $pll_ctrl & ~0x0002] + set pll_ctrl [expr {$pll_ctrl & ~0x0002}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLENSRC (bit 5) - set pll_ctrl [expr $pll_ctrl & ~0x0020] + set pll_ctrl [expr {$pll_ctrl & ~0x0020}] mww $pll_ctrl_addr $pll_ctrl # 2 - clear PLLEN (bit 0) ... enter bypass mode - set pll_ctrl [expr $pll_ctrl & ~0x0001] + set pll_ctrl [expr {$pll_ctrl & ~0x0001}] mww $pll_ctrl_addr $pll_ctrl # 3 - wait at least 4 refclk cycles sleep 1 # 4 - set PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl | 0x0008] + set pll_ctrl [expr {$pll_ctrl | 0x0008}] mww $pll_ctrl_addr $pll_ctrl # 5 - wait at least 5 usec sleep 1 # 6 - clear PLLRST (bit 3) - set pll_ctrl [expr $pll_ctrl & ~0x0008] + set pll_ctrl [expr {$pll_ctrl & ~0x0008}] mww $pll_ctrl_addr $pll_ctrl # 9 - optional: write prediv, postdiv, and pllm - mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] + mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}] if { [dict exists $config prediv] } { set div [dict get $config prediv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0114] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0114}] $div } if { [dict exists $config postdiv] } { set div [dict get $config postdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0128] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0128}] $div } # 10 - write start sequence to PLLSECCTL @@ -187,99 +187,99 @@ proc pll_v03_setup {pll_addr mult config} { set aln 0 if { [dict exists $config div1] } { set div [dict get $config div1] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0118] $div - set aln [expr $aln | 0x1] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0118}] $div + set aln [expr {$aln | 0x1}] } else { - mww [expr $pll_addr + 0x0118] 0 + mww [expr {$pll_addr + 0x0118}] 0 } if { [dict exists $config div2] } { set div [dict get $config div2] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x011c] $div - set aln [expr $aln | 0x2] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x011c}] $div + set aln [expr {$aln | 0x2}] } else { - mww [expr $pll_addr + 0x011c] 0 + mww [expr {$pll_addr + 0x011c}] 0 } if { [dict exists $config div3] } { set div [dict get $config div3] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0120] $div - set aln [expr $aln | 0x4] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0120}] $div + set aln [expr {$aln | 0x4}] } else { - mww [expr $pll_addr + 0x0120] 0 + mww [expr {$pll_addr + 0x0120}] 0 } if { [dict exists $config oscdiv] } { set div [dict get $config oscdiv] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0124] $div + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0124}] $div } else { - mww [expr $pll_addr + 0x0124] 0 + mww [expr {$pll_addr + 0x0124}] 0 } if { [dict exists $config div4] } { set div [dict get $config div4] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0160] $div - set aln [expr $aln | 0x8] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0160}] $div + set aln [expr {$aln | 0x8}] } else { - mww [expr $pll_addr + 0x0160] 0 + mww [expr {$pll_addr + 0x0160}] 0 } if { [dict exists $config div5] } { set div [dict get $config div5] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0164] $div - set aln [expr $aln | 0x10] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0164}] $div + set aln [expr {$aln | 0x10}] } else { - mww [expr $pll_addr + 0x0164] 0 + mww [expr {$pll_addr + 0x0164}] 0 } if { [dict exists $config div6] } { set div [dict get $config div6] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0168] $div - set aln [expr $aln | 0x20] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0168}] $div + set aln [expr {$aln | 0x20}] } else { - mww [expr $pll_addr + 0x0168] 0 + mww [expr {$pll_addr + 0x0168}] 0 } if { [dict exists $config div7] } { set div [dict get $config div7] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x016c] $div - set aln [expr $aln | 0x40] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x016c}] $div + set aln [expr {$aln | 0x40}] } else { - mww [expr $pll_addr + 0x016c] 0 + mww [expr {$pll_addr + 0x016c}] 0 } if { [dict exists $config div8] } { set div [dict get $config div8] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0170] $div - set aln [expr $aln | 0x80] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0170}] $div + set aln [expr {$aln | 0x80}] } else { - mww [expr $pll_addr + 0x0170] 0 + mww [expr {$pll_addr + 0x0170}] 0 } if { [dict exists $config div9] } { set div [dict get $config div9] - set div [expr 0x8000 | ($div - 1)] - mww [expr $pll_addr + 0x0174] $div - set aln [expr $aln | 0x100] + set div [expr {0x8000 | ($div - 1)}] + mww [expr {$pll_addr + 0x0174}] $div + set aln [expr {$aln | 0x100}] } else { - mww [expr $pll_addr + 0x0174] 0 + mww [expr {$pll_addr + 0x0174}] 0 } if {$aln != 0} { # clear pllcmd.GO - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 # write alingment flags - mww [expr $pll_addr + 0x0140] $aln + mww [expr {$pll_addr + 0x0140}] $aln # write pllcmd.GO; poll pllstat.GO - mww [expr $pll_addr + 0x0138] 0x01 - set pllstat [expr $pll_addr + 0x013c] + mww [expr {$pll_addr + 0x0138}] 0x01 + set pllstat [expr {$pll_addr + 0x013c}] while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } } - mww [expr $pll_addr + 0x0138] 0x00 + mww [expr {$pll_addr + 0x0138}] 0x00 set addr [dict get $config ctladdr] while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } # 12 - set PLLEN (bit 0) ... leave bypass mode - set pll_ctrl [expr $pll_ctrl | 0x0001] + set pll_ctrl [expr {$pll_ctrl | 0x0001}] mww $pll_ctrl_addr $pll_ctrl } @@ -290,26 +290,26 @@ proc pll_v03_setup {pll_addr mult config} { proc psc_enable {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f } # prepare a non-DSP module to be reset; finish with psc_go proc psc_reset {module} { set psc_addr 0x01c41000 # write MDCTL - mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f + mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f } # execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc proc psc_go {} { set psc_addr 0x01c41000 - set ptstat_addr [expr $psc_addr + 0x0128] + set ptstat_addr [expr {$psc_addr + 0x0128}] # just in case PTSTAT.go isn't clear while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } # write PTCMD.go ... ignoring any DSP power domain - mww [expr $psc_addr + 0x0120] 1 + mww [expr {$psc_addr + 0x0120}] 1 # wait for PTSTAT.go to clear (again ignoring DSP power domain) while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } @@ -344,34 +344,34 @@ proc davinci_wdog_reset {} { # # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 # # Part II -- in case watchdog hasn't been set up # # TCR: disable, force internal clock source - mww phys [expr $timer2_phys + 0x20] 0 + mww phys [expr {$timer2_phys + 0x20}] 0 # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state) - mww phys [expr $timer2_phys + 0x24] 0 - mww phys [expr $timer2_phys + 0x24] 0x110b + mww phys [expr {$timer2_phys + 0x24}] 0 + mww phys [expr {$timer2_phys + 0x24}] 0x110b # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers # so watchdog triggers ASAP - mww phys [expr $timer2_phys + 0x10] 0 - mww phys [expr $timer2_phys + 0x14] 0 - mww phys [expr $timer2_phys + 0x18] 0 - mww phys [expr $timer2_phys + 0x1c] 0 + mww phys [expr {$timer2_phys + 0x10}] 0 + mww phys [expr {$timer2_phys + 0x14}] 0 + mww phys [expr {$timer2_phys + 0x18}] 0 + mww phys [expr {$timer2_phys + 0x1c}] 0 # WDTCR: put into pre-active state, then active - mww phys [expr $timer2_phys + 0x28] 0xa5c64000 - mww phys [expr $timer2_phys + 0x28] 0xda7e4000 + mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000 + mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000 # # Part III -- it's ready to rumble # # WDTCR: write invalid WDKEY to trigger reset - mww phys [expr $timer2_phys + 0x28] 0x00004000 + mww phys [expr {$timer2_phys + 0x28}] 0x00004000 } diff --git a/tcl/target/fm4_mb9bf.cfg b/tcl/target/fm4_mb9bf.cfg index e53fdc8..ca4e5f9 100644 --- a/tcl/target/fm4_mb9bf.cfg +++ b/tcl/target/fm4_mb9bf.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x8000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/fm4_s6e2cc.cfg b/tcl/target/fm4_s6e2cc.cfg index 60b73b9..c6f835d 100644 --- a/tcl/target/fm4_s6e2cc.cfg +++ b/tcl/target/fm4_s6e2cc.cfg @@ -11,7 +11,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x18000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index d125071..cdf4f24 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -84,7 +84,7 @@ proc icepick_c_tapenable {jrc port} { set block 0x2 } elseif { $port < 32 } { # Test tap - set tap [expr ($port - 16)] + set tap [expr {$port - 16}] set block 0x1 } else { echo "ERROR: Invalid ICEPick C port number: $port" diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg index ccfddb6..e2bee7a 100644 --- a/tcl/target/imx.cfg +++ b/tcl/target/imx.cfg @@ -10,7 +10,7 @@ proc setc15 {regs value} { echo [format "set p15 0x%04x, 0x%08x" $regs $value] - arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value + arm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value } diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index 624fe29..ee10b21 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -72,11 +72,11 @@ proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } { switch $CASLAT { 2 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD } 3 { - set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ] + set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ] set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD } default { error [format "unsupported cas latency \"%s\" " $CASLAT] } diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index 6e3e78d..5b9e23c 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index 218eb64..fb76e13 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -91,7 +91,7 @@ set _TARGETNAME $_CHIPNAME.cpu # 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT) set _coreid 0 -set _dbgbase [expr 0x80000000 | ($_coreid << 13)] +set _dbgbase [expr {0x80000000 | ($_coreid << 13)}] echo "Using dbgbase = [format 0x%x $_dbgbase]" dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index 360a0dd..f85c2ee 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -69,4 +69,4 @@ set ENABLE_JSP_MULTI 4 # on burst reads and writes to improve download speeds. # This option must match the RTL configured option. -du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI] +du_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}] diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index 51a6bbd..f15924f 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -42,7 +42,7 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM global _PIC32MX_DATASIZE global _WORKAREASIZE set _PIC32MX_DATASIZE 0x800 -set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)] +set _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}] $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0 $_TARGETNAME configure -event reset-init { diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg index b4e8d05..c90fd42 100644 --- a/tcl/target/psoc5lp.cfg +++ b/tcl/target/psoc5lp.cfg @@ -34,7 +34,7 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x2000 } -$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE / 2] \ +$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \ -work-area-size $_WORKAREASIZE -work-area-backup 0 source [find mem_helper.tcl] @@ -43,15 +43,15 @@ $_TARGETNAME configure -event reset-init { # Configure Target Device (PSoC 5LP Device Programming Specification 5.2) set PANTHER_DBG_CFG 0x4008000C - set PANTHER_DBG_CFG_BYPASS [expr 1 << 1] + set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}] mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0 set PM_ACT_CFG0 0x400043A0 mww $PM_ACT_CFG0 0xBF set FASTCLK_IMO_CR 0x40004200 - set FASTCLK_IMO_CR_F_RANGE_2 [expr 2 << 0] - set FASTCLK_IMO_CR_F_RANGE_MASK [expr 7 << 0] + set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}] + set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}] mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK } diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg index 2f7fecb..d09561f 100644 --- a/tcl/target/snps_em_sk_fpga.cfg +++ b/tcl/target/snps_em_sk_fpga.cfg @@ -20,7 +20,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \ -expected-id 0x200044b1 set _coreid 0 -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \ -coreid 0 -dbgbase $_dbgbase -endian little diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg index 634e07a..372b406 100644 --- a/tcl/target/snps_hsdk.cfg +++ b/tcl/target/snps_hsdk.cfg @@ -13,7 +13,7 @@ source [find cpu/arc/hs.tcl] set _coreid 0 -set _dbgbase [expr ($_coreid << 13)] +set _dbgbase [expr {$_coreid << 13}] # CHIPNAME will be used to choose core family (600, 700 or EM). As far as # OpenOCD is concerned EM and HS are identical. @@ -30,8 +30,8 @@ $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase # Flush L2$. $_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -46,8 +46,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -62,8 +62,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {$_coreid << 13}] arc_hs_init_regs @@ -78,8 +78,8 @@ target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME $_TARGETNAME configure -coreid $_coreid $_TARGETNAME configure -dbgbase $_dbgbase $_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME" -set _coreid [expr $_coreid + 1] -set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +set _coreid [expr {$_coreid + 1}] +set _dbgbase [expr {0x00000000 | ($_coreid << 13)}] arc_hs_init_regs # Enable L2 cache support for core 1. diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 26d0d93..877976c 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -208,7 +208,7 @@ proc stm32h7x_get_chipname {} { if {$sep == -1} { return $t } - return [string range $t 0 [expr $sep - 1]] + return [string range $t 0 [expr {$sep - 1}]] } if {[set $_CHIPNAME.DUAL_CORE]} { @@ -240,7 +240,7 @@ proc stm32h7x_mrw {used_target reg} { # like mmw, but with target selection proc stm32h7x_mmw {used_target reg setbits clearbits} { set old [stm32h7x_mrw $used_target $reg] - set new [expr ($old & ~$clearbits) | $setbits] + set new [expr {($old & ~$clearbits) | $setbits}] $used_target mww $reg $new } @@ -251,10 +251,10 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { if {![using_hla]} { set _CHIPNAME [stm32h7x_get_chipname] set used_target $_CHIPNAME.ap2 - set reg_addr [expr 0xE00E1000 + $reg_offset] + set reg_addr [expr {0xE00E1000 + $reg_offset}] } { set used_target [target current] - set reg_addr [expr 0x5C001000 + $reg_offset] + set reg_addr [expr {0x5C001000 + $reg_offset}] } stm32h7x_mmw $used_target $reg_addr $setbits $clearbits diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index 91c0087..19fb0b6 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -90,7 +90,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm355 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index 8b52746..f71a77a 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -82,7 +82,7 @@ target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel, # and that the work area is used only with a kernel mmu context ... $_TARGETNAME configure \ - -work-area-virt [expr 0xfffe0000 + 0x4000] \ + -work-area-virt [expr {0xfffe0000 + 0x4000}] \ -work-area-phys [dict get $dm365 sram1] \ -work-area-size 0x4000 \ -work-area-backup 0 diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 36e0db7..5ef98e9 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -4,13 +4,13 @@ proc mmu_off {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp & ~1)] + set cp [expr {$cp & ~1}] arm mcr 15 0 1 0 0 $cp } proc mmu_on {} { set cp [arm mrc 15 0 1 0 0] - set cp [expr ($cp | 1)] + set cp [expr {$cp | 1}] arm mcr 15 0 1 0 0 $cp } diff --git a/tcl/test/selftest.cfg b/tcl/test/selftest.cfg index be420ca..0331b48 100644 --- a/tcl/test/selftest.cfg +++ b/tcl/test/selftest.cfg @@ -3,11 +3,11 @@ add_help_text selftest "run selftest using working ram
Date: Sat, 10 Apr 2021 17:37:04 +0200 Subject: tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Enclose within double quote the argument of 'expr' when there is the need to concatenate strings. Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6160 Tested-by: jenkins --- tcl/chip/atmel/at91/rtt.tcl | 2 +- tcl/chip/atmel/at91/usarts.tcl | 2 +- tcl/fpga/xilinx-xadc.cfg | 2 +- tcl/target/u8500.cfg | 18 +++++++++--------- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl index 3e3d414..d49ce71 100644 --- a/tcl/chip/atmel/at91/rtt.tcl +++ b/tcl/chip/atmel/at91/rtt.tcl @@ -17,7 +17,7 @@ proc show_RTTC_RTMR_helper { NAME ADDR VAL } { global AT91C_SLOWOSC_FREQ # Nasty hack, make this a float by tacking a .0 on the end # otherwise, jim makes the value an integer - set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0] + set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"] echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f] if { $VAL & $BIT16 } { echo "\tBit16 -> Alarm IRQ Enabled" diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl index 95aced8..f840b78 100644 --- a/tcl/chip/atmel/at91/usarts.tcl +++ b/tcl/chip/atmel/at91/usarts.tcl @@ -89,7 +89,7 @@ foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } { set vn [set WHO]_[set REG] # vn = USx_IER # vv = variable value - set vv [expr $$n + [set USx_[set REG]]] + set vv [expr "$$n + [set USx_[set REG]]"] # And VV is the address in memory of that register diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg index 043e553..c451ca2 100644 --- a/tcl/fpga/xilinx-xadc.cfg +++ b/tcl/fpga/xilinx-xadc.cfg @@ -101,7 +101,7 @@ proc xadc_select {tap} { proc xadc_xfer {tap cmd addr data} { set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]] runtest 10 - return [expr 0x$ret] + return [expr "0x$ret"] } # XADC register write diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 5ef98e9..15bacf3 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -52,9 +52,9 @@ proc pwrsts { } { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0 set pwrsts [drscan $_CHIPNAME.jrc 16 0] - echo "pwrsts ="$pwrsts - set a9 [expr (0x$pwrsts & 0xc)] - set ape [expr (0x$pwrsts & 0x3)] + echo "pwrsts ="$pwrsts + set a9 [expr "0x$pwrsts & 0xc"] + set ape [expr "0x$pwrsts & 0x3"] if {[string equal "0" $ape]} { echo "ape off" } else { @@ -81,12 +81,12 @@ proc poll_pwrsts { } { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0 set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] + set pwrsts [expr "0x$pwrsts & 0xc"] while {[string equal "4" $pwrsts] && $i<20} { irscan $_CHIPNAME.jrc 0x3a drscan $_CHIPNAME.jrc 4 0; set pwrsts [drscan $_CHIPNAME.jrc 16 0] - set pwrsts [expr (0x$pwrsts & 0xc)] + set pwrsts [expr "0x$pwrsts & 0xc"] if {![string equal "4" $pwrsts]} { set result 1 } else { @@ -239,7 +239,7 @@ proc secsts1 { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] if {![string equal "4" $secsts1]} { echo "APE target secured" } else { @@ -254,7 +254,7 @@ proc att { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] if {[string equal "4" $secsts1]} { if {[poll_pwrsts]==1} { enable_apetap @@ -291,13 +291,13 @@ proc rst_run { } { drscan $_CHIPNAME.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] while {![string equal "4" $secsts1]} { irscan u8500.jrc 0x3a drscan u8500.jrc 4 4 set secsts1 [drscan $_CHIPNAME.jrc 16 0] echo "secsts1 ="$secsts1 - set secsts1 [expr (0x$secsts1 & 0x4)] + set secsts1 [expr "0x$secsts1 & 0x4"] } echo "ape debugable" enable_apetap -- cgit v1.1 From 64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 10 Apr 2021 18:28:52 +0200 Subject: tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single arg") drops the support for multi-argument syntax for the TCL command 'expr'. Fix manually the remaining lines that don't match simple patterns and would require dedicated boring scripting. Remove the 'expr' command where appropriate. Change-Id: Ia75210c8447f88d38515addab4a836af9103096d Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6161 Tested-by: jenkins Reviewed-by: Tomas Vanek --- tcl/bitsbytes.tcl | 4 ++-- tcl/board/at91sam9261-ek.cfg | 8 ++++---- tcl/board/at91sam9263-ek.cfg | 10 +++++----- tcl/board/at91sam9g20-ek.cfg | 8 ++++---- tcl/board/dm355evm.cfg | 2 +- tcl/board/embedded-artists_lpc2478-32.cfg | 2 +- tcl/board/hilscher_nxhx10.cfg | 4 ++-- tcl/board/icnova_imx53_sodimm.cfg | 8 ++++---- tcl/board/icnova_sam9g45_sodimm.cfg | 16 ++++++++-------- tcl/board/imx53-m53evk.cfg | 8 ++++---- tcl/board/imx53loco.cfg | 8 ++++---- tcl/board/nxp_imx7sabre.cfg | 2 +- tcl/chip/atmel/at91/at91_pmc.cfg | 2 +- tcl/chip/atmel/at91/at91sam9_init.cfg | 18 +++++++++--------- tcl/chip/atmel/at91/usarts.tcl | 2 +- tcl/chip/st/spear/quirk_no_srst.tcl | 2 +- tcl/chip/st/spear/spear3xx.tcl | 8 ++++---- tcl/fpga/xilinx-xadc.cfg | 2 +- tcl/memory.tcl | 2 +- tcl/mmr_helpers.tcl | 4 ++-- tcl/target/am335x.cfg | 4 ++-- tcl/target/am437x.cfg | 14 +++++++------- tcl/target/bluenrg-x.cfg | 2 +- tcl/target/c100config.tcl | 6 +++--- tcl/target/c100helper.tcl | 22 +++++++++++----------- tcl/target/davinci.cfg | 12 ++++++------ tcl/target/hilscher_netx500.cfg | 4 ++-- tcl/target/icepick.cfg | 4 ++-- tcl/target/psoc4.cfg | 12 ++++++------ tcl/target/stellaris.cfg | 8 ++++---- tcl/target/stm32mp15x.cfg | 2 +- tcl/target/u8500.cfg | 4 ++-- tcl/tools/memtest.tcl | 4 ++-- 33 files changed, 109 insertions(+), 109 deletions(-) diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl index 5f9cae1..01cc509 100644 --- a/tcl/bitsbytes.tcl +++ b/tcl/bitsbytes.tcl @@ -36,7 +36,7 @@ proc create_mask { MSB LSB } { # Result: 0x02340000 proc extract_bitfield { VALUE MSB LSB } { - return [expr [create_mask $MSB $LSB] & $VALUE] + return [expr {[create_mask $MSB $LSB] & $VALUE}] } @@ -47,7 +47,7 @@ proc extract_bitfield { VALUE MSB LSB } { # Result: 0x00000234 # proc normalize_bitfield { VALUE MSB LSB } { - return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB] + return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}] } proc show_normalize_bitfield { VALUE MSB LSB } { diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg index d6e8c2d..1f3de48 100644 --- a/tcl/board/at91sam9261-ek.cfg +++ b/tcl/board/at91sam9261-ek.cfg @@ -29,9 +29,9 @@ proc at91sam9261ek_reset_init { } { ;# set master_pll_div 1 ;# set master_pll_mul 13 - set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable - set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt @@ -42,7 +42,7 @@ proc at91sam9261ek_reset_init { } { set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] ;# SDRAMC_CR - Configuration register - set val [expr $::AT91_SDRAMC_NC_9] + set val $::AT91_SDRAMC_NC_9 set val [expr {$val | $::AT91_SDRAMC_NR_13}] set val [expr {$val | $::AT91_SDRAMC_NB_4}] set val [expr {$val | $::AT91_SDRAMC_CAS_3}] diff --git a/tcl/board/at91sam9263-ek.cfg b/tcl/board/at91sam9263-ek.cfg index b88efa9..ab04228 100644 --- a/tcl/board/at91sam9263-ek.cfg +++ b/tcl/board/at91sam9263-ek.cfg @@ -24,9 +24,9 @@ proc at91sam9263ek_reset_init { } { set config(master_pll_div) 14 set config(master_pll_mul) 171 - set val [expr $::AT91_WDT_WDV] ;# Counter Value - set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable - set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value + set val $::AT91_WDT_WDV ;# Counter Value + set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable + set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt @@ -36,13 +36,13 @@ proc at91sam9263ek_reset_init { } { ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA - set val [expr $::AT91_MATRIX_EBI0_DBPUC] + set val $::AT91_MATRIX_EBI0_DBPUC set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] set config(matrix_ebicsa_val) $val ;# SDRAMC_CR - Configuration register - set val [expr $::AT91_SDRAMC_NC_9] + set val $::AT91_SDRAMC_NC_9 set val [expr {$val | $::AT91_SDRAMC_NR_13}] set val [expr {$val | $::AT91_SDRAMC_NB_4}] set val [expr {$val | $::AT91_SDRAMC_CAS_3}] diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 03296c5..59ee4d2 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. mww 0xfffffc28 0x202a3f01 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00000101 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg index 1e35b68..bf5659c 100644 --- a/tcl/board/dm355evm.cfg +++ b/tcl/board/dm355evm.cfg @@ -87,7 +87,7 @@ proc dm355evm_init {} { mmw $addr 0x2000 0 # wait for READY - while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 } + while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 } # set IO_READY; then LOCK and PWRSAVE; then PWRDN mmw $addr 0x4000 0 diff --git a/tcl/board/embedded-artists_lpc2478-32.cfg b/tcl/board/embedded-artists_lpc2478-32.cfg index abf0a5f..38f5e1b 100644 --- a/tcl/board/embedded-artists_lpc2478-32.cfg +++ b/tcl/board/embedded-artists_lpc2478-32.cfg @@ -125,7 +125,7 @@ proc init_board {} { # proc enable_pll {} { # Disconnect PLL in case it is already connected - if {[expr [read_register 0xE01FC080] & 0x03] == 3} { + if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} { # Disconnect it, but leave it enabled # (This MUST be done in two steps) mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg index add424d..1875dac 100644 --- a/tcl/board/hilscher_nxhx10.cfg +++ b/tcl/board/hilscher_nxhx10.cfg @@ -34,7 +34,7 @@ proc mread32 {addr} { proc init_clocks { } { puts "Enabling all clocks " set accesskey [mread32 0x101c0070] - mww 0x101c0070 [expr $accesskey] + mww 0x101c0070 $accesskey mww 0x101c0028 0x00007511 } @@ -42,7 +42,7 @@ proc init_clocks { } { proc init_sdrambus { } { puts "Initializing external SDRAM Bus 16 Bit " set accesskey [mread32 0x101c0070] - mww 0x101c0070 [expr $accesskey] + mww 0x101c0070 $accesskey mww 0x101c0C40 0x00000050 puts "Configuring SDRAM controller for K4S561632E (32MB) " diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg index 0a161f6..363d7b4 100644 --- a/tcl/board/icnova_imx53_sodimm.cfg +++ b/tcl/board/icnova_imx53_sodimm.cfg @@ -69,7 +69,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -139,7 +139,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } @@ -157,7 +157,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF @@ -243,7 +243,7 @@ proc setup_pll { PLL_ADDR CLK } { mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 - while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg index 30dc347..8a0736b 100644 --- a/tcl/board/icnova_sam9g45_sodimm.cfg +++ b/tcl/board/icnova_sam9g45_sodimm.cfg @@ -89,27 +89,27 @@ proc at91sam9g45_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. #mww 0xfffffc28 0x202a3f01 mww 0xfffffc28 0x20c73f03 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. #mww 0xfffffc30 0x00000101 mww 0xfffffc30 0x00001301 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz @@ -214,7 +214,7 @@ proc at91sam9g45_init { } { sleep 1 # 9. Enable DLL Reset (set DLL bit) - set CR [expr [read_register 0xffffe608] | 0x80] + set CR [expr {[read_register 0xffffe608] | 0x80}] mww 0xffffe608 $CR # 10. mode register cycle to reset the DLL @@ -236,7 +236,7 @@ proc at91sam9g45_init { } { # 12.3 delay 10 cycles # 13. disable DLL reset (clear DLL bit) - set CR [expr [read_register 0xffffe608] & 0xffffff7f] + set CR [expr {[read_register 0xffffe608] & 0xffffff7f}] mww 0xffffe608 $CR # 14. mode register set cycle @@ -244,7 +244,7 @@ proc at91sam9g45_init { } { mww 0x70000000 0x1 # 15. program OCD field (set OCD bits) - set CR [expr [read_register 0xffffe608] | 0x7000] + set CR [expr {[read_register 0xffffe608] | 0x7000}] mww 0xffffe608 $CR # 16. (EMRS1) @@ -253,7 +253,7 @@ proc at91sam9g45_init { } { # 16.1 delay 2 cycles # 17. disable OCD field (clear OCD bits) - set CR [expr [read_register 0xffffe608] & 0xffff8fff] + set CR [expr {[read_register 0xffffe608] & 0xffff8fff}] mww 0xffffe608 $CR # 18. (EMRS1) diff --git a/tcl/board/imx53-m53evk.cfg b/tcl/board/imx53-m53evk.cfg index 6f4964e..04f0f9f 100644 --- a/tcl/board/imx53-m53evk.cfg +++ b/tcl/board/imx53-m53evk.cfg @@ -65,7 +65,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -135,7 +135,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } @@ -153,7 +153,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF @@ -239,7 +239,7 @@ proc setup_pll { PLL_ADDR CLK } { mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 - while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg index e1bc44d..d4ec060 100644 --- a/tcl/board/imx53loco.cfg +++ b/tcl/board/imx53loco.cfg @@ -70,7 +70,7 @@ proc init_l2cc { } { set tR [arm mrc 15 0 1 0 1] ; #bic r0, r0, #0x2 ; #mcr 15, 0, r0, c1, c0, 1 - arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] + arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}] ; #/* reconfigure L2 cache aux control reg */ ; #mov r0, #0xC0 /* tag RAM */ @@ -140,7 +140,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 ; # change uart clk parent to pll2 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}] ; # make sure change is effective while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } @@ -158,7 +158,7 @@ proc init_clock { } { mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 ; # make uart div=6 - mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] + mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}] ; # Restore the default values in the Gate registers mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF @@ -244,7 +244,7 @@ proc setup_pll { PLL_ADDR CLK } { mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 - while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } + while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 } } diff --git a/tcl/board/nxp_imx7sabre.cfg b/tcl/board/nxp_imx7sabre.cfg index c595e3a..789fc5b 100644 --- a/tcl/board/nxp_imx7sabre.cfg +++ b/tcl/board/nxp_imx7sabre.cfg @@ -27,7 +27,7 @@ proc imx7_uart_dbgconf { } { } proc check_bits_set_32 { addr mask } { - while { [expr [mrw $addr] & $mask == 0] } { } + while { [expr {[mrw $addr] & $mask} == 0] } { } } proc apply_dcd { } { diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg index 0233cb4..dd554ce 100644 --- a/tcl/chip/atmel/at91/at91_pmc.cfg +++ b/tcl/chip/atmel/at91/at91_pmc.cfg @@ -87,7 +87,7 @@ set AT91_PMC_USBS_PLLA [expr {0 << 0}] set AT91_PMC_USBS_UPLL [expr {1 << 0}] set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock -;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers +;# set AT91_PMC_PCKR(n) [expr {$AT91_PMC + 0x40 + ((n) * 4)}] ;# Programmable Clock 0-N Registers set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection set AT91_PMC_CSSMCK_CSS [expr {0 << 8}] set AT91_PMC_CSSMCK_MCK [expr {1 << 8}] diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg index 688cb1f..27611eb 100644 --- a/tcl/chip/atmel/at91/at91sam9_init.cfg +++ b/tcl/chip/atmel/at91/at91sam9_init.cfg @@ -11,7 +11,7 @@ proc at91sam9_reset_start { } { jtag_rclk 8 halt wait_halt 10000 - set rstc_mr_val [expr $::AT91_RSTC_KEY] + set rstc_mr_val $::AT91_RSTC_KEY set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}] set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset. @@ -24,25 +24,25 @@ proc at91sam9_reset_init { config } { set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}] mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc. - while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 } + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 } - set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog + set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}] set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}] - set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)] - set pllar_val [expr ($pllar_val | $config(master_pll_div))] + set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}] + set pllar_val [expr {$pllar_val | $config(master_pll_div)}] mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz - while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 } + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 } ;# PCK/2 = MCK Master Clock from PLLA - set mckr_val [expr $::AT91_PMC_CSS_PLLA] + set mckr_val $::AT91_PMC_CSS_PLLA set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}] set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}] set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}] mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) - while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 } + while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 } ## switch JTAG clock to highspeed clock jtag_rclk 0 @@ -50,7 +50,7 @@ proc at91sam9_reset_init { config } { arm7_9 dcc_downloads enable ;# Enable faster DCC downloads arm7_9 fast_memory_access enable - set rstc_mr_val [expr ($::AT91_RSTC_KEY)] + set rstc_mr_val $::AT91_RSTC_KEY set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl index f840b78..253b7fb 100644 --- a/tcl/chip/atmel/at91/usarts.tcl +++ b/tcl/chip/atmel/at91/usarts.tcl @@ -63,7 +63,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } { } echo [format "\tParity: %s " $s] - set x [expr 5 + [show_normalize_bitfield $VAL 7 6]] + set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}] echo [format "\tDatabits: %d" $x] set x [show_normalize_bitfield $VAL 13 12] diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl index 515fb58..551df06 100644 --- a/tcl/chip/st/spear/quirk_no_srst.tcl +++ b/tcl/chip/st/spear/quirk_no_srst.tcl @@ -24,7 +24,7 @@ set sp_reset_mode "" proc sp_is_halted {} { global sp_target_name - return [expr [string compare [$sp_target_name curstate] "halted" ] == 0] + return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}] } # wait for reset button to be pressed, causing CPU to get halted diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl index ef38841..86f2a1d 100644 --- a/tcl/chip/st/spear/spear3xx.tcl +++ b/tcl/chip/st/spear/spear3xx.tcl @@ -19,7 +19,7 @@ proc sp3xx_clock_default {} { mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?) # DDRCORE disable to change frequency - set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000] + set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}] mww 0xfca8002c $val mww 0xfca8002c $val ;# Yes, write twice! @@ -29,7 +29,7 @@ proc sp3xx_clock_default {} { mww 0xfca80008 0x00001c0e ;# enable mww 0xfca80008 0x00001c06 ;# strobe mww 0xfca80008 0x00001c0e - while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 } + while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 } # programming PLL2 mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12 @@ -37,13 +37,13 @@ proc sp3xx_clock_default {} { mww 0xfca80014 0x00001c0e ;# enable mww 0xfca80014 0x00001c06 ;# strobe mww 0xfca80014 0x00001c0e - while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 } + while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 } mww 0xfca80028 0x00000082 ;# enable plltimeen mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2" mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode - while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 } + while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 } # Select source of DDR clock #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1 diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg index c451ca2..250879e 100644 --- a/tcl/fpga/xilinx-xadc.cfg +++ b/tcl/fpga/xilinx-xadc.cfg @@ -16,7 +16,7 @@ proc xadc_cmd {cmd addr data} { READ 0x01 WRITE 0x02 } - return [expr ($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)] + return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}] } # XADC register addresses diff --git a/tcl/memory.tcl b/tcl/memory.tcl index c1e012d..8d50ba8 100644 --- a/tcl/memory.tcl +++ b/tcl/memory.tcl @@ -58,7 +58,7 @@ set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_ set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE proc iswithin { ADDRESS BASE LEN } { - return [expr ((($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0))] + return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}] } proc address_info { ADDRESS } { diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl index 6b2c147..d9b6e63 100644 --- a/tcl/mmr_helpers.tcl +++ b/tcl/mmr_helpers.tcl @@ -2,7 +2,7 @@ proc proc_exists { NAME } { set n [info commands $NAME] set l [string length $n] - return [expr $l != 0] + return [expr {$l != 0}] } # Give: REGISTER name - must be a global variable. @@ -52,7 +52,7 @@ proc show_mmr32_bits { NAMES VAL } { echo -n " " for { set y 7 } { $y >= 0 } { incr y -1 } { - echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr {$w -1}] ""] + echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""] } echo "" } diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index efc773d..cb3e06c 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -103,10 +103,10 @@ proc disable_watchdog { } { # Empty body to make sure this executes as fast as possible. # We don't want any delays here otherwise romcode might start # executing and end up changing state of certain IPs. - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } } } $_TARGETNAME configure -event reset-end { disable_watchdog } diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index e0813ca..e954fd2 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -512,10 +512,10 @@ proc disable_watchdog { } { # Empty body to make sure this executes as fast as possible. # We don't want any delays here otherwise romcode might start # executing and end up changing state of certain IPs. - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 - while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } + while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { } } } @@ -725,13 +725,13 @@ proc emif_prcm_clk_enable { } { proc vtp_enable { } { global VTP_CTRL_REG - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }] mww $VTP_CTRL_REG $vtp - set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }] mww $VTP_CTRL_REG $vtp - set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ] + set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }] mww $VTP_CTRL_REG $vtp } @@ -948,7 +948,7 @@ proc config_ddr3 { SDRAM_CONFIG } { emif_prcm_clk_enable vtp_enable - set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ] + set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }] mww $CM_DLL_CTRL $dll while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { } @@ -978,7 +978,7 @@ proc config_ddr3 { SDRAM_CONFIG } { sleep 10 - set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ] + set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }] mww $EXT_PHY_CTRL_36 $tmp mww $EXT_PHY_CTRL_36_SHDW $tmp diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg index 6647325..ea94be9 100644 --- a/tcl/target/bluenrg-x.cfg +++ b/tcl/target/bluenrg-x.cfg @@ -65,7 +65,7 @@ $_TARGETNAME configure -event resumed { global WDOG_VALUE_SET set _JTAG_IDCODE [mrw 0x40000004] if {$_JTAG_IDCODE != 0x0201E041} { - if [expr $WDOG_VALUE_SET] { + if {$WDOG_VALUE_SET} { # Restore watchdog enable value after resume. Only Bluenrg-1/2 mww 0x40700008 $WDOG_VALUE set WDOG_VALUE_SET 0 diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index 17639fd..f252360 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -26,14 +26,14 @@ proc configC100 {} { dict set configC100 w_amba 1 dict set configC100 x_amba 1 # y = amba_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] # Arm Clk 450MHz, must be a multiple of 25 MHz dict set configC100 CFG_ARM_CLOCK 450000000 dict set configC100 w_arm 0 dict set configC100 x_arm 1 # y = arm_clk * (w+1)*(x+1)*2/xtal_clk - dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] + dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ] } @@ -362,7 +362,7 @@ proc putcUART0 {char} { # convert the 'char' to digit set tmp [ scan $char %c ] # /* wait for room in the tx FIFO on FFUART */ - while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 } + while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 } mww $UART0_THR $tmp if { $char == "\n" } { putcUART0 \r } } diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 9b8256d..2199b7a 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -119,17 +119,17 @@ proc showAmbaClk {} { echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1 # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] + set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] + set x [expr {($value(0) & 0x0001F0000) >> 16}] echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] + set y [expr {($value(0) & 0x00000007F)}] echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] + set w [expr {($value(0) & 0x000000300) >> 8}] echo [format "w: %d" $w] echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } @@ -177,7 +177,7 @@ proc setupAmbaClk {} { mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -194,17 +194,17 @@ proc showArmClk {} { echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1 # see if the PLL is in bypass mode - set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] + set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}] echo [format "PLL bypass bit: %d" $bypass] if {$bypass == 1} { echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] } else { # nope, extract x,y,w and compute the PLL output freq. - set x [expr ($value(0) & 0x0001F0000) >> 16] + set x [expr {($value(0) & 0x0001F0000) >> 16}] echo [format "x: %d" $x] - set y [expr ($value(0) & 0x00000007F)] + set y [expr {($value(0) & 0x00000007F)}] echo [format "y: %d" $y] - set w [expr ($value(0) & 0x000000300) >> 8] + set w [expr {($value(0) & 0x000000300) >> 8}] echo [format "w: %d" $w] echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] } @@ -251,7 +251,7 @@ proc setupArmClk {} { mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 # wait for PLL to lock echo "Waiting for Amba PLL to lock" - while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } + while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 } # remove the internal PLL bypass mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL # remove PLL from BYPASS mode using MUX @@ -442,7 +442,7 @@ proc initC100 {} { # APB init # // Setting APB Bus Wait states to 1, set post write # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40; - mww [expr $APB_ACCESS_WS_REG] 0x40 + mww $APB_ACCESS_WS_REG 0x40 # AHB init # // enable all 6 masters for ARAM mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index ef07856..d2ed592 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -4,7 +4,7 @@ # davinci_pinmux: assigns PINMUX$reg <== $value proc davinci_pinmux {soc reg value} { - mww [expr [dict get $soc sysbase] + 4 * $reg] $value + mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value } source [find mem_helper.tcl] @@ -110,7 +110,7 @@ proc pll_v02_setup {pll_addr mult config} { # write pllcmd.GO; poll pllstat.GO mww [expr {$pll_addr + 0x0138}] 0x01 set pllstat [expr {$pll_addr + 0x013c}] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } } mww [expr {$pll_addr + 0x0138}] 0x00 @@ -272,11 +272,11 @@ proc pll_v03_setup {pll_addr mult config} { # write pllcmd.GO; poll pllstat.GO mww [expr {$pll_addr + 0x0138}] 0x01 set pllstat [expr {$pll_addr + 0x013c}] - while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } + while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 } } mww [expr {$pll_addr + 0x0138}] 0x00 set addr [dict get $config ctladdr] - while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } + while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 } # 12 - set PLLEN (bit 0) ... leave bypass mode set pll_ctrl [expr {$pll_ctrl | 0x0001}] @@ -306,13 +306,13 @@ proc psc_go {} { set ptstat_addr [expr {$psc_addr + 0x0128}] # just in case PTSTAT.go isn't clear - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } # write PTCMD.go ... ignoring any DSP power domain mww [expr {$psc_addr + 0x0120}] 1 # wait for PTSTAT.go to clear (again ignoring DSP power domain) - while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } + while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 } } # diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg index 93375fd..6d919f9 100644 --- a/tcl/target/hilscher_netx500.cfg +++ b/tcl/target/hilscher_netx500.cfg @@ -36,10 +36,10 @@ proc mread32 {addr} { proc sdram_fix { } { set accesskey [mread32 0x00100070] - mww 0x00100070 [expr $accesskey] + mww 0x00100070 $accesskey mww 0x0010002c 0x00000001 - if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { + if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} { puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" } else { puts "SDRAM Fix succeeded!" diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index cdf4f24..cc824ad 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -54,8 +54,8 @@ proc icepick_c_disconnect {jrc} { proc icepick_c_router {jrc rw block register payload} { set new_dr_value \ - [expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ - ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ] + [expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ + ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ] # echo "\tNew router value:\t0x[format %x $new_dr_value]" diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg index b568282..d4ee79f 100644 --- a/tcl/target/psoc4.cfg +++ b/tcl/target/psoc4.cfg @@ -78,18 +78,18 @@ proc psoc4_get_family_id {} { if { $err } { return 0 } - if { [expr $romtable_pid(0) & 0xffffff00 ] - || [expr $romtable_pid(1) & 0xffffff00 ] - || [expr $romtable_pid(2) & 0xffffff00 ] } { + if { [expr {$romtable_pid(0) & 0xffffff00 }] + || [expr {$romtable_pid(1) & 0xffffff00 }] + || [expr {$romtable_pid(2) & 0xffffff00 }] } { echo "Unexpected data in ROMTABLE" return 0 } - set designer_id [expr (( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) ] + set designer_id [expr {(( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) }] if { $designer_id != 0xb4 } { echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id] return 0 } - set family_id [expr ( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) ] + set family_id [expr {( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) }] return $family_id } @@ -194,7 +194,7 @@ proc ocd_process_reset_inner { MODE } { # Set registers to reset vector values mem2array value 32 0 2 - reg pc [expr $value(1) & 0xfffffffe ] + reg pc [expr {$value(1) & 0xfffffffe} ] reg msp $value(0) if { $PSOC4_TEST_MODE_WORKAROUND } { diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 3cab4d1..4865e29 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -83,7 +83,7 @@ proc reset_peripherals {family} { mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 # RCC and RCC2 to their reset values - mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))] + mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}] mww $SYSCTL_RCC2 0x07806810 mww $SYSCTL_RCC 0x078e3ad1 @@ -121,8 +121,8 @@ proc reset_peripherals {family} { mww $SYSCTL_MISC 0xffffffff # Wait for any pending flash operations to complete - while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 } - while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 } + while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 } # Reset the flash controller registers mww $FLASH_FMA 0 @@ -152,7 +152,7 @@ $_TARGETNAME configure -event reset-start { if {$_DEVICECLASS != 0xff} { set device_class $_DEVICECLASS } else { - set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)] + set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}] } if {$device_class == 0 || $device_class == 1 || diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg index 1b2ae7d..e50ef9c 100644 --- a/tcl/target/stm32mp15x.cfg +++ b/tcl/target/stm32mp15x.cfg @@ -107,7 +107,7 @@ proc toggle_cpu0_dbg_claim0 {} { proc detect_cpu1 {} { $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1 - set dual_core [expr $cpu1_prsr(0) & 1] + set dual_core [expr {$cpu1_prsr(0) & 1}] if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine} } diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 15bacf3..5aee135 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -18,12 +18,12 @@ proc ocd_gdb_restart {target_id} { global _TARGETNAME_1 global _SMP targets $_TARGETNAME_1 - if { [expr ($_SMP == 1)] } { + if { $_SMP == 1 } { cortex_a smp off } rst_run halt - if { [expr ($_SMP == 1)]} { + if { $_SMP == 1 } { cortex_a smp on } } diff --git a/tcl/tools/memtest.tcl b/tcl/tools/memtest.tcl index f3567ef..c7fa591 100644 --- a/tcl/tools/memtest.tcl +++ b/tcl/tools/memtest.tcl @@ -166,7 +166,7 @@ proc memTestDevice { baseAddress nBytes } { return $pattern } - set antiPattern [expr ~$pattern] + set antiPattern [expr {~$pattern}] memwrite32 [expr {$baseAddress + $offset}] $antiPattern } @@ -177,7 +177,7 @@ proc memTestDevice { baseAddress nBytes } { set data [memread32 $addr] set dataHex [convertToHex $data] set antiPatternHex [convertToHex $antiPattern] - if {[expr $dataHex != $antiPatternHex]} { + if {$dataHex != $antiPatternHex} { echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset" return $pattern } -- cgit v1.1 From 167adaf841bbf33e9a08ffcc34bc66e8158e6373 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Fri, 30 Apr 2021 12:01:34 +0200 Subject: target/stm8: Make 'stm8_command_handlers' static Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6200 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI Reviewed-by: Antonio Borneo --- src/target/stm8.c | 2 +- src/target/stm8.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/target/stm8.c b/src/target/stm8.c index e99b3c2..2a34ff6 100644 --- a/src/target/stm8.c +++ b/src/target/stm8.c @@ -2159,7 +2159,7 @@ static const struct command_registration stm8_exec_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -const struct command_registration stm8_command_handlers[] = { +static const struct command_registration stm8_command_handlers[] = { { .name = "stm8", .mode = COMMAND_ANY, diff --git a/src/target/stm8.h b/src/target/stm8.h index da7f1f1..b18ff58 100644 --- a/src/target/stm8.h +++ b/src/target/stm8.h @@ -70,6 +70,4 @@ target_to_stm8(struct target *target) return target->arch_info; } -const struct command_registration stm8_command_handlers[]; - #endif /* OPENOCD_TARGET_STM8_H */ -- cgit v1.1 From 40dd1e5284a9d4bb07fdbba5c8e7c5772b06b44f Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Fri, 30 Apr 2021 10:51:35 +0200 Subject: target/riscv: Change 'authdata_read' output Use a constant output length and remove the line break to make the authentication data easier to parse. Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6199 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tim Newsome --- src/target/riscv/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index c883b42..1e93ded 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2372,7 +2372,7 @@ COMMAND_HANDLER(riscv_authdata_read) uint32_t value; if (r->authdata_read(target, &value) != ERROR_OK) return ERROR_FAIL; - command_print(CMD, "0x%" PRIx32, value); + command_print_sameline(CMD, "0x%08" PRIx32, value); return ERROR_OK; } else { LOG_ERROR("authdata_read is not implemented for this target."); -- cgit v1.1 From c5c2a8300136d2c7d536aae3cfad7324372e5dfc Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Mon, 5 Apr 2021 11:13:52 +0200 Subject: Enable adapter "Bus Pirate" by default. The Bus Pirate is now listed in the "OpenOCD configuration summary" too. Change-Id: Ieb7bf9134af456ebe9803f3108a243204fb2a62d Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/5637 Tested-by: jenkins Reviewed-by: Antonio Borneo --- configure.ac | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/configure.ac b/configure.ac index 58be790..e343875 100644 --- a/configure.ac +++ b/configure.ac @@ -148,6 +148,9 @@ m4_define([LIBJAYLINK_ADAPTERS], m4_define([PCIE_ADAPTERS], [[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]]) +m4_define([SERIAL_PORT_ADAPTERS], + [[[buspirate], [Bus Pirate], [BUS_PIRATE]]]) + m4_define([OPTIONAL_LIBRARIES], [[[capstone], [Use Capstone disassembly framework], []]]) @@ -249,6 +252,7 @@ AC_ARG_ADAPTERS([ LIBFTDI_ADAPTERS, LIBFTDI_USB1_ADAPTERS LIBGPIOD_ADAPTERS, + SERIAL_PORT_ADAPTERS, LIBJAYLINK_ADAPTERS ],[auto]) @@ -311,10 +315,6 @@ AC_ARG_ENABLE([gw16012], AS_HELP_STRING([--enable-gw16012], [Enable building support for the Gateworks GW16012 JTAG Programmer]), [build_gw16012=$enableval], [build_gw16012=no]) -AC_ARG_ENABLE([buspirate], - AS_HELP_STRING([--enable-buspirate], [Enable building support for the Buspirate]), - [build_buspirate=$enableval], [build_buspirate=no]) - AC_ARG_ENABLE([sysfsgpio], AS_HELP_STRING([--enable-sysfsgpio], [Enable building support for programming driven via sysfs gpios.]), [build_sysfsgpio=$enableval], [build_sysfsgpio=no]) @@ -399,10 +399,13 @@ AS_CASE([$host], ]) parport_use_giveio=yes - AS_IF([test "x$build_buspirate" = "xyes"], [ + AS_IF([test "x$enable_buspirate" = "xyes"], [ AC_MSG_ERROR([buspirate currently not supported by MinGW32 hosts]) ]) + # In case enable_buspirate=auto, make sure it will not be built. + enable_buspirate=no + AC_SUBST([HOST_CPPFLAGS], [-D__USE_MINGW_ANSI_STDIO]) ], [*darwin*], [ @@ -529,7 +532,7 @@ AS_IF([test "x$build_gw16012" = "xyes"], [ AC_DEFINE([BUILD_GW16012], [0], [0 if you don't want the Gateworks GW16012 driver.]) ]) -AS_IF([test "x$build_buspirate" = "xyes"], [ +AS_IF([test "x$enable_buspirate" != "xno"], [ AC_DEFINE([BUILD_BUSPIRATE], [1], [1 if you want the Buspirate JTAG driver.]) ], [ AC_DEFINE([BUILD_BUSPIRATE], [0], [0 if you don't want the Buspirate JTAG driver.]) @@ -693,7 +696,7 @@ AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x AM_CONDITIONAL([AMTJTAGACCEL], [test "x$build_amtjtagaccel" = "xyes"]) AM_CONDITIONAL([GW16012], [test "x$build_gw16012" = "xyes"]) AM_CONDITIONAL([REMOTE_BITBANG], [test "x$build_remote_bitbang" = "xyes"]) -AM_CONDITIONAL([BUSPIRATE], [test "x$build_buspirate" = "xyes"]) +AM_CONDITIONAL([BUSPIRATE], [test "x$enable_buspirate" != "xno"]) AM_CONDITIONAL([SYSFSGPIO], [test "x$build_sysfsgpio" = "xyes"]) AM_CONDITIONAL([XLNX_PCIE_XVC], [test "x$build_xlnx_pcie_xvc" = "xyes"]) AM_CONDITIONAL([USE_LIBUSB1], [test "x$use_libusb1" = "xyes"]) @@ -778,7 +781,7 @@ m4_foreach([adapter], [USB1_ADAPTERS, HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS, LIBFTDI_USB1_ADAPTERS, LIBGPIOD_ADAPTERS, - LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, + LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS, OPTIONAL_LIBRARIES], [s=m4_format(["%-40s"], ADAPTER_DESC([adapter])) AS_CASE([$ADAPTER_VAR([adapter])], -- cgit v1.1 From 3d46346e07893fe6495a6c17fc06c710196f95e1 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 2 May 2021 23:03:33 +0200 Subject: coding-style: additional style for C code To improve readability and to push more uniform code style. Prefer 'if (false) {...}' for unused code so it get checked by the compiler. Define preferred indentation for 'switch' statement. Require balanced brackets in 'if/else'. Report the max line length. Report the formatting strings for stdint/inttypes types. Report the type 'target_addr_t'. Prefer 'unsigned int' to 'unsigned'. Change-Id: I0192a4ed298f6c6c432764fdd156cffd4b13fc89 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6203 Reviewed-by: Tomas Vanek Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Tarek BOCHKATI Reviewed-by: Marc Schink --- doc/manual/style.txt | 73 +++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 69 insertions(+), 4 deletions(-) diff --git a/doc/manual/style.txt b/doc/manual/style.txt index 755709f..9108899 100644 --- a/doc/manual/style.txt +++ b/doc/manual/style.txt @@ -48,9 +48,55 @@ OpenOCD project. - use Unix line endings ('\\n'); do NOT use DOS endings ('\\r\\n') - limit adjacent empty lines to at most two (2). - remove any trailing empty lines at the end of source files -- do not "comment out" code from the tree; instead, one should either: - -# remove it entirely (git can retrieve the old version), or - -# use an @c \#if/\#endif block. +- do not "comment out" code from the tree nor put it within a block + @code + #if 0 + ... + #endif + @endcode + otherwise it would never be checked at compile time and when new + patches get merged it could be not compilable anymore. + Code that is not fully working nor ready for submission should + instead be removed entirely (git can retrieve the old version). + For exceptional cases that require keeping some unused code, let + the compiler check it by putting it in a block + @code + if (false) { + /* explain why this code should be kept here */ + ... + } + @endcode +- in a @c switch statement align the @c switch with the @c case label + @code + switch (dev_id) { + case 0x0123: + size = 0x10000; + break; + case 0x0412: + size = 0x20000; + break; + default: + size = 0x40000; + break; + } + @endcode +- in an if / then / else statement, if only one of the conditions + require curly brackets due to multi-statement block, put the curly brackets + also to the other condition + @code + if (x > 0) + a = 12 + x; + else + a = 24; + @endcode + @code + if (x > 0) { + a = 12 + x; + } else { + a = 24; + x = 0; + } + @endcode Finally, try to avoid lines of code that are longer than 72-80 columns: @@ -60,6 +106,7 @@ Finally, try to avoid lines of code that are longer than 72-80 columns: - a few lines may be wider than this limit (typically format strings), but: - all C compilers will concatenate series of string constants. - all long string constants should be split across multiple lines. + - do never exceed 120 columns. @section stylenames Naming Rules @@ -104,11 +151,15 @@ or variable length arrays on the stack. non-MMU hosts(uClinux) and pthreads require modest and predictable stack usage. @section styletypes Type Guidelines -- use native types (@c int or @c unsigned) if the type is not important +- use native types (@c int or unsigned int ) if the type is not important - if size matters, use the types from \ or \: - @c int8_t, @c int16_t, @c int32_t, or @c int64_t: signed types of specified size - @c uint8_t, @c uint16_t, @c uint32_t, or @c uint64_t: unsigned types of specified size + - use the associated @c printf and @c scanf formatting strings for these types + (e.g. @c PRId8, PRIx16, SCNu8, ...) - do @b NOT redefine @c uN types from "types.h" + - use type @c target_addr_t for target's address values + - prefer type unsigned int to type @c unsigned @section stylefunc Functions @@ -144,6 +195,20 @@ More directly, do @b not combine these kinds of statements: if ((result = foo()) != ERROR_OK) return result; @endcode +- Do not compare @c bool values with @c true or @c false but use the + value directly +@code +if (!is_enabled) + ... +@endcode +- Avoid comparing pointers with @c NULL +@code +buf = malloc(buf_size); +if (!buf) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; +} +@endcode */ /** @page styledoxygen Doxygen Style Guide -- cgit v1.1 From e05cbb4e4feed04c44c71e4a86fa37f310515b15 Mon Sep 17 00:00:00 2001 From: Daniel Anselmi Date: Sun, 11 Oct 2020 15:13:05 +0200 Subject: Add IPDBG JtagHost functionality to OpenOCD IPDBG are utilities to debug IP-cores. It uses JTAG for transport to/from the FPGA. The different UIs use TCP/IP as transport. The JtagHost makes the bridge between these two. Comparable to the bridge between GDB and the in-circuit- debugging-unit of a micro controller. Change-Id: Ib1bc10dcbd4ea426e492bb7b2d85c1ed1b7a8d5a Signed-off-by: Daniel Anselmi Reviewed-on: http://openocd.zylin.com/5938 Tested-by: jenkins Reviewed-by: Antonio Borneo --- doc/openocd.texi | 43 +++ src/helper/command.h | 42 +++ src/jtag/core.c | 10 +- src/server/Makefile.am | 4 +- src/server/ipdbg.c | 782 +++++++++++++++++++++++++++++++++++++++++++++++++ src/server/ipdbg.h | 11 + 6 files changed, 890 insertions(+), 2 deletions(-) create mode 100644 src/server/ipdbg.c create mode 100644 src/server/ipdbg.h diff --git a/doc/openocd.texi b/doc/openocd.texi index a8a413c..6614f48 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -10585,6 +10585,49 @@ If @emph{xsvfdump} shows a file is using those opcodes, it probably will not be usable with other XSVF tools. +@section IPDBG: JTAG-Host server +@cindex IPDBG JTAG-Host server +@cindex IPDBG + +IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary +waveform generator. These are synthesize-able hardware descriptions of +logic circuits in addition to software for control, visualization and further analysis. +In a session using JTAG for its transport protocol, OpenOCD supports the function +of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the +control-software. For more details see @url{http://ipdbg.org}. + +@deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}] +Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order. + +Command options: +@itemize @bullet +@item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start). +@item @option{-tap @var{tapname}} targeting the TAP @var{tapname}. +@item @option{-hub @var{ir_value}} states that the JTAG hub is +reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}. +@item @option{-port @var{number}} tcp port number where the JTAG-Host is listening. +@item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub. +@item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a +specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an +access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second +parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to +shift data through vir can be configured. +@end itemize +@end deffn + +Examples: +@example +ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4 +@end example +Starts a server listening on tcp-port 4242 which connects to tool 4. +The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board). + +@example +ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1 +@end example +Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1). +The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5). + @node Utility Commands @chapter Utility Commands @cindex Utility Commands diff --git a/src/helper/command.h b/src/helper/command.h index 68f4c14..068df9d 100644 --- a/src/helper/command.h +++ b/src/helper/command.h @@ -427,6 +427,48 @@ DECLARE_PARSE_WRAPPER(_target_addr, target_addr_t); COMMAND_PARSE_NUMBER(target_addr, in, out) /** + * @brief parses the command argument at position @a argn into @a out + * as a @a type, or prints a command error referring to @a name_str + * and passes the error code to the caller. @a argn will be incremented + * if no error occurred. Otherwise the calling function will return + * the error code produced by the parsing function. + * + * This function may cause the calling function to return immediately, + * so it should be used carefully to avoid leaking resources. In most + * situations, parsing should be completed in full before proceeding + * to allocate resources, and this strategy will most prevents leaks. + */ +#define COMMAND_PARSE_ADDITIONAL_NUMBER(type, argn, out, name_str) \ + do { \ + if (argn+1 >= CMD_ARGC || CMD_ARGV[argn+1][0] == '-') { \ + command_print(CMD, "no " name_str " given"); \ + return ERROR_FAIL; \ + } \ + ++argn; \ + COMMAND_PARSE_NUMBER(type, CMD_ARGV[argn], out); \ + } while (0) + +/** + * @brief parses the command argument at position @a argn into @a out + * as a @a type if the argument @a argn does not start with '-'. + * and passes the error code to the caller. @a argn will be incremented + * if no error occurred. Otherwise the calling function will return + * the error code produced by the parsing function. + * + * This function may cause the calling function to return immediately, + * so it should be used carefully to avoid leaking resources. In most + * situations, parsing should be completed in full before proceeding + * to allocate resources, and this strategy will most prevents leaks. + */ +#define COMMAND_PARSE_OPTIONAL_NUMBER(type, argn, out) \ + do { \ + if (argn+1 < CMD_ARGC && CMD_ARGV[argn+1][0] != '-') { \ + ++argn; \ + COMMAND_PARSE_NUMBER(type, CMD_ARGV[argn], out); \ + } \ + } while (0) + +/** * Parse the string @c as a binary parameter, storing the boolean value * in @c out. The strings @c on and @c off are used to match different * strings for true and false options (e.g. "on" and "off" or diff --git a/src/jtag/core.c b/src/jtag/core.c index 37924aa..147df28 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -45,6 +45,9 @@ #include "svf/svf.h" #include "xsvf/xsvf.h" +/* ipdbg are utilities to debug IP-cores. It uses JTAG for transport. */ +#include "server/ipdbg.h" + /** The number of JTAG queue flushes (for profiling and debugging purposes). */ static int jtag_flush_queue_count; @@ -1975,7 +1978,12 @@ static int jtag_select(struct command_context *ctx) if (retval != ERROR_OK) return retval; - return xsvf_register_commands(ctx); + retval = xsvf_register_commands(ctx); + + if (retval != ERROR_OK) + return retval; + + return ipdbg_register_commands(ctx); } static struct transport jtag_transport = { diff --git a/src/server/Makefile.am b/src/server/Makefile.am index d270ee2..5f7469a 100644 --- a/src/server/Makefile.am +++ b/src/server/Makefile.am @@ -10,7 +10,9 @@ noinst_LTLIBRARIES += %D%/libserver.la %D%/tcl_server.c \ %D%/tcl_server.h \ %D%/rtt_server.c \ - %D%/rtt_server.h + %D%/rtt_server.h \ + %D%/ipdbg.c \ + %D%/ipdbg.h %C%_libserver_la_CFLAGS = $(AM_CFLAGS) if IS_MINGW diff --git a/src/server/ipdbg.c b/src/server/ipdbg.c new file mode 100644 index 0000000..ec2fae8 --- /dev/null +++ b/src/server/ipdbg.c @@ -0,0 +1,782 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2020 by Daniel Anselmi */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include + +#include "ipdbg.h" + +#define IPDBG_BUFFER_SIZE 16384 +#define IPDBG_MIN_NUM_OF_OPTIONS 4 +#define IPDBG_MAX_NUM_OF_OPTIONS 14 +#define IPDBG_MIN_DR_LENGTH 11 +#define IPDBG_MAX_DR_LENGTH 13 +#define IPDBG_TCP_PORT_STR_MAX_LENGTH 6 + +/* private connection data for IPDBG */ +struct ipdbg_fifo { + size_t count; + size_t rd_idx; + char buffer[IPDBG_BUFFER_SIZE]; +}; + +struct ipdbg_connection { + struct ipdbg_fifo dn_fifo; + struct ipdbg_fifo up_fifo; + bool closed; +}; + +struct ipdbg_service { + struct ipdbg_hub *hub; + struct ipdbg_service *next; + uint16_t port; + struct ipdbg_connection connection; + uint8_t tool; +}; + +struct ipdbg_virtual_ir_info { + uint32_t instruction; + uint32_t length; + uint32_t value; +}; + +struct ipdbg_hub { + uint32_t user_instruction; + uint32_t max_tools; + uint32_t active_connections; + uint32_t active_services; + uint32_t valid_mask; + uint32_t xoff_mask; + uint32_t tool_mask; + uint32_t last_dn_tool; + struct ipdbg_hub *next; + struct jtag_tap *tap; + struct connection **connections; + uint8_t data_register_length; + uint8_t dn_xoff; + struct ipdbg_virtual_ir_info *virtual_ir; +}; + +static struct ipdbg_hub *ipdbg_first_hub; + +static struct ipdbg_service *ipdbg_first_service; + +static void ipdbg_init_fifo(struct ipdbg_fifo *fifo) +{ + fifo->count = 0; + fifo->rd_idx = 0; +} + +static bool ipdbg_fifo_is_empty(struct ipdbg_fifo *fifo) +{ + return fifo->count == 0; +} + +static bool ipdbg_fifo_is_full(struct ipdbg_fifo *fifo) +{ + return fifo->count == IPDBG_BUFFER_SIZE; +} + +static void ipdbg_zero_rd_idx(struct ipdbg_fifo *fifo) +{ + if (fifo->rd_idx == 0) + return; + + size_t ri = fifo->rd_idx; + for (size_t idx = 0 ; idx < fifo->count ; ++idx) + fifo->buffer[idx] = fifo->buffer[ri++]; + fifo->rd_idx = 0; +} + +static void ipdbg_append_to_fifo(struct ipdbg_fifo *fifo, char data) +{ + if (ipdbg_fifo_is_full(fifo)) + return; + + ipdbg_zero_rd_idx(fifo); + fifo->buffer[fifo->count++] = data; +} + +static char ipdbg_get_from_fifo(struct ipdbg_fifo *fifo) +{ + if (ipdbg_fifo_is_empty(fifo)) + return 0; + + fifo->count--; + return fifo->buffer[fifo->rd_idx++]; +} + +static int ipdbg_move_buffer_to_connection(struct connection *conn, struct ipdbg_fifo *fifo) +{ + if (ipdbg_fifo_is_empty(fifo)) + return ERROR_OK; + + struct ipdbg_connection *connection = conn->priv; + if (connection->closed) + return ERROR_SERVER_REMOTE_CLOSED; + + ipdbg_zero_rd_idx(fifo); + size_t bytes_written = connection_write(conn, fifo->buffer, fifo->count); + if (bytes_written != fifo->count) { + LOG_ERROR("error during write: %zu != %zu", bytes_written, fifo->count); + connection->closed = true; + return ERROR_SERVER_REMOTE_CLOSED; + } + + fifo->count -= bytes_written; + + return ERROR_OK; +} + +static int ipdbg_max_tools_from_data_register_length(uint8_t data_register_length) +{ + int max_tools = 1; + data_register_length -= 10; /* 8 bit payload, 1 xoff-flag, 1 valid-flag; remaining bits used to select tool*/ + while (data_register_length--) + max_tools *= 2; + + /* last tool is used to reset JtagCDC and transfer "XON" to host*/ + return max_tools - 1; +} + +static struct ipdbg_service *ipdbg_find_service(struct ipdbg_hub *hub, uint8_t tool) +{ + struct ipdbg_service *service; + for (service = ipdbg_first_service ; service ; service = service->next) { + if (service->hub == hub && service->tool == tool) + break; + } + return service; +} + +static void ipdbg_add_service(struct ipdbg_service *service) +{ + struct ipdbg_service *iservice; + if (ipdbg_first_service) { + for (iservice = ipdbg_first_service ; iservice->next; iservice = iservice->next) + ; + iservice->next = service; + } else + ipdbg_first_service = service; +} + +static int ipdbg_create_service(struct ipdbg_hub *hub, uint8_t tool, struct ipdbg_service **service, uint16_t port) +{ + *service = calloc(1, sizeof(struct ipdbg_service)); + if (!*service) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + (*service)->hub = hub; + (*service)->tool = tool; + (*service)->port = port; + + return ERROR_OK; +} + +static int ipdbg_remove_service(struct ipdbg_service *service) +{ + if (!ipdbg_first_service) + return ERROR_FAIL; + + if (service == ipdbg_first_service) { + ipdbg_first_service = ipdbg_first_service->next; + return ERROR_OK; + } + + for (struct ipdbg_service *iservice = ipdbg_first_service ; iservice->next ; iservice = iservice->next) { + if (service == iservice->next) { + iservice->next = service->next; + return ERROR_OK; + } + } + return ERROR_FAIL; +} + +static struct ipdbg_hub *ipdbg_find_hub(struct jtag_tap *tap, + uint32_t user_instruction, struct ipdbg_virtual_ir_info *virtual_ir) +{ + struct ipdbg_hub *hub = NULL; + for (hub = ipdbg_first_hub ; hub ; hub = hub->next) { + if (hub->tap == tap && hub->user_instruction == user_instruction) { + if ((!virtual_ir && !hub->virtual_ir) || + (virtual_ir && hub->virtual_ir && + virtual_ir->instruction == hub->virtual_ir->instruction && + virtual_ir->length == hub->virtual_ir->length && + virtual_ir->value == hub->virtual_ir->value)) { + break; + } + } + } + return hub; +} + +static void ipdbg_add_hub(struct ipdbg_hub *hub) +{ + struct ipdbg_hub *ihub; + if (ipdbg_first_hub) { + for (ihub = ipdbg_first_hub ; ihub->next; ihub = ihub->next) + ; + ihub->next = hub; + } else + ipdbg_first_hub = hub; +} + +static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uint8_t data_register_length, + struct ipdbg_virtual_ir_info *virtual_ir, struct ipdbg_hub **hub) +{ + *hub = NULL; + struct ipdbg_hub *new_hub = calloc(1, sizeof(struct ipdbg_hub)); + if (!new_hub) { + free(virtual_ir); + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + new_hub->max_tools = ipdbg_max_tools_from_data_register_length(data_register_length); + new_hub->connections = calloc(new_hub->max_tools, sizeof(struct connection *)); + if (!new_hub->connections) { + free(virtual_ir); + free(new_hub); + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + new_hub->tap = tap; + new_hub->user_instruction = user_instruction; + new_hub->data_register_length = data_register_length; + new_hub->valid_mask = BIT(data_register_length - 1); + new_hub->xoff_mask = BIT(data_register_length - 2); + new_hub->tool_mask = (new_hub->xoff_mask - 1) >> 8; + new_hub->last_dn_tool = new_hub->tool_mask; + new_hub->virtual_ir = virtual_ir; + + *hub = new_hub; + + return ERROR_OK; +} + +static void ipdbg_free_hub(struct ipdbg_hub *hub) +{ + if (!hub) + return; + free(hub->connections); + free(hub->virtual_ir); + free(hub); +} + +static int ipdbg_remove_hub(struct ipdbg_hub *hub) +{ + if (!ipdbg_first_hub) + return ERROR_FAIL; + if (hub == ipdbg_first_hub) { + ipdbg_first_hub = ipdbg_first_hub->next; + return ERROR_OK; + } + + for (struct ipdbg_hub *ihub = ipdbg_first_hub ; ihub->next ; ihub = ihub->next) { + if (hub == ihub->next) { + ihub->next = hub->next; + return ERROR_OK; + } + } + + return ERROR_FAIL; +} + +static void ipdbg_init_scan_field(struct scan_field *fields, uint8_t *in_value, int num_bits, const uint8_t *out_value) +{ + fields->check_mask = NULL; + fields->check_value = NULL; + fields->in_value = in_value; + fields->num_bits = num_bits; + fields->out_value = out_value; +} + +static int ipdbg_shift_instr(struct ipdbg_hub *hub, uint32_t instr) +{ + if (!hub) + return ERROR_FAIL; + + struct jtag_tap *tap = hub->tap; + if (!tap) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == instr) { + /* there is already the requested instruction in the ir */ + return ERROR_OK; + } + + uint8_t *ir_out_val = calloc(DIV_ROUND_UP(tap->ir_length, 8), 1); + buf_set_u32(ir_out_val, 0, tap->ir_length, instr); + + struct scan_field fields; + ipdbg_init_scan_field(&fields, NULL, tap->ir_length, ir_out_val); + jtag_add_ir_scan(tap, &fields, TAP_IDLE); + int retval = jtag_execute_queue(); + + free(ir_out_val); + + return retval; +} + +static int ipdbg_shift_vir(struct ipdbg_hub *hub) +{ + if (!hub) + return ERROR_FAIL; + + if (!hub->virtual_ir) + return ERROR_OK; + + int retval = ipdbg_shift_instr(hub, hub->virtual_ir->instruction); + if (retval != ERROR_OK) + return retval; + + struct jtag_tap *tap = hub->tap; + if (!tap) + return ERROR_FAIL; + + uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->virtual_ir->length, 8), 1); + buf_set_u32(dr_out_val, 0, hub->virtual_ir->length, hub->virtual_ir->value); + + struct scan_field fields; + ipdbg_init_scan_field(&fields, NULL, hub->virtual_ir->length, dr_out_val); + jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE); + retval = jtag_execute_queue(); + + free(dr_out_val); + + return retval; +} + +static int ipdbg_shift_data(struct ipdbg_hub *hub, uint32_t dn_data, uint32_t *up_data) +{ + if (!hub) + return ERROR_FAIL; + + struct jtag_tap *tap = hub->tap; + if (!tap) + return ERROR_FAIL; + + uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1); + buf_set_u32(dr_out_val, 0, hub->data_register_length, dn_data); + uint8_t *dr_in_val = up_data ? calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1) : NULL; + + struct scan_field fields; + ipdbg_init_scan_field(&fields, dr_in_val, hub->data_register_length, dr_out_val); + jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE); + int retval = jtag_execute_queue(); + + if (up_data && retval == ERROR_OK) + *up_data = buf_get_u32(dr_in_val, 0, hub->data_register_length); + + free(dr_out_val); + free(dr_in_val); + + return retval; +} + +static int ipdbg_distribute_data_from_hub(struct ipdbg_hub *hub, uint32_t up) +{ + const bool valid_up_data = up & hub->valid_mask; + if (!valid_up_data) + return ERROR_OK; + + const size_t tool = (up >> 8) & hub->tool_mask; + if (tool == hub->tool_mask) { + const uint8_t xon_cmd = up & 0x00ff; + hub->dn_xoff &= ~xon_cmd; + LOG_INFO("received xon cmd: %d\n", xon_cmd); + return ERROR_OK; + } + + struct connection *conn = hub->connections[tool]; + if (conn) { + struct ipdbg_connection *connection = conn->priv; + if (ipdbg_fifo_is_full(&connection->up_fifo)) { + int retval = ipdbg_move_buffer_to_connection(conn, &connection->up_fifo); + if (retval != ERROR_OK) + return retval; + } + ipdbg_append_to_fifo(&connection->up_fifo, up); + } + return ERROR_OK; +} + +static int ipdbg_jtag_transfer_byte(struct ipdbg_hub *hub, size_t tool, struct ipdbg_connection *connection) +{ + uint32_t dn = hub->valid_mask | ((tool & hub->tool_mask) << 8) | + (0x00fful & ipdbg_get_from_fifo(&connection->dn_fifo)); + uint32_t up = 0; + int ret = ipdbg_shift_data(hub, dn, &up); + if (ret != ERROR_OK) + return ret; + + ret = ipdbg_distribute_data_from_hub(hub, up); + if (ret != ERROR_OK) + return ret; + + if ((up & hub->xoff_mask) && (hub->last_dn_tool != hub->max_tools)) { + hub->dn_xoff |= BIT(hub->last_dn_tool); + LOG_INFO("tool %d sent xoff", hub->last_dn_tool); + } + + hub->last_dn_tool = tool; + + return ERROR_OK; +} + +static int ipdbg_polling_callback(void *priv) +{ + struct ipdbg_hub *hub = priv; + + int ret = ipdbg_shift_vir(hub); + if (ret != ERROR_OK) + return ret; + + ret = ipdbg_shift_instr(hub, hub->user_instruction); + if (ret != ERROR_OK) + return ret; + + /* transfer dn buffers to jtag-hub */ + unsigned int num_transfers = 0; + for (size_t tool = 0 ; tool < hub->max_tools ; ++tool) { + struct connection *conn = hub->connections[tool]; + if (conn && conn->priv) { + struct ipdbg_connection *connection = conn->priv; + while (((hub->dn_xoff & BIT(tool)) == 0) && !ipdbg_fifo_is_empty(&connection->dn_fifo)) { + ret = ipdbg_jtag_transfer_byte(hub, tool, connection); + if (ret != ERROR_OK) + return ret; + ++num_transfers; + } + } + } + + /* some transfers to get data from jtag-hub in case there is no dn data */ + while (num_transfers++ < hub->max_tools) { + uint32_t dn = 0; + uint32_t up = 0; + + int retval = ipdbg_shift_data(hub, dn, &up); + if (retval != ERROR_OK) + return ret; + + retval = ipdbg_distribute_data_from_hub(hub, up); + if (retval != ERROR_OK) + return ret; + } + + /* write from up fifos to sockets */ + for (size_t tool = 0 ; tool < hub->max_tools ; ++tool) { + struct connection *conn = hub->connections[tool]; + if (conn && conn->priv) { + struct ipdbg_connection *connection = conn->priv; + int retval = ipdbg_move_buffer_to_connection(conn, &connection->up_fifo); + if (retval != ERROR_OK) + return retval; + } + } + + return ERROR_OK; +} + +static int ipdbg_start_polling(struct ipdbg_service *service, struct connection *connection) +{ + struct ipdbg_hub *hub = service->hub; + hub->connections[service->tool] = connection; + hub->active_connections++; + if (hub->active_connections > 1) { + /* hub is already initialized */ + return ERROR_OK; + } + + const uint32_t reset_hub = hub->valid_mask | ((hub->max_tools) << 8); + + int ret = ipdbg_shift_vir(hub); + if (ret != ERROR_OK) + return ret; + + ret = ipdbg_shift_instr(hub, hub->user_instruction); + if (ret != ERROR_OK) + return ret; + + ret = ipdbg_shift_data(hub, reset_hub, NULL); + hub->last_dn_tool = hub->tool_mask; + hub->dn_xoff = 0; + if (ret != ERROR_OK) + return ret; + + LOG_INFO("IPDBG start_polling"); + + const int time_ms = 20; + const int periodic = 1; + return target_register_timer_callback(ipdbg_polling_callback, time_ms, periodic, hub); +} + +static int ipdbg_stop_polling(struct ipdbg_service *service) +{ + struct ipdbg_hub *hub = service->hub; + hub->connections[service->tool] = NULL; + hub->active_connections--; + if (hub->active_connections == 0) { + LOG_INFO("IPDBG stop_polling"); + + return target_unregister_timer_callback(ipdbg_polling_callback, hub); + } + + return ERROR_OK; +} + +static int ipdbg_on_new_connection(struct connection *connection) +{ + struct ipdbg_service *service = connection->service->priv; + connection->priv = &service->connection; + /* initialize ipdbg connection information */ + ipdbg_init_fifo(&service->connection.up_fifo); + ipdbg_init_fifo(&service->connection.dn_fifo); + + int retval = ipdbg_start_polling(service, connection); + if (retval != ERROR_OK) { + LOG_ERROR("BUG: ipdbg_start_polling failed"); + return retval; + } + + struct ipdbg_connection *conn = connection->priv; + conn->closed = false; + + LOG_INFO("New IPDBG Connection"); + + return ERROR_OK; +} + +static int ipdbg_on_connection_input(struct connection *connection) +{ + struct ipdbg_connection *conn = connection->priv; + struct ipdbg_fifo *fifo = &conn->dn_fifo; + + if (ipdbg_fifo_is_full(fifo)) + return ERROR_OK; + + ipdbg_zero_rd_idx(fifo); + int bytes_read = connection_read(connection, fifo->buffer + fifo->count, IPDBG_BUFFER_SIZE - fifo->count); + if (bytes_read <= 0) { + if (bytes_read < 0) + LOG_ERROR("error during read: %s", strerror(errno)); + return ERROR_SERVER_REMOTE_CLOSED; + } + + fifo->count += bytes_read; + + return ERROR_OK; +} + +static int ipdbg_on_connection_closed(struct connection *connection) +{ + struct ipdbg_connection *conn = connection->priv; + conn->closed = true; + LOG_INFO("Closed IPDBG Connection"); + + return ipdbg_stop_polling(connection->service->priv); +} + +static int ipdbg_start(uint16_t port, struct jtag_tap *tap, uint32_t user_instruction, + uint8_t data_register_length, struct ipdbg_virtual_ir_info *virtual_ir, uint8_t tool) +{ + LOG_INFO("starting ipdbg service on port %d for tool %d", port, tool); + + struct ipdbg_hub *hub = ipdbg_find_hub(tap, user_instruction, virtual_ir); + if (hub) { + free(virtual_ir); + if (hub->data_register_length != data_register_length) { + LOG_DEBUG("hub must have the same data_register_length for all tools"); + return ERROR_FAIL; + } + } else { + int retval = ipdbg_create_hub(tap, user_instruction, data_register_length, virtual_ir, &hub); + if (retval != ERROR_OK) { + free(virtual_ir); + return retval; + } + } + + struct ipdbg_service *service = NULL; + int retval = ipdbg_create_service(hub, tool, &service, port); + + if (retval != ERROR_OK || !service) { + if (hub->active_services == 0 && hub->active_connections == 0) + ipdbg_free_hub(hub); + return ERROR_FAIL; + } + + char port_str_buffer[IPDBG_TCP_PORT_STR_MAX_LENGTH]; + snprintf(port_str_buffer, IPDBG_TCP_PORT_STR_MAX_LENGTH, "%u", port); + retval = add_service("ipdbg", port_str_buffer, 1, &ipdbg_on_new_connection, + &ipdbg_on_connection_input, &ipdbg_on_connection_closed, service); + if (retval == ERROR_OK) { + ipdbg_add_service(service); + if (hub->active_services == 0 && hub->active_connections == 0) + ipdbg_add_hub(hub); + hub->active_services++; + } else { + if (hub->active_services == 0 && hub->active_connections == 0) + ipdbg_free_hub(hub); + free(service); + } + + return retval; +} + +static int ipdbg_stop(struct jtag_tap *tap, uint32_t user_instruction, + struct ipdbg_virtual_ir_info *virtual_ir, uint8_t tool) +{ + struct ipdbg_hub *hub = ipdbg_find_hub(tap, user_instruction, virtual_ir); + free(virtual_ir); + if (!hub) + return ERROR_FAIL; + + struct ipdbg_service *service = ipdbg_find_service(hub, tool); + if (!service) + return ERROR_FAIL; + + int retval = ipdbg_remove_service(service); + if (retval != ERROR_OK) { + LOG_ERROR("BUG: ipdbg_remove_service failed"); + return retval; + } + + char port_str_buffer[IPDBG_TCP_PORT_STR_MAX_LENGTH]; + snprintf(port_str_buffer, IPDBG_TCP_PORT_STR_MAX_LENGTH, "%u", service->port); + retval = remove_service("ipdbg", port_str_buffer); + /* The ipdbg_service structure is freed by server.c:remove_service(). + There the "priv" pointer is freed.*/ + if (retval != ERROR_OK) { + LOG_ERROR("BUG: remove_service failed"); + return retval; + } + hub->active_services--; + if (hub->active_connections == 0 && hub->active_services == 0) { + retval = ipdbg_remove_hub(hub); + if (retval != ERROR_OK) { + LOG_ERROR("BUG: ipdbg_remove_hub failed"); + return retval; + } + ipdbg_free_hub(hub); + } + return ERROR_OK; +} + +COMMAND_HANDLER(handle_ipdbg_command) +{ + struct jtag_tap *tap = NULL; + uint16_t port = 4242; + uint8_t tool = 1; + uint32_t user_instruction = 0x00; + uint8_t data_register_length = IPDBG_MAX_DR_LENGTH; + bool start = true; + bool hub_configured = false; + bool has_virtual_ir = false; + uint32_t virtual_ir_instruction = 0x00e; + uint32_t virtual_ir_length = 5; + uint32_t virtual_ir_value = 0x11; + struct ipdbg_virtual_ir_info *virtual_ir = NULL; + + if ((CMD_ARGC < IPDBG_MIN_NUM_OF_OPTIONS) || (CMD_ARGC > IPDBG_MAX_NUM_OF_OPTIONS)) + return ERROR_COMMAND_SYNTAX_ERROR; + + for (unsigned int i = 0; i < CMD_ARGC; ++i) { + if (strcmp(CMD_ARGV[i], "-tap") == 0) { + if (i + 1 >= CMD_ARGC || CMD_ARGV[i + 1][0] == '-') { + command_print(CMD, "no TAP given"); + return ERROR_FAIL; + } + tap = jtag_tap_by_string(CMD_ARGV[i + 1]); + if (!tap) { + command_print(CMD, "Tap %s unknown", CMD_ARGV[i + 1]); + return ERROR_FAIL; + } + ++i; + } else if (strcmp(CMD_ARGV[i], "-hub") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u32, i, user_instruction, "ir_value to select hub"); + hub_configured = true; + COMMAND_PARSE_OPTIONAL_NUMBER(u8, i, data_register_length); + if (data_register_length < IPDBG_MIN_DR_LENGTH || + data_register_length > IPDBG_MAX_DR_LENGTH) { + command_print(CMD, "length of \"user\"-data register must be at least %d and at most %d.", + IPDBG_MIN_DR_LENGTH, IPDBG_MAX_DR_LENGTH); + return ERROR_FAIL; + } + } else if (strcmp(CMD_ARGV[i], "-vir") == 0) { + COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_value); + COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_length); + COMMAND_PARSE_OPTIONAL_NUMBER(u32, i, virtual_ir_instruction); + has_virtual_ir = true; + } else if (strcmp(CMD_ARGV[i], "-port") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u16, i, port, "port number"); + } else if (strcmp(CMD_ARGV[i], "-tool") == 0) { + COMMAND_PARSE_ADDITIONAL_NUMBER(u8, i, tool, "tool"); + } else if (strcmp(CMD_ARGV[i], "-stop") == 0) { + start = false; + } else if (strcmp(CMD_ARGV[i], "-start") == 0) { + start = true; + } else { + command_print(CMD, "Unknown argument: %s", CMD_ARGV[i]); + return ERROR_FAIL; + } + } + + if (!tap) { + command_print(CMD, "no valid tap selected"); + return ERROR_FAIL; + } + + if (!hub_configured) { + command_print(CMD, "hub not configured correctly"); + return ERROR_FAIL; + } + + if (tool >= ipdbg_max_tools_from_data_register_length(data_register_length)) { + command_print(CMD, "Tool: %d is invalid", tool); + return ERROR_FAIL; + } + + if (has_virtual_ir) { + virtual_ir = calloc(1, sizeof(struct ipdbg_virtual_ir_info)); + if (!virtual_ir) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + virtual_ir->instruction = virtual_ir_instruction; + virtual_ir->length = virtual_ir_length; + virtual_ir->value = virtual_ir_value; + } + + if (start) + return ipdbg_start(port, tap, user_instruction, data_register_length, virtual_ir, tool); + else + return ipdbg_stop(tap, user_instruction, virtual_ir, tool); +} + +static const struct command_registration ipdbg_command_handlers[] = { + { + .name = "ipdbg", + .handler = handle_ipdbg_command, + .mode = COMMAND_EXEC, + .help = "Starts or stops an IPDBG JTAG-Host server.", + .usage = "[-start|-stop] -tap device.tap -hub ir_value [dr_length]" + " [-port number] [-tool number] [-vir [vir_value [length [instr_code]]]]", + }, + COMMAND_REGISTRATION_DONE +}; + +int ipdbg_register_commands(struct command_context *cmd_ctx) +{ + return register_commands(cmd_ctx, NULL, ipdbg_command_handlers); +} diff --git a/src/server/ipdbg.h b/src/server/ipdbg.h new file mode 100644 index 0000000..6b70545 --- /dev/null +++ b/src/server/ipdbg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2020 by Daniel Anselmi */ + +#ifndef OPENOCD_IPDBG_IPDBG_H +#define OPENOCD_IPDBG_IPDBG_H + +#include + +int ipdbg_register_commands(struct command_context *cmd_ctx); + +#endif /* OPENOCD_IPDBG_IPDBG_H */ -- cgit v1.1 From aa952a1b773b65e8f469a5c04600b46e4f37a701 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Sat, 1 May 2021 16:22:51 +0200 Subject: flash/nor/xcf: Do not use 'Yoda conditions' Change-Id: I17308f5237338ce468e5b86289a0634429deaaa9 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6201 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo --- src/flash/nor/xcf.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c index 0cef43b..01329f4 100644 --- a/src/flash/nor/xcf.c +++ b/src/flash/nor/xcf.c @@ -169,7 +169,7 @@ static int isc_enter(struct flash_bank *bank) jtag_execute_queue(); status = read_status(bank); - if (false == status.isc_mode) { + if (!status.isc_mode) { LOG_ERROR("*** XCF: FAILED to enter ISC mode"); return ERROR_FLASH_OPERATION_FAILED; } @@ -183,7 +183,7 @@ static int isc_leave(struct flash_bank *bank) struct xcf_status status = read_status(bank); - if (false == status.isc_mode) + if (!status.isc_mode) return ERROR_OK; else { struct scan_field scan; @@ -199,7 +199,7 @@ static int isc_leave(struct flash_bank *bank) alive_sleep(1); /* device needs 50 uS to leave ISC mode */ status = read_status(bank); - if (true == status.isc_mode) { + if (status.isc_mode) { LOG_ERROR("*** XCF: FAILED to leave ISC mode"); return ERROR_FLASH_OPERATION_FAILED; } @@ -280,7 +280,7 @@ static int isc_set_register(struct flash_bank *bank, const uint8_t *cmd, scan.in_value = NULL; jtag_add_dr_scan(bank->target->tap, 1, &scan, TAP_IDLE); - if (0 == timeout_ms) + if (timeout_ms == 0) return jtag_execute_queue(); else return isc_wait_erase_program(bank, timeout_ms); @@ -311,7 +311,7 @@ static int isc_program_register(struct flash_bank *bank, const uint8_t *cmd, scan.in_value = NULL; jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE); - if (0 == timeout_ms) + if (timeout_ms == 0) return jtag_execute_queue(); else return isc_wait_erase_program(bank, timeout_ms); @@ -409,7 +409,7 @@ static bool need_bit_reverse(const uint8_t *buffer) reference[18] = 0xAA; reference[19] = 0x66; - if (0 == memcmp(reference, buffer, L)) + if (memcmp(reference, buffer, L) == 0) return false; else return true; @@ -444,7 +444,7 @@ static int read_write_data(struct flash_bank *bank, const uint8_t *w_buffer, goto EXIT; } - if ((write_flag) && (0 == offset) && (count >= XCF_PAGE_SIZE)) + if ((write_flag) && (offset == 0) && (count >= XCF_PAGE_SIZE)) revbit = need_bit_reverse(w_buffer); while (count > 0) { @@ -585,7 +585,7 @@ static int xcf_info(struct flash_bank *bank, char *buf, int buf_size) { const struct xcf_priv *priv = bank->driver_priv; - if (false == priv->probed) { + if (!priv->probed) { snprintf(buf, buf_size, "\nXCF flash bank not probed yet\n"); return ERROR_OK; } @@ -598,7 +598,7 @@ static int xcf_probe(struct flash_bank *bank) struct xcf_priv *priv = bank->driver_priv; uint32_t id; - if (true == priv->probed) + if (priv->probed) free(bank->sectors); priv->probed = false; @@ -629,7 +629,7 @@ static int xcf_probe(struct flash_bank *bank) } bank->sectors = malloc(bank->num_sectors * sizeof(struct flash_sector)); - if (NULL == bank->sectors) { + if (bank->sectors == NULL) { LOG_ERROR("No memory for sector table"); return ERROR_FAIL; } @@ -652,7 +652,7 @@ static int xcf_auto_probe(struct flash_bank *bank) { struct xcf_priv *priv = bank->driver_priv; - if (true == priv->probed) + if (priv->probed) return ERROR_OK; else return xcf_probe(bank); -- cgit v1.1 From 5d9de1c40090d81288adc85d06c734984b2c5de1 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Tue, 12 Jan 2021 20:11:11 +0100 Subject: cortex_m: add armv8m special registers Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6016 Tested-by: jenkins Reviewed-by: Tomas Vanek --- src/target/armv7m.c | 57 +++++++++++++++++++++++++++++++++++++++------------ src/target/armv7m.h | 44 +++++++++++++++++++++++++++++++++++++++ src/target/cortex_m.c | 3 +++ 3 files changed, 91 insertions(+), 13 deletions(-) diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 101094a..2bcb8ab 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -125,6 +125,29 @@ static const struct { { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, { ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + /* ARMv8-M specific registers */ + { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" }, + + { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL }, + { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + + { ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL }, + { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" }, + + /* FPU registers */ { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" }, @@ -243,6 +266,15 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id) case ARMV7M_PMSK_BPRI_FLTMSK_CTRL: return ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL; + case ARMV8M_MSP_NS...ARMV8M_PSPLIM_NS: + return arm_reg_id - ARMV8M_MSP_NS + ARMV8M_REGSEL_MSP_NS; + + case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S: + return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S; + + case ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS: + return ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS; + case ARMV7M_FPSCR: return ARMV7M_REGSEL_FPSCR; @@ -258,28 +290,26 @@ static uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id) static bool armv7m_map_reg_packing(unsigned int arm_reg_id, unsigned int *reg32_id, uint32_t *offset) { + switch (arm_reg_id) { - case ARMV7M_PRIMASK: + case ARMV7M_PRIMASK...ARMV7M_CONTROL: *reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL; - *offset = 0; + *offset = arm_reg_id - ARMV7M_PRIMASK; return true; - case ARMV7M_BASEPRI: - *reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL; - *offset = 1; + case ARMV8M_PRIMASK_S...ARMV8M_CONTROL_S: + *reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S; + *offset = arm_reg_id - ARMV8M_PRIMASK_S; return true; - case ARMV7M_FAULTMASK: - *reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL; - *offset = 2; - return true; - case ARMV7M_CONTROL: - *reg32_id = ARMV7M_PMSK_BPRI_FLTMSK_CTRL; - *offset = 3; + case ARMV8M_PRIMASK_NS...ARMV8M_CONTROL_NS: + *reg32_id = ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS; + *offset = arm_reg_id - ARMV8M_PRIMASK_NS; return true; default: return false; } + } static int armv7m_read_core_reg(struct target *target, struct reg *r, @@ -743,7 +773,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) reg_list[i].value = arch_info[i].value; reg_list[i].dirty = false; reg_list[i].valid = false; - reg_list[i].hidden = i == ARMV7M_PMSK_BPRI_FLTMSK_CTRL; + reg_list[i].hidden = (i == ARMV7M_PMSK_BPRI_FLTMSK_CTRL || + i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS || i == ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S); reg_list[i].type = &armv7m_reg_type; reg_list[i].arch_info = &arch_info[i]; diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 652dbe7..588470f 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -60,7 +60,18 @@ enum { ARMV7M_REGSEL_MSP, ARMV7M_REGSEL_PSP, + ARMV8M_REGSEL_MSP_NS = 0x18, + ARMV8M_REGSEL_PSP_NS, + ARMV8M_REGSEL_MSP_S, + ARMV8M_REGSEL_PSP_S, + ARMV8M_REGSEL_MSPLIM_S, + ARMV8M_REGSEL_PSPLIM_S, + ARMV8M_REGSEL_MSPLIM_NS, + ARMV8M_REGSEL_PSPLIM_NS, + ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22, + ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23, ARMV7M_REGSEL_FPSCR = 0x21, /* 32bit Floating-point registers */ @@ -129,6 +140,8 @@ enum { /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */ + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ /* working register for packing/unpacking special regs, hidden from gdb */ ARMV7M_PMSK_BPRI_FLTMSK_CTRL, @@ -142,6 +155,35 @@ enum { ARMV7M_BASEPRI, ARMV7M_FAULTMASK, ARMV7M_CONTROL, + /* The end of block of container and contained registers */ + + /* ARMv8-M specific registers */ + ARMV8M_MSP_NS, + ARMV8M_PSP_NS, + ARMV8M_MSP_S, + ARMV8M_PSP_S, + ARMV8M_MSPLIM_S, + ARMV8M_PSPLIM_S, + ARMV8M_MSPLIM_NS, + ARMV8M_PSPLIM_NS, + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, + ARMV8M_PRIMASK_S, + ARMV8M_BASEPRI_S, + ARMV8M_FAULTMASK_S, + ARMV8M_CONTROL_S, + /* The end of block of container and contained registers */ + + /* A block of container and contained registers follows: + * THE ORDER IS IMPORTANT to the end of the block ! */ + ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, + ARMV8M_PRIMASK_NS, + ARMV8M_BASEPRI_NS, + ARMV8M_FAULTMASK_NS, + ARMV8M_CONTROL_NS, + /* The end of block of container and contained registers */ /* 64bit Floating-point registers */ ARMV7M_D0, @@ -170,6 +212,8 @@ enum { ARMV7M_CORE_LAST_REG = ARMV7M_xPSR, ARMV7M_FPU_FIRST_REG = ARMV7M_D0, ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR, + ARMV8M_FIRST_REG = ARMV8M_MSP_NS, + ARMV8M_LAST_REG = ARMV8M_CONTROL_NS, }; enum { diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 982f550..e35cdbe 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -2069,6 +2069,9 @@ int cortex_m_examine(struct target *target) for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++) armv7m->arm.core_cache->reg_list[idx].exist = false; + if (!armv7m->arm.is_armv8m) + for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++) + armv7m->arm.core_cache->reg_list[idx].exist = false; if (!armv7m->stlink) { if (core == 3 || core == 4) -- cgit v1.1 From 77b28ced14321fbedb9493729a377856bab28144 Mon Sep 17 00:00:00 2001 From: Evgeniy Didin Date: Tue, 16 Feb 2021 21:53:41 +0300 Subject: rtos: Add support for Zephyr RTOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With this patch, the Zephyr[1] RTOS is supported by OpenOCD. As usual with support for other RTOSes, Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols with information needed in order to build the list of threads. The current implementation is limited to Zephyr running on ARM Cortex-M processors. This is the only ARM variant supported by Zephyr at the moment and is used on most of the officially supported boards. [1] https://www.zephyrproject.org/ Change-Id: I22afdbec91562f3a22cf5b88cd4ea3a7a59ba0b4 Signed-off-by: Evgeniy Didin Signed-off-by: Leandro Pereira Signed-off-by: Daniel Glƶckner Reviewed-on: http://openocd.zylin.com/4988 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Antonio Borneo --- doc/openocd.texi | 12 +- src/rtos/Makefile.am | 1 + src/rtos/rtos.c | 2 + src/rtos/zephyr.c | 788 +++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 800 insertions(+), 3 deletions(-) create mode 100644 src/rtos/zephyr.c diff --git a/doc/openocd.texi b/doc/openocd.texi index 6614f48..fc44833 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4681,7 +4681,7 @@ The value should normally correspond to a static mapping for the @var{rtos_type} can be one of @option{auto}, @option{eCos}, @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS}, @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}, -@option{RIOT} +@option{RIOT}, @option{Zephyr} @xref{gdbrtossupport,,RTOS Support}. @item @code{-defer-examine} -- skip target examination at initial JTAG chain @@ -10950,6 +10950,7 @@ Currently supported rtos's include: @item @option{nuttx} @item @option{RIOT} @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.) +@item @option{Zephyr} @end itemize Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot @@ -10984,12 +10985,17 @@ g_readytorun, g_tasklisttable. sched_threads, sched_num_threads, sched_active_pid, max_threads, _tcb_name_offset. @end raggedright +@item Zephyr symbols +_kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size @end table For most RTOS supported the above symbols will be exported by default. However for -some, eg. FreeRTOS and uC/OS-III, extra steps must be taken. +some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken. -These RTOSes may require additional OpenOCD-specific file to be linked +Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols +with information needed in order to build the list of threads. + +FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked along with the project: @table @code diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am index de54596..49cb830 100644 --- a/src/rtos/Makefile.am +++ b/src/rtos/Makefile.am @@ -19,6 +19,7 @@ noinst_LTLIBRARIES += %D%/librtos.la %D%/uCOS-III.c \ %D%/nuttx.c \ %D%/hwthread.c \ + %D%/zephyr.c \ %D%/riot.c \ %D%/rtos.h \ %D%/rtos_standard_stackings.h \ diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index 91d9379..fdb3862 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -39,6 +39,7 @@ extern struct rtos_type uCOS_III_rtos; extern struct rtos_type nuttx_rtos; extern struct rtos_type hwthread_rtos; extern struct rtos_type riot_rtos; +extern struct rtos_type zephyr_rtos; static struct rtos_type *rtos_types[] = { &ThreadX_rtos, @@ -52,6 +53,7 @@ static struct rtos_type *rtos_types[] = { &uCOS_III_rtos, &nuttx_rtos, &riot_rtos, + &zephyr_rtos, /* keep this as last, as it always matches with rtos auto */ &hwthread_rtos, NULL diff --git a/src/rtos/zephyr.c b/src/rtos/zephyr.c new file mode 100644 index 0000000..e5d6835 --- /dev/null +++ b/src/rtos/zephyr.c @@ -0,0 +1,788 @@ +/*************************************************************************** + * Copyright (C) 2017 by Intel Corporation + * Leandro Pereira + * Daniel Glƶckner * + * Copyright (C) 2021 by Synopsys, Inc. + * Evgeniy Didin + * * + * SPDX-License-Identifier: GPL-2.0-or-later * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include + +#include "helper/log.h" +#include "helper/types.h" +#include "rtos.h" +#include "rtos_standard_stackings.h" +#include "target/target.h" +#include "target/target_type.h" +#include "target/armv7m.h" +#include "target/arc.h" + +#define UNIMPLEMENTED 0xFFFFFFFFU + +/* ARC specific defines */ +#define ARC_AUX_SEC_BUILD_REG 0xdb +#define ARC_REG_NUM 38 + +/* ARM specific defines */ +#define ARM_XPSR_OFFSET 28 + +struct zephyr_thread { + uint32_t ptr, next_ptr; + uint32_t entry; + uint32_t stack_pointer; + uint8_t state; + uint8_t user_options; + int8_t prio; + char name[64]; +}; + +enum zephyr_offsets { + OFFSET_VERSION, + OFFSET_K_CURR_THREAD, + OFFSET_K_THREADS, + OFFSET_T_ENTRY, + OFFSET_T_NEXT_THREAD, + OFFSET_T_STATE, + OFFSET_T_USER_OPTIONS, + OFFSET_T_PRIO, + OFFSET_T_STACK_POINTER, + OFFSET_T_NAME, + OFFSET_T_ARCH, + OFFSET_T_PREEMPT_FLOAT, + OFFSET_T_COOP_FLOAT, + OFFSET_MAX +}; + +struct zephyr_params { + const char *target_name; + uint8_t size_width; + uint8_t pointer_width; + uint32_t num_offsets; + uint32_t offsets[OFFSET_MAX]; + const struct rtos_register_stacking *callee_saved_stacking; + const struct rtos_register_stacking *cpu_saved_nofp_stacking; + const struct rtos_register_stacking *cpu_saved_fp_stacking; + int (*get_cpu_state)(struct rtos *rtos, target_addr_t *addr, + struct zephyr_params *params, + struct rtos_reg *callee_saved_reg_list, + struct rtos_reg **reg_list, int *num_regs); +}; + +static const struct stack_register_offset arm_callee_saved[] = { + { ARMV7M_R13, 32, 32 }, + { ARMV7M_R4, 0, 32 }, + { ARMV7M_R5, 4, 32 }, + { ARMV7M_R6, 8, 32 }, + { ARMV7M_R7, 12, 32 }, + { ARMV7M_R8, 16, 32 }, + { ARMV7M_R9, 20, 32 }, + { ARMV7M_R10, 24, 32 }, + { ARMV7M_R11, 28, 32 }, +}; + +static const struct stack_register_offset arc_callee_saved[] = { + { ARC_R13, 0, 32 }, + { ARC_R14, 4, 32 }, + { ARC_R15, 8, 32 }, + { ARC_R16, 12, 32 }, + { ARC_R17, 16, 32 }, + { ARC_R18, 20, 32 }, + { ARC_R19, 24, 32 }, + { ARC_R20, 28, 32 }, + { ARC_R21, 32, 32 }, + { ARC_R22, 36, 32 }, + { ARC_R23, 40, 32 }, + { ARC_R24, 44, 32 }, + { ARC_R25, 48, 32 }, + { ARC_GP, 52, 32 }, + { ARC_FP, 56, 32 }, + { ARC_R30, 60, 32 } +}; +static const struct rtos_register_stacking arm_callee_saved_stacking = { + .stack_registers_size = 36, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(arm_callee_saved), + .register_offsets = arm_callee_saved, +}; + +static const struct rtos_register_stacking arc_callee_saved_stacking = { + .stack_registers_size = 64, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(arc_callee_saved), + .register_offsets = arc_callee_saved, +}; + +static const struct stack_register_offset arm_cpu_saved[] = { + { ARMV7M_R0, 0, 32 }, + { ARMV7M_R1, 4, 32 }, + { ARMV7M_R2, 8, 32 }, + { ARMV7M_R3, 12, 32 }, + { ARMV7M_R4, -1, 32 }, + { ARMV7M_R5, -1, 32 }, + { ARMV7M_R6, -1, 32 }, + { ARMV7M_R7, -1, 32 }, + { ARMV7M_R8, -1, 32 }, + { ARMV7M_R9, -1, 32 }, + { ARMV7M_R10, -1, 32 }, + { ARMV7M_R11, -1, 32 }, + { ARMV7M_R12, 16, 32 }, + { ARMV7M_R13, -2, 32 }, + { ARMV7M_R14, 20, 32 }, + { ARMV7M_PC, 24, 32 }, + { ARMV7M_xPSR, 28, 32 }, +}; + +static struct stack_register_offset arc_cpu_saved[] = { + { ARC_R0, -1, 32 }, + { ARC_R1, -1, 32 }, + { ARC_R2, -1, 32 }, + { ARC_R3, -1, 32 }, + { ARC_R4, -1, 32 }, + { ARC_R5, -1, 32 }, + { ARC_R6, -1, 32 }, + { ARC_R7, -1, 32 }, + { ARC_R8, -1, 32 }, + { ARC_R9, -1, 32 }, + { ARC_R10, -1, 32 }, + { ARC_R11, -1, 32 }, + { ARC_R12, -1, 32 }, + { ARC_R13, -1, 32 }, + { ARC_R14, -1, 32 }, + { ARC_R15, -1, 32 }, + { ARC_R16, -1, 32 }, + { ARC_R17, -1, 32 }, + { ARC_R18, -1, 32 }, + { ARC_R19, -1, 32 }, + { ARC_R20, -1, 32 }, + { ARC_R21, -1, 32 }, + { ARC_R22, -1, 32 }, + { ARC_R23, -1, 32 }, + { ARC_R24, -1, 32 }, + { ARC_R25, -1, 32 }, + { ARC_GP, -1, 32 }, + { ARC_FP, -1, 32 }, + { ARC_SP, -1, 32 }, + { ARC_ILINK, -1, 32 }, + { ARC_R30, -1, 32 }, + { ARC_BLINK, 0, 32 }, + { ARC_LP_COUNT, -1, 32 }, + { ARC_PCL, -1, 32 }, + { ARC_PC, -1, 32 }, + { ARC_LP_START, -1, 32 }, + { ARC_LP_END, -1, 32 }, + { ARC_STATUS32, 4, 32 } +}; + + +enum zephyr_symbol_values { + ZEPHYR_VAL__KERNEL, + ZEPHYR_VAL__KERNEL_OPENOCD_OFFSETS, + ZEPHYR_VAL__KERNEL_OPENOCD_SIZE_T_SIZE, + ZEPHYR_VAL__KERNEL_OPENOCD_NUM_OFFSETS, + ZEPHYR_VAL_COUNT +}; + +static int64_t zephyr_cortex_m_stack_align(struct target *target, + const uint8_t *stack_data, + const struct rtos_register_stacking *stacking, int64_t stack_ptr) +{ + return rtos_Cortex_M_stack_align(target, stack_data, stacking, + stack_ptr, ARM_XPSR_OFFSET); +} + +static const struct rtos_register_stacking arm_cpu_saved_nofp_stacking = { + .stack_registers_size = 32, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(arm_cpu_saved), + .calculate_process_stack = zephyr_cortex_m_stack_align, + .register_offsets = arm_cpu_saved, +}; + +static const struct rtos_register_stacking arm_cpu_saved_fp_stacking = { + .stack_registers_size = 32 + 18 * 4, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(arm_cpu_saved), + .calculate_process_stack = zephyr_cortex_m_stack_align, + .register_offsets = arm_cpu_saved, +}; + +/* stack_registers_size is 8 because besides caller registers + * there are only blink and Status32 registers on stack left */ +static struct rtos_register_stacking arc_cpu_saved_stacking = { + .stack_registers_size = 8, + .stack_growth_direction = -1, + .num_output_registers = ARRAY_SIZE(arc_cpu_saved), + .register_offsets = arc_cpu_saved, +}; + +/* ARCv2 specific implementation */ +static int zephyr_get_arc_state(struct rtos *rtos, target_addr_t *addr, + struct zephyr_params *params, + struct rtos_reg *callee_saved_reg_list, + struct rtos_reg **reg_list, int *num_regs) +{ + + uint32_t real_stack_addr; + int retval = 0; + int num_callee_saved_regs; + const struct rtos_register_stacking *stacking; + + /* Getting real stack address from Kernel thread struct */ + retval = target_read_u32(rtos->target, *addr, &real_stack_addr); + if (retval != ERROR_OK) + return retval; + + /* Getting callee registers */ + retval = rtos_generic_stack_read(rtos->target, + params->callee_saved_stacking, + real_stack_addr, &callee_saved_reg_list, + &num_callee_saved_regs); + if (retval != ERROR_OK) + return retval; + + stacking = params->cpu_saved_nofp_stacking; + + /* Getting blink and status32 registers */ + retval = rtos_generic_stack_read(rtos->target, stacking, + real_stack_addr + num_callee_saved_regs * 4, + reg_list, num_regs); + if (retval != ERROR_OK) + return retval; + + for (int i = 0; i < num_callee_saved_regs; i++) + buf_cpy(callee_saved_reg_list[i].value, + (*reg_list)[callee_saved_reg_list[i].number].value, + callee_saved_reg_list[i].size); + + /* The blink, sp, pc offsets in arc_cpu_saved structure may be changed, + * but the registers number shall not. So the next code searches the + * offsetst of these registers in arc_cpu_saved structure. */ + unsigned short blink_offset = 0, pc_offset = 0, sp_offset = 0; + for (size_t i = 0; i < ARRAY_SIZE(arc_cpu_saved); i++) { + if (arc_cpu_saved[i].number == ARC_BLINK) + blink_offset = i; + if (arc_cpu_saved[i].number == ARC_SP) + sp_offset = i; + if (arc_cpu_saved[i].number == ARC_PC) + pc_offset = i; + } + + if (blink_offset == 0 || sp_offset == 0 || pc_offset == 0) { + LOG_ERROR("Basic registers offsets are missing, check struct"); + return ERROR_FAIL; + } + + /* Put blink value into PC */ + buf_cpy((*reg_list)[blink_offset].value, + (*reg_list)[pc_offset].value, sizeof((*reg_list)[blink_offset].value)); + + /* Put address after callee/caller in SP. */ + int64_t stack_top; + + stack_top = real_stack_addr + num_callee_saved_regs * 4 + + arc_cpu_saved_stacking.stack_registers_size; + buf_cpy(&stack_top, (*reg_list)[sp_offset].value, sizeof(stack_top)); + + return retval; +} + +/* ARM Cortex-M-specific implementation */ +static int zephyr_get_arm_state(struct rtos *rtos, target_addr_t *addr, + struct zephyr_params *params, + struct rtos_reg *callee_saved_reg_list, + struct rtos_reg **reg_list, int *num_regs) +{ + + int retval = 0; + int num_callee_saved_regs; + const struct rtos_register_stacking *stacking; + + retval = rtos_generic_stack_read(rtos->target, + params->callee_saved_stacking, + *addr, &callee_saved_reg_list, + &num_callee_saved_regs); + if (retval != ERROR_OK) + return retval; + + *addr = target_buffer_get_u32(rtos->target, + callee_saved_reg_list[0].value); + + if (params->offsets[OFFSET_T_PREEMPT_FLOAT] != UNIMPLEMENTED) + stacking = params->cpu_saved_fp_stacking; + else + stacking = params->cpu_saved_nofp_stacking; + + retval = rtos_generic_stack_read(rtos->target, stacking, *addr, reg_list, + num_regs); + if (retval != ERROR_OK) + return retval; + + for (int i = 1; i < num_callee_saved_regs; i++) + buf_cpy(callee_saved_reg_list[i].value, + (*reg_list)[callee_saved_reg_list[i].number].value, + callee_saved_reg_list[i].size); + return 0; +} + +static struct zephyr_params zephyr_params_list[] = { + { + .target_name = "cortex_m", + .pointer_width = 4, + .callee_saved_stacking = &arm_callee_saved_stacking, + .cpu_saved_nofp_stacking = &arm_cpu_saved_nofp_stacking, + .cpu_saved_fp_stacking = &arm_cpu_saved_fp_stacking, + .get_cpu_state = &zephyr_get_arm_state, + }, + { + .target_name = "hla_target", + .pointer_width = 4, + .callee_saved_stacking = &arm_callee_saved_stacking, + .cpu_saved_nofp_stacking = &arm_cpu_saved_nofp_stacking, + .cpu_saved_fp_stacking = &arm_cpu_saved_fp_stacking, + .get_cpu_state = &zephyr_get_arm_state, + + }, + { + .target_name = "arcv2", + .pointer_width = 4, + .callee_saved_stacking = &arc_callee_saved_stacking, + .cpu_saved_nofp_stacking = &arc_cpu_saved_stacking, + .get_cpu_state = &zephyr_get_arc_state, + }, + { + .target_name = NULL + } +}; + +static const struct symbol_table_elem zephyr_symbol_list[] = { + { + .symbol_name = "_kernel", + .optional = false + }, + { + .symbol_name = "_kernel_openocd_offsets", + .optional = false + }, + { + .symbol_name = "_kernel_openocd_size_t_size", + .optional = false + }, + { + .symbol_name = "_kernel_openocd_num_offsets", + .optional = true + }, + { + .symbol_name = NULL + } +}; + +static bool zephyr_detect_rtos(struct target *target) +{ + if (target->rtos->symbols == NULL) { + LOG_INFO("Zephyr: no symbols while detecting RTOS"); + return false; + } + + for (enum zephyr_symbol_values symbol = ZEPHYR_VAL__KERNEL; + symbol != ZEPHYR_VAL_COUNT; symbol++) { + LOG_INFO("Zephyr: does it have symbol %d (%s)?", symbol, + target->rtos->symbols[symbol].optional ? "optional" : "mandatory"); + + if (target->rtos->symbols[symbol].optional) + continue; + if (target->rtos->symbols[symbol].address == 0) + return false; + } + + LOG_INFO("Zephyr: all mandatory symbols found"); + + return true; +} + +static int zephyr_create(struct target *target) +{ + const char *name; + + name = target_type_name(target); + + LOG_INFO("Zephyr: looking for target: %s", name); + + /* ARC specific, check if EM target has security subsystem + * In case of ARC_HAS_SECURE zephyr option enabled + * the thread stack contains blink,sec_stat,status32 register + * values. If ARC_HAS_SECURE is disabled, only blink and status32 + * register values are saved on stack. */ + if (!strcmp(name, "arcv2")) { + uint32_t value; + struct arc_common *arc = target_to_arc(target); + /* Reading SEC_BUILD bcr */ + CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, ARC_AUX_SEC_BUILD_REG, &value)); + if (value != 0) { + LOG_DEBUG("ARC EM board has security subsystem, changing offsets"); + arc_cpu_saved[ARC_REG_NUM - 1].offset = 8; + /* After reading callee registers in stack + * now blink,sec_stat,status32 registers + * are located. */ + arc_cpu_saved_stacking.stack_registers_size = 12; + } + } + + for (struct zephyr_params *p = zephyr_params_list; p->target_name; p++) { + if (!strcmp(p->target_name, name)) { + LOG_INFO("Zephyr: target known, params at %p", p); + target->rtos->rtos_specific_params = p; + return ERROR_OK; + } + } + + LOG_ERROR("Could not find target in Zephyr compatibility list"); + return ERROR_FAIL; +} + +struct zephyr_array { + void *ptr; + size_t elements; +}; + +static void zephyr_array_init(struct zephyr_array *array) +{ + array->ptr = NULL; + array->elements = 0; +} + +static void zephyr_array_free(struct zephyr_array *array) +{ + free(array->ptr); + zephyr_array_init(array); +} + +static void *zephyr_array_append(struct zephyr_array *array, size_t size) +{ + if (!(array->elements % 16)) { + void *ptr = realloc(array->ptr, (array->elements + 16) * size); + + if (!ptr) { + LOG_ERROR("Out of memory"); + return NULL; + } + + array->ptr = ptr; + } + + return (unsigned char *)array->ptr + (array->elements++) * size; +} + +static void *zephyr_array_detach_ptr(struct zephyr_array *array) +{ + void *ptr = array->ptr; + + zephyr_array_init(array); + + return ptr; +} + +static uint32_t zephyr_kptr(const struct rtos *rtos, enum zephyr_offsets off) +{ + const struct zephyr_params *params = rtos->rtos_specific_params; + + return rtos->symbols[ZEPHYR_VAL__KERNEL].address + params->offsets[off]; +} + +static int zephyr_fetch_thread(const struct rtos *rtos, + struct zephyr_thread *thread, uint32_t ptr) +{ + const struct zephyr_params *param = rtos->rtos_specific_params; + int retval; + + thread->ptr = ptr; + + retval = target_read_u32(rtos->target, ptr + param->offsets[OFFSET_T_ENTRY], + &thread->entry); + if (retval != ERROR_OK) + return retval; + + retval = target_read_u32(rtos->target, + ptr + param->offsets[OFFSET_T_NEXT_THREAD], + &thread->next_ptr); + if (retval != ERROR_OK) + return retval; + + retval = target_read_u32(rtos->target, + ptr + param->offsets[OFFSET_T_STACK_POINTER], + &thread->stack_pointer); + if (retval != ERROR_OK) + return retval; + + retval = target_read_u8(rtos->target, ptr + param->offsets[OFFSET_T_STATE], + &thread->state); + if (retval != ERROR_OK) + return retval; + + retval = target_read_u8(rtos->target, + ptr + param->offsets[OFFSET_T_USER_OPTIONS], + &thread->user_options); + if (retval != ERROR_OK) + return retval; + + uint8_t prio; + retval = target_read_u8(rtos->target, + ptr + param->offsets[OFFSET_T_PRIO], &prio); + if (retval != ERROR_OK) + return retval; + thread->prio = prio; + + thread->name[0] = '\0'; + if (param->offsets[OFFSET_T_NAME] != UNIMPLEMENTED) { + retval = target_read_buffer(rtos->target, + ptr + param->offsets[OFFSET_T_NAME], + sizeof(thread->name) - 1, (uint8_t *)thread->name); + if (retval != ERROR_OK) + return retval; + + thread->name[sizeof(thread->name) - 1] = '\0'; + } + + LOG_DEBUG("Fetched thread%" PRIx32 ": {entry@0x%" PRIx32 + ", state=%" PRIu8 ", useropts=%" PRIu8 ", prio=%" PRId8 "}", + ptr, thread->entry, thread->state, thread->user_options, thread->prio); + + return ERROR_OK; +} + +static int zephyr_fetch_thread_list(struct rtos *rtos, uint32_t current_thread) +{ + struct zephyr_array thread_array; + struct zephyr_thread thread; + struct thread_detail *td; + int64_t curr_id = -1; + uint32_t curr; + int retval; + + retval = target_read_u32(rtos->target, zephyr_kptr(rtos, OFFSET_K_THREADS), + &curr); + if (retval != ERROR_OK) { + LOG_ERROR("Could not fetch current thread pointer"); + return retval; + } + + zephyr_array_init(&thread_array); + + for (; curr; curr = thread.next_ptr) { + retval = zephyr_fetch_thread(rtos, &thread, curr); + if (retval != ERROR_OK) + goto error; + + td = zephyr_array_append(&thread_array, sizeof(*td)); + if (!td) + goto error; + + td->threadid = thread.ptr; + td->exists = true; + + if (thread.name[0]) + td->thread_name_str = strdup(thread.name); + else + td->thread_name_str = alloc_printf("thr_%" PRIx32 "_%" PRIx32, + thread.entry, thread.ptr); + td->extra_info_str = alloc_printf("prio:%" PRId8 ",useropts:%" PRIu8, + thread.prio, thread.user_options); + if (!td->thread_name_str || !td->extra_info_str) + goto error; + + if (td->threadid == current_thread) + curr_id = (int64_t)thread_array.elements - 1; + } + + LOG_DEBUG("Got information for %zu threads", thread_array.elements); + + rtos_free_threadlist(rtos); + + rtos->thread_count = (int)thread_array.elements; + rtos->thread_details = zephyr_array_detach_ptr(&thread_array); + + rtos->current_threadid = curr_id; + rtos->current_thread = current_thread; + + return ERROR_OK; + +error: + td = thread_array.ptr; + for (size_t i = 0; i < thread_array.elements; i++) { + free(td[i].thread_name_str); + free(td[i].extra_info_str); + } + + zephyr_array_free(&thread_array); + + return ERROR_FAIL; +} + +static int zephyr_update_threads(struct rtos *rtos) +{ + struct zephyr_params *param; + int retval; + + if (!rtos->rtos_specific_params) + return ERROR_FAIL; + + param = (struct zephyr_params *)rtos->rtos_specific_params; + + if (!rtos->symbols) { + LOG_ERROR("No symbols for Zephyr"); + return ERROR_FAIL; + } + + if (rtos->symbols[ZEPHYR_VAL__KERNEL].address == 0) { + LOG_ERROR("Can't obtain kernel struct from Zephyr"); + return ERROR_FAIL; + } + + if (rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_OFFSETS].address == 0) { + LOG_ERROR("Please build Zephyr with CONFIG_OPENOCD option set"); + return ERROR_FAIL; + } + + retval = target_read_u8(rtos->target, + rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_SIZE_T_SIZE].address, + ¶m->size_width); + if (retval != ERROR_OK) { + LOG_ERROR("Couldn't determine size of size_t from host"); + return retval; + } + + if (param->size_width != 4) { + LOG_ERROR("Only size_t of 4 bytes are supported"); + return ERROR_FAIL; + } + + if (rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_NUM_OFFSETS].address) { + retval = target_read_u32(rtos->target, + rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_NUM_OFFSETS].address, + ¶m->num_offsets); + if (retval != ERROR_OK) { + LOG_ERROR("Couldn't not fetch number of offsets from Zephyr"); + return retval; + } + + if (param->num_offsets <= OFFSET_T_STACK_POINTER) { + LOG_ERROR("Number of offsets too small"); + return ERROR_FAIL; + } + } else { + retval = target_read_u32(rtos->target, + rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_OFFSETS].address, + ¶m->offsets[OFFSET_VERSION]); + if (retval != ERROR_OK) { + LOG_ERROR("Couldn't not fetch offsets from Zephyr"); + return retval; + } + + if (param->offsets[OFFSET_VERSION] > 1) { + LOG_ERROR("Unexpected OpenOCD support version %" PRIu32, + param->offsets[OFFSET_VERSION]); + return ERROR_FAIL; + } + switch (param->offsets[OFFSET_VERSION]) { + case 0: + param->num_offsets = OFFSET_T_STACK_POINTER + 1; + break; + case 1: + param->num_offsets = OFFSET_T_COOP_FLOAT + 1; + break; + } + } + /* We can fetch the whole array for version 0, as they're supposed + * to grow only */ + uint32_t address; + address = rtos->symbols[ZEPHYR_VAL__KERNEL_OPENOCD_OFFSETS].address; + for (size_t i = 0; i < OFFSET_MAX; i++, address += param->size_width) { + if (i >= param->num_offsets) { + param->offsets[i] = UNIMPLEMENTED; + continue; + } + + retval = target_read_u32(rtos->target, address, ¶m->offsets[i]); + if (retval != ERROR_OK) { + LOG_ERROR("Could not fetch offsets from Zephyr"); + return ERROR_FAIL; + } + } + + LOG_DEBUG("Zephyr OpenOCD support version %" PRId32, + param->offsets[OFFSET_VERSION]); + + uint32_t current_thread; + retval = target_read_u32(rtos->target, + zephyr_kptr(rtos, OFFSET_K_CURR_THREAD), ¤t_thread); + if (retval != ERROR_OK) { + LOG_ERROR("Could not obtain current thread ID"); + return retval; + } + + retval = zephyr_fetch_thread_list(rtos, current_thread); + if (retval != ERROR_OK) { + LOG_ERROR("Could not obtain thread list"); + return retval; + } + + return ERROR_OK; +} + +static int zephyr_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, + struct rtos_reg **reg_list, int *num_regs) +{ + struct zephyr_params *params; + struct rtos_reg *callee_saved_reg_list = NULL; + target_addr_t addr; + int retval; + + LOG_INFO("Getting thread %" PRId64 " reg list", thread_id); + + if (rtos == NULL) + return ERROR_FAIL; + + if (thread_id == 0) + return ERROR_FAIL; + + params = rtos->rtos_specific_params; + if (params == NULL) + return ERROR_FAIL; + + addr = thread_id + params->offsets[OFFSET_T_STACK_POINTER] + - params->callee_saved_stacking->register_offsets[0].offset; + + retval = params->get_cpu_state(rtos, &addr, params, callee_saved_reg_list, reg_list, num_regs); + + free(callee_saved_reg_list); + + return retval; +} + +static int zephyr_get_symbol_list_to_lookup(struct symbol_table_elem **symbol_list) +{ + *symbol_list = malloc(sizeof(zephyr_symbol_list)); + if (!*symbol_list) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + + memcpy(*symbol_list, zephyr_symbol_list, sizeof(zephyr_symbol_list)); + return ERROR_OK; +} + +struct rtos_type zephyr_rtos = { + .name = "Zephyr", + + .detect_rtos = zephyr_detect_rtos, + .create = zephyr_create, + .update_threads = zephyr_update_threads, + .get_thread_reg_list = zephyr_get_thread_reg_list, + .get_symbol_list_to_lookup = zephyr_get_symbol_list_to_lookup, +}; -- cgit v1.1 From d624da96a96287e6e4a192c3bfecd2d45d4c0a82 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Mon, 10 May 2021 10:46:20 +0100 Subject: target/armv7m.h: [style] replace tab with space between variable type and name Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6230 Reviewed-by: Marc Schink Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/armv7m.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 588470f..f3445e1 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -228,7 +228,7 @@ enum { #define ARMV7M_COMMON_MAGIC 0x2A452A45 struct armv7m_common { - struct arm arm; + struct arm arm; int common_magic; int exception_number; -- cgit v1.1 From b392ba466c98642f6e470dcbfdf0339c827fd06d Mon Sep 17 00:00:00 2001 From: Yasushi SHOJI Date: Thu, 13 May 2021 21:07:02 +0900 Subject: server: gdb_server: Add colon for target extended-remote Both GDB commands "target remote" and "target extended-remote" require to have ":" right before port number. e.g. (gdb) target extended-remote :3333 Add ":" to the warning message so that users can copy & past it. Change-Id: Id6d8ec1e4dfd3c12cb7f3b314064f2c35fa7ab55 Signed-off-by: Yasushi SHOJI Reviewed-on: http://openocd.zylin.com/6237 Reviewed-by: Tarek BOCHKATI Tested-by: jenkins Reviewed-by: Marc Schink Reviewed-by: Antonio Borneo --- src/server/gdb_server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index 002b587..00c04e3 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -3315,7 +3315,7 @@ static int gdb_input_inner(struct connection *connection) /* '?' is sent after the eventual '!' */ if (!warn_use_ext && !gdb_con->extended_protocol) { warn_use_ext = true; - LOG_WARNING("Prefer GDB command \"target extended-remote %s\" instead of \"target remote %s\"", + LOG_WARNING("Prefer GDB command \"target extended-remote :%s\" instead of \"target remote :%s\"", connection->service->port, connection->service->port); } break; -- cgit v1.1 From bbbfddc3efd4a93b0c9489c2537efbaa117bcfb0 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 13 May 2021 16:03:22 +0200 Subject: jimtcl: restrict memory leak workaround on Linux only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The workaround for jimtcl 0.80 in commit 36ae487ed04b ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80") issues a compile time error on macOS: ../src/helper/command.c:157:22: error: aliases are not supported on darwin __attribute__((weak, alias("workaround_createcommand"))); The OS is x86_64-apple-darwin19.6.0 and the compiler used is x86_64-apple-darwin13.4.0-clang. Restrict the workaround on Linux host only. The fix for 'expr' syntax change is already merged and the workaround will be dropped soon. Change-Id: I925109a9c57c05f8c95b70bc7d6604eb1172cd79 Signed-off-by: Antonio Borneo Reported-by: Adam Jeliński Fixes: 36ae487ed04b ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80") Fixes: https://sourceforge.net/p/openocd/tickets/304/ Reviewed-on: http://openocd.zylin.com/6241 Tested-by: jenkins --- src/helper/command.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/helper/command.c b/src/helper/command.c index 0c6e785..3a931b5 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -144,12 +144,13 @@ static void command_log_capture_finish(struct log_capture_state *state) * Use the internal jimtcl API Jim_CreateCommandObj, not exported by jim.h, * and override the bugged API through preprocessor's macro. * This workaround works only when jimtcl is compiled as OpenOCD submodule. + * It's broken on macOS, so it's currently restricted on Linux only. * If jimtcl is linked-in from a precompiled library, either static or dynamic, * the symbol Jim_CreateCommandObj is not exported and the build will use the * bugged API. * To be removed when OpenOCD will switch to jimtcl 0.81 */ -#if JIM_VERSION == 80 +#if JIM_VERSION == 80 && defined __linux__ static int workaround_createcommand(Jim_Interp *interp, const char *cmdName, Jim_CmdProc *cmdProc, void *privData, Jim_DelCmdProc *delProc); int Jim_CreateCommandObj(Jim_Interp *interp, Jim_Obj *cmdNameObj, @@ -168,7 +169,7 @@ static int workaround_createcommand(Jim_Interp *interp, const char *cmdName, return retval; } #define Jim_CreateCommand workaround_createcommand -#endif /* JIM_VERSION == 80 */ +#endif /* JIM_VERSION == 80 && defined __linux__*/ /* FIXME: end of workaround for memory leak in jimtcl 0.80 */ static int command_retval_set(Jim_Interp *interp, int retval) -- cgit v1.1 From d7558e2ed67000afc2fa344e3acf67899fc3cebf Mon Sep 17 00:00:00 2001 From: Tomas Vanek Date: Sun, 16 May 2021 10:05:02 +0200 Subject: target/armv7m: fix static analyzer warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Despite of assert(is_packed) clang static analyser complains on use of the uninitialized offset variable. Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings src/target/armv7m.c: In function ā€˜armv7m_read_core_regā€™: src/target/armv7m.c:337:54: error: ā€˜reg32_idā€™ may be used uninitialized in this function [-Werror=maybe-uninitialized] It happens because mingw32 defines assert() without the attribute "noreturn", whatever NDEBUG is defined or not. Replace assert(is_packed) by if (is_packed) conditional and call assert(false) in the else branch. Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019 Signed-off-by: Tomas Vanek Reviewed-on: http://openocd.zylin.com/6256 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tarek BOCHKATI Reviewed-by: Andrzej Sierżęga --- src/target/armv7m.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 2bcb8ab..11770b5 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -329,11 +329,17 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r, if (r->size <= 8) { /* any 8-bit or shorter register is packed */ - uint32_t offset = 0; /* silence false gcc warning */ + uint32_t offset; unsigned int reg32_id; bool is_packed = armv7m_map_reg_packing(num, ®32_id, &offset); - assert(is_packed); + if (!is_packed) { + /* We should not get here as all 8-bit or shorter registers + * are packed */ + assert(false); + /* assert() does nothing if NDEBUG is defined */ + return ERROR_FAIL; + } struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id]; /* Read 32-bit container register if not cached */ @@ -394,11 +400,17 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r, if (r->size <= 8) { /* any 8-bit or shorter register is packed */ - uint32_t offset = 0; /* silence false gcc warning */ + uint32_t offset; unsigned int reg32_id; bool is_packed = armv7m_map_reg_packing(num, ®32_id, &offset); - assert(is_packed); + if (!is_packed) { + /* We should not get here as all 8-bit or shorter registers + * are packed */ + assert(false); + /* assert() does nothing if NDEBUG is defined */ + return ERROR_FAIL; + } struct reg *r32 = &armv7m->arm.core_cache->reg_list[reg32_id]; if (!r32->valid) { -- cgit v1.1 From d3a859cc448441a0220287bfeecd0fab72cb31ca Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 01:43:44 +0200 Subject: cmsis_dap: fix build on macOS Compile fails with error: src/jtag/drivers/cmsis_dap.c:683:28: error: format specifies type 'unsigned char' but the argument has type 'int' [-Werror,-Wformat] " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~ Fix the format specifier. Change-Id: I0a5a1a35452d634019989d14d849501fb8a7e93a Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6255 Tested-by: jenkins Reviewed-by: Tomas Vanek --- src/jtag/drivers/cmsis_dap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index 26e576b..927b33b 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -679,8 +679,8 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, int timeout_ms) uint8_t *resp = dap->response; if (resp[0] != CMD_DAP_TFER) { - LOG_ERROR("CMSIS-DAP command mismatch. Expected 0x%" PRIx8 - " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]); + LOG_ERROR("CMSIS-DAP command mismatch. Expected 0x%x received 0x%" PRIx8, + CMD_DAP_TFER, resp[0]); queued_retval = ERROR_FAIL; goto skip; } -- cgit v1.1 From 3a85fd52b66360a7cc3fa7ee236f31ac4c46daeb Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Fri, 7 May 2021 14:40:14 +0100 Subject: cortex_m: do not perform soft_reset_halt on targets without VECTRESET Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6209 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Tomas Vanek --- src/target/cortex_m.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index e35cdbe..245490c 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -727,6 +727,11 @@ static int cortex_m_soft_reset_halt(struct target *target) * core, not the peripherals */ LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead."); + if (!cortex_m->vectreset_supported) { + LOG_ERROR("VECTRESET is not supported on this Cortex-M core"); + return ERROR_FAIL; + } + /* Set C_DEBUGEN */ retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS); if (retval != ERROR_OK) -- cgit v1.1 From 936cff887abf116427802c4f07096fca1f2b1d88 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Tue, 11 May 2021 09:22:01 +0100 Subject: cortex_m: fix VECTRESET detection for ARMv6-M cores VECTRESET check should be done after verifying if the core is an ARMv6-M core, and not before that. Fixes: 2dc9c1df81b6 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET") Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6232 Tested-by: jenkins Reviewed-by: Tomas Vanek Reviewed-by: Antonio Borneo --- src/target/cortex_m.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 245490c..9f9bc0d 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -2040,9 +2040,6 @@ int cortex_m_examine(struct target *target) } LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - /* VECTRESET is supported only on ARMv7-M cores */ - cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m; - if (core == 4) { target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR1, &mvfr1); @@ -2069,6 +2066,9 @@ int cortex_m_examine(struct target *target) armv7m->arm.is_armv6m = true; } + /* VECTRESET is supported only on ARMv7-M cores */ + cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m; + /* Check for FPU, otherwise mark FPU register as non-existent */ if (armv7m->fp_feature == FP_NONE) for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++) -- cgit v1.1 From 510df38407da25aa0fa7427d26b9253455885d9b Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Wed, 5 May 2021 12:27:11 +0200 Subject: target/arm_dpm: rename 'wp_pc' as 'wp_addr' The field 'wp_pc' was originally introduced in commit 55eeea7fceb6 ("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009 to contain the address of the instruction which triggered a watchpoint. Later on with commit 651b861d5d5f ("target/aarch64: Add watchpoint support") it has been reused in to hold directly the memory address that triggered a watchpoint. Rename 'wp_pc' as 'wp_addr' and change its doxygen description. While there, fix the format string to print the field. Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6204 Tested-by: jenkins Reviewed-by: Liming Sun --- src/target/aarch64.c | 6 +++--- src/target/arm11.c | 3 +-- src/target/arm_dpm.c | 2 +- src/target/arm_dpm.h | 8 ++++++-- src/target/armv7a.c | 3 +-- src/target/armv8.c | 3 +-- src/target/armv8_dpm.c | 2 +- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 4ba92c8..e6eb2ca 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1856,7 +1856,7 @@ int aarch64_hit_watchpoint(struct target *target, uint64_t exception_address; struct watchpoint *wp; - exception_address = armv8->dpm.wp_pc; + exception_address = armv8->dpm.wp_addr; if (exception_address == 0xFFFFFFFF) return ERROR_FAIL; @@ -1867,12 +1867,12 @@ int aarch64_hit_watchpoint(struct target *target, /* the EDWAR value needs to have 8 added to it so we add */ /* that check as well not sure if that is a core bug) */ /**********************************************************/ - for (exception_address = armv8->dpm.wp_pc; exception_address <= (armv8->dpm.wp_pc + 8); + for (exception_address = armv8->dpm.wp_addr; exception_address <= (armv8->dpm.wp_addr + 8); exception_address += 8) { for (wp = target->watchpoints; wp; wp = wp->next) { if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) { *hit_watchpoint = wp; - if (exception_address != armv8->dpm.wp_pc) + if (exception_address != armv8->dpm.wp_addr) LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8"); return ERROR_OK; } diff --git a/src/target/arm11.c b/src/target/arm11.c index 68d4e18..ff125d0 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -355,8 +355,7 @@ static int arm11_arch_state(struct target *target) /* REVISIT also display ARM11-specific MMU and cache status ... */ if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) arm11->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr); return retval; } diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 6bfe355..e172fad 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -1010,7 +1010,7 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) /* ?? */ break; } - dpm->wp_pc = addr; + dpm->wp_addr = addr; } /*----------------------------------------------------------------------*/ diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index 8270782..80587f5 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -137,8 +137,12 @@ struct arm_dpm { struct dpm_bp *dbp; struct dpm_wp *dwp; - /** Address of the instruction which triggered a watchpoint. */ - target_addr_t wp_pc; + /** + * Target dependent watchpoint address. + * Either the address of the instruction which triggered a watchpoint + * or the memory address whose access triggered a watchpoint. + */ + target_addr_t wp_addr; /** Recent value of DSCR. */ uint32_t dscr; diff --git a/src/target/armv7a.c b/src/target/armv7a.c index abca335..5c9f308 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -571,8 +571,7 @@ int armv7a_arch_state(struct target *target) if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) armv7a->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv7a->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/armv8.c b/src/target/armv8.c index 6bf3b11..e209e88 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1169,8 +1169,7 @@ int armv8_arch_state(struct target *target) armv8_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) armv8->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv8->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index e7d0f86..a7b4f1d 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1297,7 +1297,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr) LOG_DEBUG("Unknown core_state"); break; } - dpm->wp_pc = addr; + dpm->wp_addr = addr; } /* -- cgit v1.1 From 15dd48119a3564df2ceb5512fc2b62ca42f43614 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Wed, 5 May 2021 15:05:21 +0200 Subject: target/aarch64: fix watchpoint management The early documentation for armv8a report the debug register WFAR as containing the address of the instruction that triggered the watchpoint. More recent documentation report the register EDWAR as containing the data memory address that triggered the watchpoint. The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not correct as they point to the debug register EDWAR, so reading such register returns directly the data memory address that triggered the watchpoint. The code incorrectly passes this address value to the function armv8_dpm_report_wfar(); this function is supposed to adjust the PC value, decrementing it to remove the effects of the CPU pipeline. This pipeline offset, that has no meaning on the value in EDWAR, caused commit 651b861d5d5f ("target/aarch64: Add watchpoint support") to add back the offset while comparing the address with the watchpoint enabled. The upper 32 bits of EDWAR are not valid in aarch32 mode and have to be ignored. Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1. Remove the function armv8_dpm_report_wfar(). Remove the offset while searching the matching watchpoint. Ignore the upper 32 bits of EDWAR in aarch32 mode. Fix a comment and the LOG text. Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6205 Tested-by: jenkins Reviewed-by: Liming Sun --- src/target/aarch64.c | 49 +++++++++++++++++++------------------------------ src/target/armv8.c | 2 +- src/target/armv8.h | 4 ++-- src/target/armv8_dpm.c | 21 --------------------- src/target/armv8_dpm.h | 2 -- 5 files changed, 22 insertions(+), 56 deletions(-) diff --git a/src/target/aarch64.c b/src/target/aarch64.c index e6eb2ca..612924f 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -988,25 +988,26 @@ static int aarch64_debug_entry(struct target *target) /* Examine debug reason */ armv8_dpm_report_dscr(dpm, dscr); - /* save address of instruction that triggered the watchpoint? */ + /* save the memory address that triggered the watchpoint */ if (target->debug_reason == DBG_REASON_WATCHPOINT) { uint32_t tmp; - uint64_t wfar = 0; retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_WFAR1, - &tmp); + armv8->debug_base + CPUV8_DBG_EDWAR0, &tmp); if (retval != ERROR_OK) return retval; - wfar = tmp; - wfar = (wfar << 32); - retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_WFAR0, - &tmp); - if (retval != ERROR_OK) - return retval; - wfar |= tmp; - armv8_dpm_report_wfar(&armv8->dpm, wfar); + target_addr_t edwar = tmp; + + /* EDWAR[63:32] has unknown content in aarch32 state */ + if (core_state == ARM_STATE_AARCH64) { + retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_EDWAR1, &tmp); + if (retval != ERROR_OK) + return retval; + edwar |= ((target_addr_t)tmp) << 32; + } + + armv8->dpm.wp_addr = edwar; } retval = armv8_dpm_read_current_registers(&armv8->dpm); @@ -1853,7 +1854,7 @@ int aarch64_hit_watchpoint(struct target *target, struct armv8_common *armv8 = target_to_armv8(target); - uint64_t exception_address; + target_addr_t exception_address; struct watchpoint *wp; exception_address = armv8->dpm.wp_addr; @@ -1861,23 +1862,11 @@ int aarch64_hit_watchpoint(struct target *target, if (exception_address == 0xFFFFFFFF) return ERROR_FAIL; - /**********************************************************/ - /* see if a watchpoint address matches a value read from */ - /* the EDWAR register. Testing shows that on some ARM CPUs*/ - /* the EDWAR value needs to have 8 added to it so we add */ - /* that check as well not sure if that is a core bug) */ - /**********************************************************/ - for (exception_address = armv8->dpm.wp_addr; exception_address <= (armv8->dpm.wp_addr + 8); - exception_address += 8) { - for (wp = target->watchpoints; wp; wp = wp->next) { - if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) { - *hit_watchpoint = wp; - if (exception_address != armv8->dpm.wp_addr) - LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8"); - return ERROR_OK; - } + for (wp = target->watchpoints; wp; wp = wp->next) + if (exception_address >= wp->address && exception_address < (wp->address + wp->length)) { + *hit_watchpoint = wp; + return ERROR_OK; } - } return ERROR_FAIL; } diff --git a/src/target/armv8.c b/src/target/armv8.c index e209e88..0c5cf34 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1169,7 +1169,7 @@ int armv8_arch_state(struct target *target) armv8_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv8->dpm.wp_addr); + LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/armv8.h b/src/target/armv8.h index 978b2ad..f09f3ab 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -257,8 +257,8 @@ static inline bool is_armv8(struct armv8_common *armv8) #define CPUV8_DBG_EDESR 0x20 #define CPUV8_DBG_EDECR 0x24 -#define CPUV8_DBG_WFAR0 0x30 -#define CPUV8_DBG_WFAR1 0x34 +#define CPUV8_DBG_EDWAR0 0x30 +#define CPUV8_DBG_EDWAR1 0x34 #define CPUV8_DBG_DSCR 0x088 #define CPUV8_DBG_DRCR 0x090 #define CPUV8_DBG_ECCR 0x098 diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index a7b4f1d..6ef8c33 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1279,27 +1279,6 @@ static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp) return retval; } -void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr) -{ - switch (dpm->arm->core_state) { - case ARM_STATE_ARM: - case ARM_STATE_AARCH64: - addr -= 8; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - addr -= 4; - break; - case ARM_STATE_JAZELLE: - /* ?? */ - break; - default: - LOG_DEBUG("Unknown core_state"); - break; - } - dpm->wp_addr = addr; -} - /* * Handle exceptions taken in debug state. This happens mostly for memory * accesses that violated a MMU policy. Taking an exception while in debug diff --git a/src/target/armv8_dpm.h b/src/target/armv8_dpm.h index a6cade3..c30b04f 100644 --- a/src/target/armv8_dpm.h +++ b/src/target/armv8_dpm.h @@ -38,8 +38,6 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode); int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp); -void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t wfar); - /* DSCR bits; see ARMv7a arch spec section C10.3.1. * Not all v7 bits are valid in v6. */ -- cgit v1.1 From 2d16d62ddc7d6362433468f3f104ca4b38550b55 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Thu, 13 May 2021 17:44:14 +0100 Subject: flash/stm32l4x: add missing break statement this is not a bug fix, this for loop will issue only one match adding the break will save unnecessary more loops. Change-Id: Ic1484ea8cdea1b284eb570f9e3e7818e07daf5cd Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6248 Reviewed-by: Oleksij Rempel Tested-by: jenkins --- src/flash/nor/stm32l4x.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index 594bce0..7e1fe7c 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -1351,8 +1351,10 @@ static int stm32l4_probe(struct flash_bank *bank) device_id = stm32l4_info->idcode & 0xFFF; for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) { - if (device_id == stm32l4_parts[n].id) + if (device_id == stm32l4_parts[n].id) { stm32l4_info->part_info = &stm32l4_parts[n]; + break; + } } if (!stm32l4_info->part_info) { -- cgit v1.1 From a9c004d2c8bdfa1d1a7c98fd086bfeb2a5e23e61 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Wed, 24 Mar 2021 21:33:36 +0100 Subject: github/action: create a permanent 'latest' release this commit extends the existing snapshot action to create a release named 'latest' with the built binaries for windows. this 'latest' release will be updated after every push to github. Change-Id: I75a64c598169241743add3ac9aa7a0337fbab7f2 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6127 Tested-by: jenkins Reviewed-by: Antonio Borneo --- .github/workflows/snapshot.yml | 45 +++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/.github/workflows/snapshot.yml b/.github/workflows/snapshot.yml index 9e871de..45db72e 100644 --- a/.github/workflows/snapshot.yml +++ b/.github/workflows/snapshot.yml @@ -15,7 +15,8 @@ jobs: steps: - name: Install needed packages run: sudo apt-get install autotools-dev autoconf automake libtool pkg-config cmake texinfo texlive g++-mingw-w64-i686 - - uses: actions/checkout@v1 + - name: Checkout Code + uses: actions/checkout@v1 - run: ./bootstrap - name: Prepare libusb1 env: @@ -62,9 +63,14 @@ jobs: LIBFTDI_CONFIG: "-DCMAKE_TOOLCHAIN_FILE='${{ env.LIBFTDI_SRC }}/cmake/Toolchain-i686-w64-mingw32.cmake' -DBUILD_TESTS:BOOL=off -DFTDIPP:BOOL=off -DPYTHON_BINDINGS:BOOL=off -DEXAMPLES:BOOL=off -DDOCUMENTATION:BOOL=off -DFTDI_EEPROM:BOOL=off" CAPSTONE_CONFIG: "CAPSTONE_BUILD_CORE_ONLY=yes CAPSTONE_STATIC=yes CAPSTONE_SHARED=no" run: | - # set snapshot tag + # check if there is tag pointing at HEAD, otherwise take the HEAD SHA-1 as OPENOCD_TAG OPENOCD_TAG="`git tag --points-at HEAD`" [ -z $OPENOCD_TAG ] && OPENOCD_TAG="`git rev-parse --short HEAD`" + # check if there is tag pointing at HEAD, if so the release will have the same name as the tag, + # otherwise it will be named 'latest' + RELEASE_NAME="`git tag --points-at HEAD`" + [ -z $RELEASE_NAME ] && RELEASE_NAME="latest" + [[ $RELEASE_NAME = "latest" ]] && IS_PRE_RELEASE="true" || IS_PRE_RELEASE="false" # set env and call cross-build.sh export OPENOCD_TAG=$OPENOCD_TAG export OPENOCD_SRC=$PWD @@ -78,31 +84,26 @@ jobs: # prepare the artifact ARTIFACT="openocd-${OPENOCD_TAG}-${HOST}.tar.gz" tar -czf $ARTIFACT * - echo "ARTIFACT_NAME=$ARTIFACT" >> $GITHUB_ENV + echo "RELEASE_NAME=$RELEASE_NAME" >> $GITHUB_ENV + echo "IS_PRE_RELEASE=$IS_PRE_RELEASE" >> $GITHUB_ENV echo "ARTIFACT_PATH=$PWD/$ARTIFACT" >> $GITHUB_ENV - name: Publish OpenOCD packaged for windows - uses: actions/upload-artifact@v1 + uses: actions/upload-artifact@v2 with: - name: ${{ env.ARTIFACT_NAME }} path: ${{ env.ARTIFACT_PATH }} - - name: Create Release - id: create_release - if: startsWith(github.ref, 'refs/tags/') - uses: actions/create-release@v1.1.4 - env: - GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Delete 'latest' Release + uses: dev-drprasad/delete-tag-and-release@v0.2.0 with: - tag_name: ${{ github.ref }} - release_name: ${{ github.ref }} - draft: false - prerelease: false - - name: Release OpenOCD packaged for windows - if: startsWith(github.ref, 'refs/tags/') - uses: actions/upload-release-asset@v1 + delete_release: true + tag_name: ${{ env.RELEASE_NAME }} env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Create Release + uses: ncipollo/release-action@v1 with: - upload_url: ${{ steps.create_release.outputs.upload_url }} - asset_path: ${{ env.ARTIFACT_PATH }} - asset_name: ${{ env.ARTIFACT_NAME }} - asset_content_type: application/gzip + tag: ${{ env.RELEASE_NAME }} + commit: ${{ github.sha }} + draft: false + artifacts: ${{ env.ARTIFACT_PATH }} + prerelease: ${{ env.IS_PRE_RELEASE }} + token: ${{ secrets.GITHUB_TOKEN }} -- cgit v1.1 From f440af41ff1598ec3e86ddc2b3facd5b5b2cf113 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 3 May 2021 00:15:20 +0200 Subject: tcl/rp2040: remove empty line at end of file Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6221 Tested-by: jenkins --- tcl/board/pico-debug.cfg | 1 - tcl/target/rp2040-core0.cfg | 1 - 2 files changed, 2 deletions(-) diff --git a/tcl/board/pico-debug.cfg b/tcl/board/pico-debug.cfg index c2fe7d3..ba59f86 100644 --- a/tcl/board/pico-debug.cfg +++ b/tcl/board/pico-debug.cfg @@ -8,4 +8,3 @@ adapter speed 4000 set CHIPNAME rp2040 source [find target/rp2040-core0.cfg] - diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg index e427083..8c3533b 100644 --- a/tcl/target/rp2040-core0.cfg +++ b/tcl/target/rp2040-core0.cfg @@ -35,4 +35,3 @@ flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME # srst does not exist; use SYSRESETREQ to perform a soft reset cortex_m reset_config sysresetreq - -- cgit v1.1 From 2a1f3b2574ef8b046d29f7321f74e59cc0b40e8b Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 28 Jan 2021 12:27:53 +0100 Subject: tcl: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. While there, fix one indentation. Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6214 Tested-by: jenkins --- tcl/bitsbytes.tcl | 2 +- tcl/board/arm_evaluator7t.cfg | 2 +- tcl/board/at91sam9g20-ek.cfg | 2 +- tcl/board/digilent_atlys.cfg | 2 +- tcl/board/hitex_lpc2929.cfg | 2 +- tcl/board/mini2440.cfg | 2 +- tcl/board/uptech_2410.cfg | 2 +- tcl/interface/ftdi/swd-resistor-hack.cfg | 2 +- tcl/target/c100config.tcl | 6 +++--- tcl/target/c100helper.tcl | 8 ++++---- tcl/target/davinci.cfg | 2 +- tcl/target/lpc8nxx.cfg | 2 +- tcl/target/psoc4.cfg | 2 +- 13 files changed, 18 insertions(+), 18 deletions(-) diff --git a/tcl/bitsbytes.tcl b/tcl/bitsbytes.tcl index 01cc509..756c725 100644 --- a/tcl/bitsbytes.tcl +++ b/tcl/bitsbytes.tcl @@ -2,7 +2,7 @@ # Purpose - Create some $BIT variables # Create $K and $M variables # and some bit field extraction variables. -# Creat helper variables ... +# Create helper variables ... # BIT0.. BIT31 for { set x 0 } { $x < 32 } { set x [expr {$x + 1}]} { diff --git a/tcl/board/arm_evaluator7t.cfg b/tcl/board/arm_evaluator7t.cfg index 96d859c..ef4b782 100644 --- a/tcl/board/arm_evaluator7t.cfg +++ b/tcl/board/arm_evaluator7t.cfg @@ -5,5 +5,5 @@ source [find target/samsung_s3c4510.cfg] # # FIXME: # Add (A) sdram configuration -# Add (B) flash cfi programing configuration +# Add (B) flash cfi programming configuration # diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 59ee4d2..e1cbb91 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -153,7 +153,7 @@ proc at91sam9g20_reset_init { } { nand probe nandflash_cs3 - # The AT91SAM9G20-EK evaluation board has build-in serial data flash also. + # The AT91SAM9G20-EK evaluation board has built-in serial data flash also. # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference diff --git a/tcl/board/digilent_atlys.cfg b/tcl/board/digilent_atlys.cfg index f298e3d..3eb6219 100644 --- a/tcl/board/digilent_atlys.cfg +++ b/tcl/board/digilent_atlys.cfg @@ -5,7 +5,7 @@ # ID 1443:0007 Digilent Development board JTAG # # However, the ixo-usb-jtag project provides an alternative open firmware for -# the on board programmer. When using thie firmware the board will then +# the on board programmer. When using this firmware the board will then # enumerate as: # ID 16c0:06ad Van Ooijen Technische Informatica # (With SerialNumber == hw_nexys) diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg index 2fe1f3c..8268306 100644 --- a/tcl/board/hitex_lpc2929.cfg +++ b/tcl/board/hitex_lpc2929.cfg @@ -34,7 +34,7 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe $_TARGETNAME configure -event reset-init { # Flash - mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached + mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached # Use PLL mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 9dca5a3..3d01b38 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -38,7 +38,7 @@ # it's apt-get install libusb-dev. When I made my config I only included # --enable-jlink and --enable-usbdevs # -# I HAVE NOT Tested this throughly, so there could still be problems. +# I HAVE NOT Tested this thoroughly, so there could still be problems. # But it should get you way ahead of the game from where I started. # If you find problems (and fixes) please post them to # openocd-development@lists.berlios.de and join the developers and diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg index 227cf42..0a2c475 100644 --- a/tcl/board/uptech_2410.cfg +++ b/tcl/board/uptech_2410.cfg @@ -1,5 +1,5 @@ # Target Configuration for the Uptech 2410 board. -# This configuration hould also work on smdk2410, but I havn't tested it yet. +# This configuration should also work on smdk2410, but I haven't tested it yet. # Author: xionglingfeng@Gmail.com source [find target/samsung_s3c2410.cfg] diff --git a/tcl/interface/ftdi/swd-resistor-hack.cfg b/tcl/interface/ftdi/swd-resistor-hack.cfg index 04f3a73..26eb44c 100644 --- a/tcl/interface/ftdi/swd-resistor-hack.cfg +++ b/tcl/interface/ftdi/swd-resistor-hack.cfg @@ -5,7 +5,7 @@ # # You also need to have reliable GND connection between the target and # adapter. Vref of the adapter should be supplied with a voltage equal -# to the target's (preferrably connect it to Vcc). You can also +# to the target's (preferably connect it to Vcc). You can also # optionally connect nSRST. Leave everything else unconnected. # # FTDI Target diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index f252360..e937219 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -43,7 +43,7 @@ proc setupTelo {} { # setup GPIO used as control signals for C100 setupGPIO - # This will allow acces to lower 8MB or NOR + # This will allow access to lower 8MB or NOR lowGPIO5 # setup NOR size,timing,etc. setupNOR @@ -79,7 +79,7 @@ proc setupNOR {} { #mww $EX_CS0_TMG3_REG # set EBUS clock 165/5=33MHz mww $EX_CLOCK_DIV_REG 0x5 - # everthing else is OK with default + # everything else is OK with default } proc bootNOR {} { @@ -159,7 +159,7 @@ proc boardID {id} { proc ooma_board_detect {} { set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG] - # read the current value of the BOOTSRAP pins + # read the current value of the BOOTSTRAP pins set tmp [mrw $GPIO_BOOTSTRAP_REG] echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp] # extract the GPBP bits diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index 2199b7a..bdcfd8c 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -13,16 +13,16 @@ proc helpC100 {} { echo "10) showArmClk: will show current config registers for Arm Bus Clock" echo "11) setupArmClk: will setup Amba Bus Clock=450MHz" echo "12) ooma_board_detect: will show which version of Telo you have" - echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg" + echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured" echo "14) showDDR2: will show DDR2 config registers" echo "15) showWatchdog: will show current register config for watchdog" echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)" echo "17) bootNOR: will boot Telo from NOR" - echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured" + echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured" echo "19) putcUART0: will print a character on UART0" echo "20) putsUART0: will print a string on UART0" - echo "21) trainDDR2: will run DDR2 training program" - echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin" + echo "21) trainDDR2: will run DDR2 training program" + echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin" } source [find mem_helper.tcl] diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index d2ed592..5ca54ae 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -267,7 +267,7 @@ proc pll_v03_setup {pll_addr mult config} { if {$aln != 0} { # clear pllcmd.GO mww [expr {$pll_addr + 0x0138}] 0x00 - # write alingment flags + # write alignment flags mww [expr {$pll_addr + 0x0140}] $aln # write pllcmd.GO; poll pllstat.GO mww [expr {$pll_addr + 0x0138}] 0x01 diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg index 1bc77b2..4db78cb 100644 --- a/tcl/target/lpc8nxx.cfg +++ b/tcl/target/lpc8nxx.cfg @@ -56,7 +56,7 @@ proc set_sysclk_500khz {} { echo "Notice: sysclock set to 500kHz." } -# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash. +# Do not remap the ARM interrupt vectors to anything but the beginning of the flash. # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description # Bit Symbol Value Description # 0 map - interrupt vector remap. 0 after boot. diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg index d4ee79f..cffcbc7 100644 --- a/tcl/target/psoc4.cfg +++ b/tcl/target/psoc4.cfg @@ -60,7 +60,7 @@ adapter speed 1500 # # Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE # clear TEST_MODE flag during device reset so workaround is not possible. -# Use a KitProg adapter for theese devices or "reset halt" will not stop +# Use a KitProg adapter for these devices or "reset halt" will not stop # before executing user code. # # 3) SWD cannot be connected during system initialization after reset. -- cgit v1.1 From 583be907cf56162123cd1d4ecf6ceace09922211 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 28 Jan 2021 12:51:44 +0100 Subject: flash: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: Ia5f134c91beb483fd865df9e4877e0ec3e789478 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6215 Tested-by: jenkins --- src/flash/nand/core.h | 2 +- src/flash/nor/kinetis.c | 2 +- src/flash/nor/mrvlqspi.c | 2 +- src/flash/nor/msp432.h | 2 +- src/flash/nor/nrf5.c | 2 +- src/flash/nor/stmqspi.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/flash/nand/core.h b/src/flash/nand/core.h index 5bf9fb3..12fc2b7 100644 --- a/src/flash/nand/core.h +++ b/src/flash/nand/core.h @@ -100,7 +100,7 @@ struct nand_info { const char *name; }; -/* Option constants for bizarre disfunctionality and real features +/* Option constants for bizarre dysfunctionality and real features */ enum { /* Chip can not auto increment pages */ diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c index e6b452e..1fee6eb 100644 --- a/src/flash/nor/kinetis.c +++ b/src/flash/nor/kinetis.c @@ -2803,7 +2803,7 @@ static int kinetis_blank_check(struct flash_bank *bank) struct kinetis_chip *k_chip = k_bank->k_chip; int result; - /* suprisingly blank check does not work in VLPR and HSRUN modes */ + /* surprisingly blank check does not work in VLPR and HSRUN modes */ result = kinetis_check_run_mode(k_chip); if (result != ERROR_OK) return result; diff --git a/src/flash/nor/mrvlqspi.c b/src/flash/nor/mrvlqspi.c index 3f5ce2c..b98c49d 100644 --- a/src/flash/nor/mrvlqspi.c +++ b/src/flash/nor/mrvlqspi.c @@ -37,7 +37,7 @@ #define QSPI_W_EN (0x1) #define QSPI_SS_DISABLE (0x0) #define QSPI_SS_ENABLE (0x1) -#define WRITE_DISBALE (0x0) +#define WRITE_DISABLE (0x0) #define WRITE_ENABLE (0x1) #define QSPI_TIMEOUT (1000) diff --git a/src/flash/nor/msp432.h b/src/flash/nor/msp432.h index 663393b..af1d40c 100644 --- a/src/flash/nor/msp432.h +++ b/src/flash/nor/msp432.h @@ -43,7 +43,7 @@ #define P4_SECTOR_LENGTH 0x1000 #define P4_ALGO_ENTRY_ADDR 0x01000110 -/* MSP432E4 flash paramters */ +/* MSP432E4 flash parameters */ #define E4_FLASH_BASE FLASH_BASE #define E4_FLASH_SIZE 0x100000 #define E4_SECTOR_LENGTH 0x4000 diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c index 12bbac6..5e17a8c 100644 --- a/src/flash/nor/nrf5.c +++ b/src/flash/nor/nrf5.c @@ -1038,7 +1038,7 @@ static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer, * RM reads: Code running from code region 1 will not be able to write * to code region 0. * Unfortunately the flash loader running from RAM can write to both - * code regions whithout any hint the protection is violated. + * code regions without any hint the protection is violated. * * Update protection state and check if any flash sector to be written * is protected. */ diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c index 11aa438..a3555a4 100644 --- a/src/flash/nor/stmqspi.c +++ b/src/flash/nor/stmqspi.c @@ -175,7 +175,7 @@ struct stmqspi_flash_bank { bool octo; struct flash_device dev; uint32_t io_base; - uint32_t saved_cr; /* in particalar FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */ + uint32_t saved_cr; /* in particular FSEL, DFM bit mask in QUADSPI_CR *AND* OCTOSPI_CR */ uint32_t saved_ccr; /* different meaning for QUADSPI and OCTOSPI */ uint32_t saved_tcr; /* only for OCTOSPI */ uint32_t saved_ir; /* only for OCTOSPI */ -- cgit v1.1 From 8e337052b6b808d3b6b3833ef74f9089ab1b9fd1 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 28 Jan 2021 13:05:53 +0100 Subject: jtag: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I101c76a638805d77c1ff356cf0f027552389e5d3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6216 Tested-by: jenkins --- src/jtag/aice/aice_interface.c | 2 +- src/jtag/aice/aice_usb.c | 2 +- src/jtag/core.c | 4 ++-- src/jtag/drivers/cmsis_dap_usb_bulk.c | 2 +- src/jtag/drivers/jtag_dpi.c | 2 +- src/jtag/drivers/nulink_usb.c | 8 ++++---- src/jtag/drivers/usb_blaster/usb_blaster.c | 4 ++-- src/jtag/minidriver.h | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c index 160eb11..86e9d16 100644 --- a/src/jtag/aice/aice_interface.c +++ b/src/jtag/aice/aice_interface.c @@ -436,7 +436,7 @@ static const struct command_registration aice_subcommand_handlers[] = { .handler = &aice_handle_aice_desc_command, .mode = COMMAND_CONFIG, .help = "set the aice device description", - .usage = "[desciption string]", + .usage = "[description string]", }, { .name = "serial", diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c index 6c452a3..3a0e485 100644 --- a/src/jtag/aice/aice_usb.c +++ b/src/jtag/aice/aice_usb.c @@ -2627,7 +2627,7 @@ static int aice_usb_halt(uint32_t coreid) if (core_info[coreid].debug_under_dex_on) { if (core_info[coreid].dex_use_psw_on == false) { - /* under debug 'debug mode', force $psw to 'debug mode' bahavior */ + /* under debug 'debug mode', force $psw to 'debug mode' behavior */ /* !!!NOTICE!!! this is workaround for debug 'debug mode'. * it is only for debugging 'debug exception handler' purpose. * after openocd detaches from target, target behavior is diff --git a/src/jtag/core.c b/src/jtag/core.c index 147df28..2166374 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -490,7 +490,7 @@ void jtag_add_tlr(void) /** * If supported by the underlying adapter, this clocks a raw bit sequence - * onto TMS for switching betwen JTAG and SWD modes. + * onto TMS for switching between JTAG and SWD modes. * * DO NOT use this to bypass the integrity checks and logging provided * by the jtag_add_pathmove() and jtag_add_statemove() calls. @@ -1343,7 +1343,7 @@ static int jtag_validate_ircapture(void) int chain_pos = 0; int retval; - /* when autoprobing, accomodate huge IR lengths */ + /* when autoprobing, accommodate huge IR lengths */ for (tap = NULL, total_ir_length = 0; (tap = jtag_tap_next_enabled(tap)) != NULL; total_ir_length += tap->ir_length) { diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c index a588b1b..c42bab2 100644 --- a/src/jtag/drivers/cmsis_dap_usb_bulk.c +++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c @@ -262,7 +262,7 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p * - config asked explicitly for an interface number * - the device has only one interface * The later two cases should be honored only if we know - * we are on the rigt device */ + * we are on the right device */ bool intf_identified_reliably = cmsis_dap_in_interface_str || (device_identified_reliably && (cmsis_dap_usb_interface != -1 diff --git a/src/jtag/drivers/jtag_dpi.c b/src/jtag/drivers/jtag_dpi.c index 7cac200..f5a67dd 100644 --- a/src/jtag/drivers/jtag_dpi.c +++ b/src/jtag/drivers/jtag_dpi.c @@ -301,7 +301,7 @@ static int jtag_dpi_init(void) serv_addr.sin_addr.s_addr = inet_addr(server_address); if (serv_addr.sin_addr.s_addr == INADDR_NONE) { - LOG_ERROR("inet_addr error occured"); + LOG_ERROR("inet_addr error occurred"); return ERROR_FAIL; } diff --git a/src/jtag/drivers/nulink_usb.c b/src/jtag/drivers/nulink_usb.c index 48a5c79..3eea9de 100644 --- a/src/jtag/drivers/nulink_usb.c +++ b/src/jtag/drivers/nulink_usb.c @@ -844,11 +844,11 @@ static int nulink_usb_read_mem(void *handle, uint32_t addr, uint32_t size, /* the nulink only supports 8/32bit memory read/writes * honour 32bit, all others will be handled as 8bit access */ if (size == 4) { - /* When in jtag mode the nulink uses the auto-increment functinality. + /* When in jtag mode the nulink uses the auto-increment functionality. * However it expects us to pass the data correctly, this includes * alignment and any page boundaries. We already do this as part of the * adi_v5 implementation, but the nulink is a hla adapter and so this - * needs implementiong manually. + * needs implementing manually. * currently this only affects jtag mode, they do single * access in SWD mode - but this may change and so we do it for both modes */ @@ -909,11 +909,11 @@ static int nulink_usb_write_mem(void *handle, uint32_t addr, uint32_t size, /* the nulink only supports 8/32bit memory read/writes * honour 32bit, all others will be handled as 8bit access */ if (size == 4) { - /* When in jtag mode the nulink uses the auto-increment functinality. + /* When in jtag mode the nulink uses the auto-increment functionality. * However it expects us to pass the data correctly, this includes * alignment and any page boundaries. We already do this as part of the * adi_v5 implementation, but the nulink is a hla adapter and so this - * needs implementiong manually. + * needs implementing manually. * currently this only affects jtag mode, do single * access in SWD mode - but this may change and so we do it for both modes */ diff --git a/src/jtag/drivers/usb_blaster/usb_blaster.c b/src/jtag/drivers/usb_blaster/usb_blaster.c index c312468..aa7c240 100644 --- a/src/jtag/drivers/usb_blaster/usb_blaster.c +++ b/src/jtag/drivers/usb_blaster/usb_blaster.c @@ -561,8 +561,8 @@ static int ublast_read_byteshifted_tdos(uint8_t *buf, int nb_bytes) * - first bit is stored in byte0, bit0 (LSB) * - second bit is stored in byte0, bit 1 * ... - * - eight bit is sotred in byte0, bit 7 - * - ninth bit is sotred in byte1, bit 0 + * - eight bit is stored in byte0, bit 7 + * - ninth bit is stored in byte1, bit 0 * - etc ... * * Returns ERROR_OK if OK, ERROR_xxx if a read error occurred diff --git a/src/jtag/minidriver.h b/src/jtag/minidriver.h index c6fdfaf..0624c55 100644 --- a/src/jtag/minidriver.h +++ b/src/jtag/minidriver.h @@ -32,7 +32,7 @@ * interface functions, instead of the built-in asynchronous driver * module that is used by the standard JTAG interface drivers. * - * In addtion to the functions defined in the @c minidriver.h file, the + * In addition to the functions defined in the @c minidriver.h file, the * @c jtag_minidriver.h file must declare the following functions (or * define static inline versions of them): * - jtag_add_callback -- cgit v1.1 From f1bc46c78a8d0d76e48c83daf1b0f3d6895aa59e Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 28 Jan 2021 13:32:41 +0100 Subject: target: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I548581247db72e683249749d1b8725035530b06e Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6217 Tested-by: jenkins --- src/target/arc.c | 2 +- src/target/arc.h | 2 +- src/target/arm_adi_v5.c | 2 +- src/target/avr32_mem.c | 4 ++-- src/target/embeddedice.h | 2 +- src/target/target.c | 2 +- src/target/target_type.h | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/target/arc.c b/src/target/arc.c index 694ac6f..e11cd7d 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -1467,7 +1467,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num, if (control_tt != AP_AC_TT_DISABLE) { if (arc->actionpoints_num_avail < 1) { - LOG_ERROR("No free actionpoints, maximim amount is %u", + LOG_ERROR("No free actionpoints, maximum amount is %u", arc->actionpoints_num); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } diff --git a/src/target/arc.h b/src/target/arc.h index 8d44bfa..f0351bd 100644 --- a/src/target/arc.h +++ b/src/target/arc.h @@ -206,7 +206,7 @@ struct arc_common { bool dcache_invalidated; bool l2cache_invalidated; - /* Indicate if cach was built (for deinit function) */ + /* Indicate if cache was built (for deinit function) */ bool core_aux_cache_built; bool bcr_cache_built; /* Closely Coupled memory(CCM) regions for performance-critical diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 8f5ad59..6569fcc 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -32,7 +32,7 @@ * This file implements support for the ARM Debug Interface version 5 (ADIv5) * debugging architecture. Compared with previous versions, this includes * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message - * transport, and focusses on memory mapped resources as defined by the + * transport, and focuses on memory mapped resources as defined by the * CoreSight architecture. * * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two diff --git a/src/target/avr32_mem.c b/src/target/avr32_mem.c index 71ec0b4..8f38a18 100644 --- a/src/target/avr32_mem.c +++ b/src/target/avr32_mem.c @@ -176,7 +176,7 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, */ if (addr & 3) { /* - * mwa_read will read whole world, no nead to fiddle + * mwa_read will read whole world, no need to fiddle * with address. It will be truncated in set_addr */ retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, @@ -248,7 +248,7 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, */ if (addr & 3) { /* - * mwa_read will read whole world, no nead to fiddle + * mwa_read will read whole world, no need to fiddle * with address. It will be truncated in set_addr */ retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 4b5c816..4a62cef 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -106,7 +106,7 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout); -/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be +/* If many embeddedice_write_reg() follow each other, then the >1 invocations can be * this faster version of embeddedice_write_reg */ static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value) diff --git a/src/target/target.c b/src/target/target.c index e9d6770..d60e642 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -5173,7 +5173,7 @@ no_params: if (goi->isconfigure) { struct command_context *cmd_ctx = current_command_context(goi->interp); if (cmd_ctx->mode != COMMAND_CONFIG) { - Jim_SetResultString(goi->interp, "-gdb-max-conenctions must be configured before 'init'", -1); + Jim_SetResultString(goi->interp, "-gdb-max-connections must be configured before 'init'", -1); return JIM_ERR; } diff --git a/src/target/target_type.h b/src/target/target_type.h index 0f3df00..1948121 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -79,7 +79,7 @@ struct target_type { * state correctly. * * Otherwise the following would fail, as there will not - * be any "poll" invoked inbetween the "reset run" and + * be any "poll" invoked between the "reset run" and * "halt". * * reset run; halt -- cgit v1.1 From 3c4206936d541db512ed39ce5ff4d3a0ab9ef33c Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 28 Jan 2021 13:34:51 +0100 Subject: openocd: fix some minor typo Minor typos found by the new checkpatch boosted by the dictionary provided by 'codespell'. Change-Id: I7b4cae1798ff5ea048fcbc671a397af763fdc605 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6218 Tested-by: jenkins --- doc/manual/style.txt | 2 +- doc/openocd.texi | 6 +++--- src/helper/time_support.h | 2 +- src/rtos/mqx.c | 2 +- src/xsvf/xsvf.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/doc/manual/style.txt b/doc/manual/style.txt index 9108899..58f3980 100644 --- a/doc/manual/style.txt +++ b/doc/manual/style.txt @@ -406,7 +406,7 @@ For technical reference material: vice versa. - Alphabetize the \@defn declarations for all commands in each section. -- Keep the per-command documentation focussed on exactly what that +- Keep the per-command documentation focused on exactly what that command does, not motivation, advice, suggestions, or big examples. When commands deserve such expanded text, it belongs elsewhere. Solutions might be using a \@section explaining a cluster of related diff --git a/doc/openocd.texi b/doc/openocd.texi index fc44833..4ca7be8 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -315,7 +315,7 @@ There are several things you should keep in mind when choosing a dongle. @enumerate @item @b{Transport} Does it support the kind of communication that you need? -OpenOCD focusses mostly on JTAG. Your version may also support +OpenOCD focuses mostly on JTAG. Your version may also support other ways to communicate with target devices. @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V? Does your dongle support it? You might need a level converter. @@ -5577,7 +5577,7 @@ flash driver infers all parameters from current controller register values when 'flash probe @var{bank_id}' is executed. Normal OpenOCD commands like @command{mdw} can be used to display the flash content, -but only after proper controller initialization as decribed above. However, +but only after proper controller initialization as described above. However, due to a silicon bug in some devices, attempting to access the very last word should be avoided. @@ -11392,7 +11392,7 @@ your C code, do the same - artificially push some zeros onto the stack, remember to pop them off when the ISR is done. @b{Also note:} If you have a multi-threaded operating system, they -often do not @b{in the intrest of saving memory} waste these few +often do not @b{in the interest of saving memory} waste these few bytes. Painful... diff --git a/src/helper/time_support.h b/src/helper/time_support.h index 3c7d425..b83c0ac 100644 --- a/src/helper/time_support.h +++ b/src/helper/time_support.h @@ -46,7 +46,7 @@ struct duration { /** Update the duration->start field to start the @a duration measurement. */ int duration_start(struct duration *duration); -/** Update the duration->elapsed field to finish the @a duration measurment. */ +/** Update the duration->elapsed field to finish the @a duration measurement. */ int duration_measure(struct duration *duration); /** @returns Elapsed time in seconds. */ diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 0914e31..22cd721 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -222,7 +222,7 @@ static int mqx_is_scheduler_running( return ERROR_FAIL; } /* check first member, the '_mqx_kernel_data->ADDRESSING_CAPABILITY'. - it supose to be set to value 8 */ + it suppose to be set to value 8 */ if (capability_value != 8) { LOG_WARNING("MQX RTOS - value of '_mqx_kernel_data->ADDRESSING_CAPABILITY' contains invalid value"); return ERROR_FAIL; diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c index 2a7b56d..8237849 100644 --- a/src/xsvf/xsvf.c +++ b/src/xsvf/xsvf.c @@ -1057,7 +1057,7 @@ int xsvf_register_commands(struct command_context *cmd_ctx) /* -PSUEDO-Code from Xilinx Appnote XAPP067.pdf : +PSEUDO-Code from Xilinx Appnote XAPP067.pdf : the following pseudo code clarifies the intent of the xrepeat support.The flow given is for the entire processing of an SVF file, not an XSVF file. -- cgit v1.1 From 1f54a0860fb23f3a63a661ac6eeb68e3081ff1b7 Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Mon, 10 May 2021 18:10:30 +0200 Subject: Document the buspirate interface driver. Change-Id: Iaff13fc5187041a840f4f00eb6b4ee52880cf47e Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6231 Tested-by: jenkins Reviewed-by: Antonio Borneo --- doc/openocd.texi | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/doc/openocd.texi b/doc/openocd.texi index 4ca7be8..361ceb4 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -3264,6 +3264,68 @@ Specifies the TCP/IP address of the SystemVerilog DPI server interface. @end deffn +@deffn {Interface Driver} {buspirate} + +This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices. +It uses a simple data protocol over a serial port connection. + +Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver +allows you to start building your own JTAG adapter without the complexity of a custom USB connection. + +@deffn {Config Command} {buspirate_port} serial_port +Specify the serial port's filename. For example: +@example +buspirate_port /dev/ttyUSB0 +@end example +@end deffn + +@deffn {Config Command} {buspirate_speed} (normal|fast) +Set the communication speed to 115k (normal) or 1M (fast). For example: +@example +buspirate_mode normal +@end example +@end deffn + +@deffn {Config Command} {buspirate_mode} (normal|open-drain) +Set the Bus Pirate output mode. +@itemize @minus +@item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF. +@item In open drain mode, you will then need to enable the pull-ups. +@end itemize +For example: +@example +buspirate_mode normal +@end example +@end deffn + +@deffn {Config Command} {buspirate_pullup} (0|1) +Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF) +to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS). +For example: +@example +buspirate_pullup 0 +@end example +@end deffn + +@deffn {Config Command} {buspirate_vreg} (0|1) +Whether to enable (1) or disable (0) the built-in voltage regulator, +which can be used to supply power to a test circuit through +I/O header pins +3V3 and +5V. For example: +@example +buspirate_vreg 0 +@end example +@end deffn + +@deffn {Command} {buspirate_led} (0|1) +Turns the Bus Pirate's LED on (1) or off (0). For example: +@end deffn +@example +buspirate_led 1 +@end example + +@end deffn + + @section Transport Configuration @cindex Transport As noted earlier, depending on the version of OpenOCD you use, -- cgit v1.1 From 229c4c6a71ce6540917cbc10629d8f51c98c7e7b Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Thu, 13 May 2021 14:19:13 +0200 Subject: Warn on undefined preprocessor symbols Preprocessor directives like "#if SYMBOL" silently replace undefined or misspelt symbols with 0, which makes configuration bugs hard to spot. Compiler flag "-Wundef" prevents such errors. Change-Id: I91b7ba2db02ef0c3c452d334601c53aebda4660e Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6238 Tested-by: jenkins Reviewed-by: Antonio Borneo --- configure.ac | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configure.ac b/configure.ac index e343875..139598e 100644 --- a/configure.ac +++ b/configure.ac @@ -637,6 +637,7 @@ m4_define([PROCESS_ADAPTERS], [ AC_MSG_ERROR([$3 is required for the ADAPTER_DESC([adapter])]) ]) ADAPTER_VAR([adapter])=no + AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).) ]) AM_CONDITIONAL(ADAPTER_SYM([adapter]), [test "x$ADAPTER_VAR([adapter])" != "xno"]) ]) @@ -756,6 +757,7 @@ AS_IF([test "x${gcc_wextra}" = "xyes"], [ GCC_WARNINGS="${GCC_WARNINGS} -Wcast-align" GCC_WARNINGS="${GCC_WARNINGS} -Wredundant-decls" GCC_WARNINGS="${GCC_WARNINGS} -Wpointer-arith" + GCC_WARNINGS="${GCC_WARNINGS} -Wundef" ]) AS_IF([test "x${gcc_werror}" = "xyes"], [ GCC_WARNINGS="${GCC_WARNINGS} -Werror" -- cgit v1.1 From 6e92cd0642ce19ce36cfd8bfe3faf5afc696f37e Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Thu, 13 May 2021 14:47:44 +0200 Subject: Remove compatibility macros m4_ifblank and m4_ifnblank They are at least since Autoconf 2.67 present, and we are requiring version 2.69. Change-Id: I41b33d4ebe02198f03cdddcc4a3c1beedd993d78 Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6239 Tested-by: jenkins Reviewed-by: Antonio Borneo --- config_subdir.m4 | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/config_subdir.m4 b/config_subdir.m4 index 1c79098..45a1c6c 100644 --- a/config_subdir.m4 +++ b/config_subdir.m4 @@ -1,17 +1,3 @@ -dnl -dnl If needed, define the m4_ifblank and m4_ifnblank macros from autoconf 2.64 -dnl This allows us to run with earlier Autoconfs as well. -ifdef([m4_ifblank],[],[ -m4_define([m4_ifblank], -[m4_if(m4_translit([[$1]], [ ][ ][ -]), [], [$2], [$3])])]) -dnl -ifdef([m4_ifnblank],[],[ -m4_define([m4_ifnblank], -[m4_if(m4_translit([[$1]], [ ][ ][ -]), [], [$3], [$2])])]) -dnl - dnl AC_CONFIG_SUBDIRS does not allow configure options to be passed dnl to subdirs, this function allows that by creating a configure.gnu dnl script that prepends configure options and then calls the real -- cgit v1.1 From 909d45e35c4d189a0424744a9ecf65227811b019 Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Thu, 13 May 2021 13:43:09 +0200 Subject: configure.ac: use a separate folder for Autoconf-generated files Autoconf generates several files in root folder of the project. Keep the root folder cleaner by specifying subfolder 'build-aux'. Align .gitignore accordingly. Signed-off-by: R. Diez Change-Id: Ied87faba495d9eeb8f98e78c2e2b7e7e596febfb Reviewed-on: http://openocd.zylin.com/6236 Tested-by: jenkins Reviewed-by: Antonio Borneo --- .gitignore | 12 ++++-------- configure.ac | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index f1021b2..e25d1ba 100644 --- a/.gitignore +++ b/.gitignore @@ -53,27 +53,23 @@ doc/openocd.toc doc/openocd.tp doc/openocd.vr doc/version.texi -texinfo.tex src/openocd src/openocd.exe # configure/autotools output +/build-aux/ aclocal.m4 autom4te.cache -compile -config.* +config.h +config.log +config.status configure -depcomp doxygen doxygen.log Doxyfile -install-sh libtool -ltmain.sh Makefile !contrib/loaders/**/Makefile -mdate-sh -missing stamp-h1 stamp-vti INSTALL diff --git a/configure.ac b/configure.ac index 139598e..2a455fa 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ AC_PREREQ([2.69]) AC_INIT([openocd], [0.11.0+dev], [OpenOCD Mailing List ]) AC_CONFIG_SRCDIR([src/openocd.c]) -AC_CONFIG_AUX_DIR([.]) +AC_CONFIG_AUX_DIR([build-aux]) m4_include([config_subdir.m4])dnl -- cgit v1.1 From 0c5ca348ec70663f89a9a4e3b2d96d75787d431f Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 8 May 2021 11:02:12 +0200 Subject: helper/command: silent debug msg on command register/unregister Commit e216186fab59 ("helper/command: register full-name commands in jim") and commit a7d68878e4ba ("helper/command: unregister commands through their full-name") introduce a LOG_DEBUG() message each for command registration and unregistration. The messages above are quite noisy and pollute the log when debug_level is 3 or higher. They can be useful to debug the command registration logic, but for the other debug activities on OpenOCD are just noisy. Already commit a03ac1ba3087 ("helper/command: disable logging of registered commands [RFC]") was merged to silent the first case that is now back with additional logs. Silent both log messages. Use 'if (false)' to silent them, making easy to re-enable it when or if someone needs it. Change-Id: Id8a067e60e822d4ecbddcb036d081298f7e6181f Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6220 Tested-by: jenkins --- src/helper/command.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/helper/command.c b/src/helper/command.c index 3a931b5..c3d2e95 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -343,7 +343,8 @@ static struct command *register_command(struct command_context *context, return NULL; } - LOG_DEBUG("registering '%s'...", full_name); + if (false) /* too noisy with debug_level 3 */ + LOG_DEBUG("registering '%s'...", full_name); int retval = Jim_CreateCommand(context->interp, full_name, jim_command_dispatch, c, command_free); if (retval != JIM_OK) { @@ -441,7 +442,8 @@ int unregister_commands_match(struct command_context *cmd_ctx, const char *forma Jim_DecrRefCount(interp, elem); continue; } - LOG_DEBUG("delete command \"%s\"", name); + if (false) /* too noisy with debug_level 3 */ + LOG_DEBUG("delete command \"%s\"", name); #if JIM_VERSION >= 80 Jim_DeleteCommand(interp, elem); #else -- cgit v1.1 From 2fe2cafe2028c9c3c6faf82b0a545d33f6344ace Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Wed, 6 Jan 2021 18:01:00 +0100 Subject: mem_ap: fix target arch_info type The target mem_ap appears as an ARM target, thus it allows the execution of ARM specific commands causing the crash of OpenOCD. E.g. 'arm mrc ...' can be executed and segfaults. Replace the incorrect ARM magic number with a dedicated one. While there, remove the 'struct arm', that is now holding only the mem_ap's dap, and replace it with a pointer to the dap. Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6213 Tested-by: jenkins --- src/target/mem_ap.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c index 89c0c02..0c3d7f7 100644 --- a/src/target/mem_ap.c +++ b/src/target/mem_ap.c @@ -18,14 +18,16 @@ #include "target.h" #include "target_type.h" -#include "arm.h" #include "arm_adi_v5.h" #include "register.h" #include +#define MEM_AP_COMMON_MAGIC 0x4DE4DA50 + struct mem_ap { - struct arm arm; + int common_magic; + struct adiv5_dap *dap; struct adiv5_ap *ap; int ap_num; }; @@ -51,8 +53,8 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp) } mem_ap->ap_num = pc->ap_num; - mem_ap->arm.common_magic = ARM_COMMON_MAGIC; - mem_ap->arm.dap = pc->dap; + mem_ap->common_magic = MEM_AP_COMMON_MAGIC; + mem_ap->dap = pc->dap; target->arch_info = mem_ap; @@ -137,7 +139,7 @@ static int mem_ap_examine(struct target *target) struct mem_ap *mem_ap = target->arch_info; if (!target_was_examined(target)) { - mem_ap->ap = dap_ap(mem_ap->arm.dap, mem_ap->ap_num); + mem_ap->ap = dap_ap(mem_ap->dap, mem_ap->ap_num); target_set_examined(target); target->state = TARGET_UNKNOWN; target->debug_reason = DBG_REASON_UNDEFINED; -- cgit v1.1 From 8d207b5d2e034c94b7a989fcb20e90d496aa8c3b Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 11:58:31 +0200 Subject: riscv: drop unused variable The array newly_halted[] is assigned but its value is never used. Drop it! Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6257 Tested-by: jenkins Reviewed-by: Xiang W Reviewed-by: Tim Newsome --- src/target/riscv/riscv.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 1e93ded..7b7b728 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2040,7 +2040,6 @@ int riscv_openocd_poll(struct target *target) } else if (target->smp) { unsigned halts_discovered = 0; unsigned total_targets = 0; - bool newly_halted[RISCV_MAX_HARTS] = {0}; unsigned should_remain_halted = 0; unsigned should_resume = 0; unsigned i = 0; @@ -2049,7 +2048,6 @@ int riscv_openocd_poll(struct target *target) total_targets++; struct target *t = list->target; riscv_info_t *r = riscv_info(t); - assert(i < DIM(newly_halted)); enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid); switch (out) { case RPH_NO_CHANGE: @@ -2060,7 +2058,6 @@ int riscv_openocd_poll(struct target *target) break; case RPH_DISCOVERED_HALTED: halts_discovered++; - newly_halted[i] = true; t->state = TARGET_HALTED; enum riscv_halt_reason halt_reason = riscv_halt_reason(t, r->current_hartid); -- cgit v1.1 From 036de3b48217e9c0b5ec0bbf6638e9cad6cae517 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 14:02:53 +0200 Subject: riscv: replace macro DIM() with ARRAY_SIZE() OpenOCD already defines the macro ARRAY_SIZE, while riscv code uses a local macro DIM. Prefer using the macro ARRAY_SIZE() instead of DIM(). Not all the riscv code has been upstreamed, yes; this patch only covers the code already upstreamed. Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6258 Reviewed-by: Xiang W Tested-by: jenkins Reviewed-by: Tim Newsome --- src/target/riscv/riscv-011.c | 4 +--- src/target/riscv/riscv-013.c | 4 +--- src/target/riscv/riscv.c | 16 +++++++--------- 3 files changed, 9 insertions(+), 15 deletions(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 9b5f749..7a5e990 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -70,8 +70,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -1634,7 +1632,7 @@ static riscv_error_t handle_halt_routine(struct target *target) /* Read S0 from dscratch */ unsigned int csr[] = {CSR_DSCRATCH0, CSR_DPC, CSR_DCSR}; - for (unsigned int i = 0; i < DIM(csr); i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(csr); i++) { scans_add_write32(scans, 0, csrr(S0, csr[i]), true); scans_add_read(scans, SLOT0, false); } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 32a7f02..b70c259 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -86,8 +86,6 @@ static int riscv013_test_compliance(struct target *target); #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - #define CSR_DCSR_CAUSE_SWBP 1 #define CSR_DCSR_CAUSE_TRIGGER 2 #define CSR_DCSR_CAUSE_DEBUGINT 3 @@ -358,7 +356,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) }; text[0] = 0; - for (unsigned i = 0; i < DIM(description); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(description); i++) { if (description[i].address == address) { uint64_t mask = description[i].mask; unsigned value = get_field(data, mask); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 7b7b728..fa07fe8 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -23,8 +23,6 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) -#define DIM(x) (sizeof(x)/sizeof(*x)) - /* Constants for legacy SiFive hardware breakpoints. */ #define CSR_BPCONTROL_X (1<<0) #define CSR_BPCONTROL_W (1<<1) @@ -184,10 +182,10 @@ struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = { } }; struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi; -uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = DIM(_bscan_tunnel_nested_tap_select_dmi); +uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi); struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi; -uint32_t bscan_tunnel_data_register_select_dmi_num_fields = DIM(_bscan_tunnel_data_register_select_dmi); +uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi); struct trigger { uint64_t address; @@ -348,8 +346,8 @@ uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out) tunneled_dr[0].in_value = NULL; } jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_ir), tunneled_ir, TAP_IDLE); - jtag_add_dr_scan(target->tap, DIM(tunneled_dr), tunneled_dr, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE); + jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE); select_dmi_via_bscan(target); int retval = jtag_execute_queue(); @@ -1788,7 +1786,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params, GDB_REGNO_PC, GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE, }; - for (unsigned i = 0; i < DIM(regnums); i++) { + for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) { enum gdb_regno regno = regnums[i]; riscv_reg_t reg_value; if (riscv_get_register(target, ®_value, regno) != ERROR_OK) @@ -3768,7 +3766,7 @@ int riscv_init_registers(struct target *target) #undef DECLARE_CSR }; /* encoding.h does not contain the registers in sorted order. */ - qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info); + qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info); unsigned csr_info_index = 0; unsigned custom_range_index = 0; @@ -4028,7 +4026,7 @@ int riscv_init_registers(struct target *target) unsigned csr_number = number - GDB_REGNO_CSR0; while (csr_info[csr_info_index].number < csr_number && - csr_info_index < DIM(csr_info) - 1) { + csr_info_index < ARRAY_SIZE(csr_info) - 1) { csr_info_index++; } if (csr_info[csr_info_index].number == csr_number) { -- cgit v1.1 From 4e872a797f81595d5de790138bdec62f2bf175f0 Mon Sep 17 00:00:00 2001 From: Olivier DANET Date: Mon, 17 May 2021 14:47:14 +0200 Subject: target/zynqmp : Add AXI AP access port The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs. Change-Id: I6303331c217795657575de4759444938e775dee1 Signed-off-by: Olivier DANET Reviewed-on: http://openocd.zylin.com/6263 Reviewed-by: Tarek BOCHKATI Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/xilinx_zynqmp.cfg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index b21603f..e66289a 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -92,6 +92,8 @@ for { set _core 0 } { $_core < $_cores } { incr _core } { eval $_command } +target create uscale.axi mem_ap -dap uscale.dap -ap-num 0 + eval $_smp_command targets $_TARGETNAME.0 -- cgit v1.1 From 8f6dd512c7753ce1252283b208bb8f8880f93f37 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 24 Aug 2020 11:40:13 +0200 Subject: drivers/versaloon: use ARRAY_SIZE() Replace the custom macro dimof() with the OpenOCD macro ARRAY_SIZE(). Change-Id: I2fe638444f6c16f2a78c1fd558b21550f76282d6 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6259 Tested-by: jenkins Reviewed-by: Xiang W --- src/jtag/drivers/versaloon/versaloon.c | 2 +- src/jtag/drivers/versaloon/versaloon_include.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c index 6fea888..e564d8b 100644 --- a/src/jtag/drivers/versaloon/versaloon.c +++ b/src/jtag/drivers/versaloon/versaloon.c @@ -124,7 +124,7 @@ void versaloon_free_want_pos(void) } versaloon_want_pos = NULL; - for (i = 0; i < dimof(versaloon_pending); i++) { + for (i = 0; i < ARRAY_SIZE(versaloon_pending); i++) { tmp = versaloon_pending[i].pos; while (tmp != NULL) { free_tmp = tmp; diff --git a/src/jtag/drivers/versaloon/versaloon_include.h b/src/jtag/drivers/versaloon/versaloon_include.h index 4ca81d5..a954b48 100644 --- a/src/jtag/drivers/versaloon/versaloon_include.h +++ b/src/jtag/drivers/versaloon/versaloon_include.h @@ -27,7 +27,6 @@ #define PARAM_CHECK 1 #define sleep_ms(ms) jtag_sleep((ms) * 1000) -#define dimof(arr) (sizeof(arr) / sizeof((arr)[0])) #define TO_STR(name) #name #define RESULT int -- cgit v1.1 From 8446e140181e85bab82daa273c1637b1eab01bd5 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 24 Aug 2020 11:42:15 +0200 Subject: openocd: use macro ARRAY_SIZE() There are still few cases where the macro ARRAY_SIZE() should be used in place of custom code. Use ARRAY_SIZE() whenever possible. Change-Id: Iba0127a02357bc704fe639e08562a4f9aa7011df Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6260 Reviewed-by: Xiang W Tested-by: jenkins --- src/flash/nor/psoc4.c | 2 +- src/flash/nor/stm32lx.c | 4 ++-- src/jtag/drivers/xds110.c | 2 +- src/rtos/mqx.c | 8 +++----- src/rtos/nuttx.c | 2 +- 5 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c index b606e18..3ca1f36 100644 --- a/src/flash/nor/psoc4.c +++ b/src/flash/nor/psoc4.c @@ -335,7 +335,7 @@ static int psoc4_sysreq(struct flash_bank *bank, uint8_t cmd, /* Execute wait code */ retval = target_run_algorithm(target, 0, NULL, - sizeof(reg_params) / sizeof(*reg_params), reg_params, + ARRAY_SIZE(reg_params), reg_params, sysreq_wait_algorithm->address, 0, 1000, &armv7m_info); if (retval != ERROR_OK) { LOG_ERROR("sysreq wait code execution failed"); diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c index 3cb1a49..b014d09 100644 --- a/src/flash/nor/stm32lx.c +++ b/src/flash/nor/stm32lx.c @@ -533,8 +533,8 @@ static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buff buf_set_u32(reg_params[2].value, 0, 32, this_count / 4); /* 5: Execute the bunch of code */ - retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params) - / sizeof(*reg_params), reg_params, + retval = target_run_algorithm(target, 0, NULL, + ARRAY_SIZE(reg_params), reg_params, write_algorithm->address, 0, 10000, &armv7m_info); if (retval != ERROR_OK) break; diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c index c492807..85a1b81 100644 --- a/src/jtag/drivers/xds110.c +++ b/src/jtag/drivers/xds110.c @@ -356,7 +356,7 @@ static bool usb_connect(void) /* Check for device vid/pid match */ libusb_get_device_descriptor(list[i], &desc); match = false; - for (device = 0; device < sizeof(vids)/sizeof(vids[0]); device++) { + for (device = 0; device < ARRAY_SIZE(vids); device++) { if (desc.idVendor == vids[device] && desc.idProduct == pids[device]) { match = true; diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 22cd721..9f895de 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -267,8 +267,7 @@ static int mqx_create( ) { /* check target name against supported architectures */ - int mqx_params_list_num = (sizeof(mqx_params_list)/sizeof(struct mqx_params)); - for (int i = 0; i < mqx_params_list_num; i++) { + for (unsigned int i = 0; i < ARRAY_SIZE(mqx_params_list); i++) { if (0 == strcmp(mqx_params_list[i].target_name, target->type->name)) { target->rtos->rtos_specific_params = (void *)&mqx_params_list[i]; /* LOG_DEBUG("MQX RTOS - valid architecture: %s", target->type->name); */ @@ -351,7 +350,7 @@ static int mqx_update_threads( uint8_t task_name[MQX_THREAD_NAME_LENGTH + 1]; uint32_t task_addr = 0, task_template = 0, task_state = 0; uint32_t task_name_addr = 0, task_id = 0, task_errno = 0; - uint32_t state_index = 0, state_max = 0; + uint32_t state_index = 0; uint32_t extra_info_length = 0; char *state_name = "Unknown"; @@ -412,8 +411,7 @@ static int mqx_update_threads( } task_state &= MQX_TASK_STATE_MASK; /* and search for defined state */ - state_max = (sizeof(mqx_states)/sizeof(struct mqx_state)); - for (state_index = 0; (state_index < state_max); state_index++) { + for (state_index = 0; state_index < ARRAY_SIZE(mqx_states); state_index++) { if (mqx_states[state_index].state == task_state) { state_name = mqx_states[state_index].name; break; diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c index 0705b17..c525471 100644 --- a/src/rtos/nuttx.c +++ b/src/rtos/nuttx.c @@ -314,7 +314,7 @@ static int nuttx_update_threads(struct rtos *rtos) state = tcb.dat[state_offset - 8]; thread->extra_info_str = NULL; - if (state < sizeof(task_state_str)/sizeof(char *)) { + if (state < ARRAY_SIZE(task_state_str)) { thread->extra_info_str = malloc(256); snprintf(thread->extra_info_str, 256, "pid:%d, %s", tcb.dat[pid_offset - 8] | -- cgit v1.1 From 240943c65a1fbfe67cf5bd6bacb72076ffb6f1ce Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 16 May 2021 15:43:28 +0200 Subject: rtos: use ARRAY_SIZE() and simplify rtos_type.create() Use the existing macro ARRAY_SIZE(). Rewrite the functions rtos_type.create() to simplify the logic. Change-Id: I8833354767045d1642801d26944c9087a77add00 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6261 Tested-by: jenkins --- src/rtos/FreeRTOS.c | 20 +++++++------------- src/rtos/ThreadX.c | 26 ++++++++++---------------- src/rtos/chibios.c | 23 +++++++++-------------- src/rtos/eCos.c | 26 ++++++++++---------------- 4 files changed, 36 insertions(+), 59 deletions(-) diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index f04b0a2..30c6e34 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -102,8 +102,6 @@ static const struct FreeRTOS_params FreeRTOS_params_list[] = { }, }; -#define FREERTOS_NUM_PARAMS ((int)(sizeof(FreeRTOS_params_list)/sizeof(struct FreeRTOS_params))) - static bool FreeRTOS_detect_rtos(struct target *target); static int FreeRTOS_create(struct target *target); static int FreeRTOS_update_threads(struct rtos *rtos); @@ -547,16 +545,12 @@ static bool FreeRTOS_detect_rtos(struct target *target) static int FreeRTOS_create(struct target *target) { - int i = 0; - while ((i < FREERTOS_NUM_PARAMS) && - (0 != strcmp(FreeRTOS_params_list[i].target_name, target->type->name))) { - i++; - } - if (i >= FREERTOS_NUM_PARAMS) { - LOG_ERROR("Could not find target in FreeRTOS compatibility list"); - return -1; - } + for (unsigned int i = 0; i < ARRAY_SIZE(FreeRTOS_params_list); i++) + if (strcmp(FreeRTOS_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&FreeRTOS_params_list[i]; + return 0; + } - target->rtos->rtos_specific_params = (void *) &FreeRTOS_params_list[i]; - return 0; + LOG_ERROR("Could not find target in FreeRTOS compatibility list"); + return -1; } diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c index 0b3fef0..53a74f8 100644 --- a/src/rtos/ThreadX.c +++ b/src/rtos/ThreadX.c @@ -65,7 +65,7 @@ static const struct ThreadX_thread_state ThreadX_thread_states[] = { { 13, "Waiting - Mutex" }, }; -#define THREADX_NUM_STATES (sizeof(ThreadX_thread_states)/sizeof(struct ThreadX_thread_state)) +#define THREADX_NUM_STATES ARRAY_SIZE(ThreadX_thread_states) #define ARM926EJS_REGISTERS_SIZE_SOLICITED (11 * 4) static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_solicited[] = { @@ -179,8 +179,6 @@ static const struct ThreadX_params ThreadX_params_list[] = { }, }; -#define THREADX_NUM_PARAMS ((int)(sizeof(ThreadX_params_list)/sizeof(struct ThreadX_params))) - enum ThreadX_symbol_values { ThreadX_VAL_tx_thread_current_ptr = 0, ThreadX_VAL_tx_thread_created_ptr = 1, @@ -599,18 +597,14 @@ static int ThreadX_get_thread_detail(struct rtos *rtos, static int ThreadX_create(struct target *target) { - int i = 0; - while ((i < THREADX_NUM_PARAMS) && - (0 != strcmp(ThreadX_params_list[i].target_name, target->type->name))) { - i++; - } - if (i >= THREADX_NUM_PARAMS) { - LOG_ERROR("Could not find target in ThreadX compatibility list"); - return -1; - } + for (unsigned int i = 0; i < ARRAY_SIZE(ThreadX_params_list); i++) + if (strcmp(ThreadX_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&ThreadX_params_list[i]; + target->rtos->current_thread = 0; + target->rtos->thread_details = NULL; + return 0; + } - target->rtos->rtos_specific_params = (void *) &ThreadX_params_list[i]; - target->rtos->current_thread = 0; - target->rtos->thread_details = NULL; - return 0; + LOG_ERROR("Could not find target in ThreadX compatibility list"); + return -1; } diff --git a/src/rtos/chibios.c b/src/rtos/chibios.c index 29abede..2a23017 100644 --- a/src/rtos/chibios.c +++ b/src/rtos/chibios.c @@ -74,7 +74,7 @@ static const char * const chibios_thread_states[] = { "READY", "CURRENT", "WTEXIT", "WTOREVT", "WTANDEVT", "SNDMSGQ", "SNDMSG", "WTMSG", "FINAL" }; -#define CHIBIOS_NUM_STATES (sizeof(chibios_thread_states)/sizeof(char *)) +#define CHIBIOS_NUM_STATES ARRAY_SIZE(chibios_thread_states) /* Maximum ChibiOS thread name. There is no real limit set by ChibiOS but 64 * chars ought to be enough. @@ -100,7 +100,6 @@ static struct chibios_params chibios_params_list[] = { NULL, /* stacking_info */ } }; -#define CHIBIOS_NUM_PARAMS ((int)(sizeof(chibios_params_list)/sizeof(struct chibios_params))) static bool chibios_detect_rtos(struct target *target); static int chibios_create(struct target *target); @@ -529,17 +528,13 @@ static bool chibios_detect_rtos(struct target *target) static int chibios_create(struct target *target) { - int i = 0; - while ((i < CHIBIOS_NUM_PARAMS) && - (0 != strcmp(chibios_params_list[i].target_name, target->type->name))) { - i++; - } - if (i >= CHIBIOS_NUM_PARAMS) { - LOG_WARNING("Could not find target \"%s\" in ChibiOS compatibility " - "list", target->type->name); - return -1; - } + for (unsigned int i = 0; i < ARRAY_SIZE(chibios_params_list); i++) + if (strcmp(chibios_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&chibios_params_list[i]; + return 0; + } - target->rtos->rtos_specific_params = (void *) &chibios_params_list[i]; - return 0; + LOG_WARNING("Could not find target \"%s\" in ChibiOS compatibility " + "list", target->type->name); + return -1; } diff --git a/src/rtos/eCos.c b/src/rtos/eCos.c index 9501a55..1b1e73e 100644 --- a/src/rtos/eCos.c +++ b/src/rtos/eCos.c @@ -47,7 +47,7 @@ static const struct eCos_thread_state eCos_thread_states[] = { { 16, "Exited" } }; -#define ECOS_NUM_STATES (sizeof(eCos_thread_states)/sizeof(struct eCos_thread_state)) +#define ECOS_NUM_STATES ARRAY_SIZE(eCos_thread_states) struct eCos_params { const char *target_name; @@ -73,8 +73,6 @@ static const struct eCos_params eCos_params_list[] = { } }; -#define ECOS_NUM_PARAMS ((int)(sizeof(eCos_params_list)/sizeof(struct eCos_params))) - enum eCos_symbol_values { eCos_VAL_thread_list = 0, eCos_VAL_current_thread_ptr = 1 @@ -375,18 +373,14 @@ static bool eCos_detect_rtos(struct target *target) static int eCos_create(struct target *target) { - int i = 0; - while ((i < ECOS_NUM_PARAMS) && - (0 != strcmp(eCos_params_list[i].target_name, target->type->name))) { - i++; - } - if (i >= ECOS_NUM_PARAMS) { - LOG_ERROR("Could not find target in eCos compatibility list"); - return -1; - } + for (unsigned int i = 0; i < ARRAY_SIZE(eCos_params_list); i++) + if (strcmp(eCos_params_list[i].target_name, target->type->name) == 0) { + target->rtos->rtos_specific_params = (void *)&eCos_params_list[i]; + target->rtos->current_thread = 0; + target->rtos->thread_details = NULL; + return 0; + } - target->rtos->rtos_specific_params = (void *) &eCos_params_list[i]; - target->rtos->current_thread = 0; - target->rtos->thread_details = NULL; - return 0; + LOG_ERROR("Could not find target in eCos compatibility list"); + return -1; } -- cgit v1.1 From 30f3a2a650aa2375ab932203091a62d5bb109419 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Fri, 21 May 2021 18:01:59 +0200 Subject: tcl: remove remaining deprecated commands There are still few adapter_khz, ftdi_location, jtag_nsrst_delay and xds110_serial strolling around ... Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6270 Tested-by: jenkins --- tcl/board/dp_busblaster_v4.cfg | 2 +- tcl/board/imx53loco.cfg | 2 +- tcl/board/kasli.cfg | 2 +- tcl/board/nds32_corvettef1.cfg | 2 +- tcl/board/sayma_amc.cfg | 2 +- tcl/board/snps_hsdk.cfg | 2 +- tcl/interface/xds110.cfg | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tcl/board/dp_busblaster_v4.cfg b/tcl/board/dp_busblaster_v4.cfg index 066b54f..7b3bee8 100644 --- a/tcl/board/dp_busblaster_v4.cfg +++ b/tcl/board/dp_busblaster_v4.cfg @@ -10,7 +10,7 @@ # https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf # # To reprogram the on-board CPLD do: -# openocd -f board/dp_busblaster_v4.cfg -c "adapter_khz 1000; init; svf ; shutdown" +# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf ; shutdown" # source [find interface/ftdi/dp_busblaster.cfg] diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg index d4ec060..c4d45f0 100644 --- a/tcl/board/imx53loco.cfg +++ b/tcl/board/imx53loco.cfg @@ -19,7 +19,7 @@ adapter speed 3000 jtag_rclk 1000 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } -#jtag_nsrst_delay 200 +#adapter srst delay 200 #jtag_ntrst_delay 200 $_TARGETNAME configure -event "reset-assert" { diff --git a/tcl/board/kasli.cfg b/tcl/board/kasli.cfg index 06cc1e6..d492249 100644 --- a/tcl/board/kasli.cfg +++ b/tcl/board/kasli.cfg @@ -3,7 +3,7 @@ ftdi_device_desc "Quad RS232-HS" ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 ftdi_layout_init 0x0008 0x000b -# ftdi_location 1:8 +# adapter usb location 1:8 reset_config none transport select jtag diff --git a/tcl/board/nds32_corvettef1.cfg b/tcl/board/nds32_corvettef1.cfg index 1a3782c..cec1723 100644 --- a/tcl/board/nds32_corvettef1.cfg +++ b/tcl/board/nds32_corvettef1.cfg @@ -4,7 +4,7 @@ # ADP-Corvette-F1 R2.0 # http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/ -adapter_khz 10000 +adapter speed 10000 adapter driver ftdi ftdi_device_desc "Dual RS232-HS" diff --git a/tcl/board/sayma_amc.cfg b/tcl/board/sayma_amc.cfg index 009eb78..64c0854 100644 --- a/tcl/board/sayma_amc.cfg +++ b/tcl/board/sayma_amc.cfg @@ -15,7 +15,7 @@ ftdi_device_desc "Quad RS232-HS" ftdi_vid_pid 0x0403 0x6011 ftdi_channel 0 # Use this to distinguish multiple boards by topology -#ftdi_location 5:1 +#adapter usb location 5:1 # sampling on falling edge generally seems to work and accelerates things but # is not fully tested #ftdi_tdo_sample_edge falling diff --git a/tcl/board/snps_hsdk.cfg b/tcl/board/snps_hsdk.cfg index fed7343..a6228f4 100644 --- a/tcl/board/snps_hsdk.cfg +++ b/tcl/board/snps_hsdk.cfg @@ -9,7 +9,7 @@ # source [find interface/ftdi/snps_sdp.cfg] -adapter_khz 10000 +adapter speed 10000 # ARCs supports only JTAG. transport select jtag diff --git a/tcl/interface/xds110.cfg b/tcl/interface/xds110.cfg index edc438d..51f4e28 100644 --- a/tcl/interface/xds110.cfg +++ b/tcl/interface/xds110.cfg @@ -9,4 +9,4 @@ adapter driver xds110 # Use serial number option to use a specific XDS110 # when more than one are connected to the host. -#xds110_serial 00000000 +#xds110 serial 00000000 -- cgit v1.1 From a40cbd85e08df2c87b200c6053c2a608f3bc16e6 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 27 Mar 2021 21:41:30 +0100 Subject: help text: remove trailing space Some help text end with a useless space character. Remove it. Change-Id: I397e1194fac8042f0fab694222f925f906716de3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6222 Tested-by: jenkins --- src/jtag/adapter.c | 2 +- src/jtag/drivers/cmsis_dap.c | 2 +- src/jtag/drivers/ftdi.c | 2 +- src/jtag/hla/hla_interface.c | 2 +- src/jtag/hla/hla_transport.c | 2 +- src/jtag/tcl.c | 4 ++-- src/target/armv4_5.c | 2 +- src/target/armv7a_cache_l2x.c | 2 +- src/target/dsp563xx.c | 2 +- src/target/target.c | 6 +++--- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index cf579ed..0dcb78f 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -584,7 +584,7 @@ static const struct command_registration adapter_command_handlers[] = { .handler = adapter_transports_command, .mode = COMMAND_CONFIG, .help = "Declare transports the adapter supports.", - .usage = "transport ... ", + .usage = "transport ...", }, { .name = "usb", diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index 927b33b..c259375 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -1763,7 +1763,7 @@ static const struct command_registration cmsis_dap_command_handlers[] = { .handler = &cmsis_dap_handle_vid_pid_command, .mode = COMMAND_CONFIG, .help = "the vendor ID and product ID of the CMSIS-DAP device", - .usage = "(vid pid)* ", + .usage = "(vid pid)*", }, { .name = "cmsis_dap_serial", diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c index e13977f..210d0f7 100644 --- a/src/jtag/drivers/ftdi.c +++ b/src/jtag/drivers/ftdi.c @@ -1004,7 +1004,7 @@ static const struct command_registration ftdi_command_handlers[] = { .handler = &ftdi_handle_vid_pid_command, .mode = COMMAND_CONFIG, .help = "the vendor ID and product ID of the FTDI device", - .usage = "(vid pid)* ", + .usage = "(vid pid)*", }, { .name = "ftdi_tdo_sample_edge", diff --git a/src/jtag/hla/hla_interface.c b/src/jtag/hla/hla_interface.c index 04e01d2..1565176 100644 --- a/src/jtag/hla/hla_interface.c +++ b/src/jtag/hla/hla_interface.c @@ -359,7 +359,7 @@ static const struct command_registration hl_interface_command_handlers[] = { .handler = &hl_interface_handle_vid_pid_command, .mode = COMMAND_CONFIG, .help = "the vendor and product ID of the adapter", - .usage = "(vid pid)* ", + .usage = "(vid pid)*", }, { .name = "hla_stlink_backend", diff --git a/src/jtag/hla/hla_transport.c b/src/jtag/hla/hla_transport.c index 1002826..d925b17 100644 --- a/src/jtag/hla/hla_transport.c +++ b/src/jtag/hla/hla_transport.c @@ -76,7 +76,7 @@ hl_transport_jtag_subcommand_handlers[] = { .help = "Create a new TAP instance named basename.tap_type, " "and appends it to the scan chain.", .usage = "basename tap_type '-irlen' count " - "['-expected_id' number] ", + "['-expected_id' number]", }, { .name = "init", diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 8a52c0f..5dc2f14 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -887,7 +887,7 @@ static const struct command_registration jtag_subcommand_handlers[] = { "['-expected_id' number] " "['-ignore-version'] " "['-ircapture' number] " - "['-mask' number] ", + "['-mask' number]", }, { .name = "tapisenabled", @@ -1353,7 +1353,7 @@ static const struct command_registration jtag_command_handlers[] = { .mode = COMMAND_ANY, .help = "Wait for an SRST deassert. " "Useful for cases where you need something to happen within ms " - "of an srst deassert. Timeout in ms ", + "of an srst deassert. Timeout in ms", .usage = "ms", }, { diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index b725853..8ba9136 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1149,7 +1149,7 @@ static const struct command_registration arm_exec_command_handlers[] = { .handler = handle_arm_disassemble_command, .mode = COMMAND_EXEC, .usage = "address [count ['thumb']]", - .help = "disassemble instructions ", + .help = "disassemble instructions", }, { .name = "mcr", diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c index 3607a51..8ecdb00 100644 --- a/src/target/armv7a_cache_l2x.c +++ b/src/target/armv7a_cache_l2x.c @@ -325,7 +325,7 @@ static const struct command_registration arm7a_l2x_cache_commands[] = { .name = "conf", .handler = armv7a_l2x_cache_conf_cmd, .mode = COMMAND_ANY, - .help = "configure l2x cache ", + .help = "configure l2x cache", .usage = " ", }, { diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index b825429..21bed89 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -2243,7 +2243,7 @@ static const struct command_registration dsp563xx_command_handlers[] = { .handler = dsp563xx_remove_watchpoint_command, .mode = COMMAND_EXEC, .help = "remove watchpoint custom", - .usage = " ", + .usage = "", }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/target.c b/src/target/target.c index d60e642..1c1deee 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -6677,15 +6677,15 @@ static const struct command_registration target_exec_command_handlers[] = { .handler = handle_target_reset_nag, .mode = COMMAND_ANY, .help = "Nag after each reset about options that could have been " - "enabled to improve performance. ", + "enabled to improve performance.", .usage = "['enable'|'disable']", }, { .name = "ps", .handler = handle_ps_command, .mode = COMMAND_EXEC, - .help = "list all tasks ", - .usage = " ", + .help = "list all tasks", + .usage = "", }, { .name = "test_mem_access", -- cgit v1.1 From bfce4b41d15e8983eab49c9fc1aab5fb169c602a Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sat, 27 Mar 2021 22:23:50 +0100 Subject: help: fix line size in 'usage' output The implementation of command 'usage' is broken while checking the line limit of 76 chars per line (e.g. 'usage load_image') and the line wrapping is not correct. The same broken code is used for the first output line of command 'help' too. When call command_help_show_wrap(), include the command's name in the string so the whole text would be wrapped. Change-Id: Idece01ce54994db7e851d8522435ff764b11f3ac Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6223 Tested-by: jenkins --- src/helper/command.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/helper/command.c b/src/helper/command.c index c3d2e95..d4f6a0a 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -820,14 +820,13 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c, ((c->help != NULL) && (strstr(c->help, cmd_match) != NULL)); if (is_match) { - command_help_show_indent(n); - LOG_USER_N("%s", c->cmd_name); - if (c->usage && strlen(c->usage) > 0) { - LOG_USER_N(" "); - command_help_show_wrap(c->usage, 0, n + 5); - } else - LOG_USER_N("\n"); + char *msg = alloc_printf("%s %s", c->cmd_name, c->usage); + command_help_show_wrap(msg, n, n + 5); + free(msg); + } else { + command_help_show_wrap(c->cmd_name, n, n + 5); + } } if (is_match && show_help) { -- cgit v1.1 From 1d24b669118fdf3097b165093fd75905ec450589 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 28 Dec 2017 16:27:18 +0100 Subject: LICENSES: Add the MIT license Add the full text of the MIT license to the kernel tree. It was copied directly from: https://spdx.org/licenses/MIT.html#licenseText Add the required tags for reference and tooling. Change-Id: I94a5dea5ced6421809ea2a3448f8dda19a93f5c9 Signed-off-by: Thomas Gleixner Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6219 Tested-by: jenkins --- LICENSES/preferred/MIT | 30 ++++++++++++++++++++++++++++++ Makefile.am | 1 + 2 files changed, 31 insertions(+) create mode 100644 LICENSES/preferred/MIT diff --git a/LICENSES/preferred/MIT b/LICENSES/preferred/MIT new file mode 100644 index 0000000..f33a68c --- /dev/null +++ b/LICENSES/preferred/MIT @@ -0,0 +1,30 @@ +Valid-License-Identifier: MIT +SPDX-URL: https://spdx.org/licenses/MIT.html +Usage-Guide: + To use the MIT License put the following SPDX tag/value pair into a + comment according to the placement guidelines in the licensing rules + documentation: + SPDX-License-Identifier: MIT +License-Text: + +MIT License + +Copyright (c) + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/Makefile.am b/Makefile.am index fc444f1..a047298 100644 --- a/Makefile.am +++ b/Makefile.am @@ -57,6 +57,7 @@ EXTRA_DIST += \ LICENSES/preferred/GFDL-1.2 \ LICENSES/preferred/gfdl-1.2.texi.readme \ LICENSES/preferred/GPL-2.0 \ + LICENSES/preferred/MIT \ LICENSES/stand-alone/GPL-3.0 \ tools/logger.pl \ tools/rlink_make_speed_table \ -- cgit v1.1 From bc944c832bcef45674fddebdf27a87e2abfdb168 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Mon, 9 Nov 2020 23:08:24 +0100 Subject: stlink: add comment of firmware version for each flag bit Change-Id: I7f7c7b9c9cfd88125f82662ed864a2c0715140b1 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6211 Tested-by: jenkins --- src/jtag/drivers/stlink_usb.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 60a2c31..1a19634 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -413,17 +413,17 @@ static inline int stlink_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, i * Map the relevant features, quirks and workaround for specific firmware * version of stlink */ -#define STLINK_F_HAS_TRACE BIT(0) -#define STLINK_F_HAS_SWD_SET_FREQ BIT(1) -#define STLINK_F_HAS_JTAG_SET_FREQ BIT(2) -#define STLINK_F_HAS_MEM_16BIT BIT(3) -#define STLINK_F_HAS_GETLASTRWSTATUS2 BIT(4) -#define STLINK_F_HAS_DAP_REG BIT(5) -#define STLINK_F_QUIRK_JTAG_DP_READ BIT(6) -#define STLINK_F_HAS_AP_INIT BIT(7) -#define STLINK_F_HAS_DPBANKSEL BIT(8) -#define STLINK_F_HAS_RW8_512BYTES BIT(9) -#define STLINK_F_FIX_CLOSE_AP BIT(10) +#define STLINK_F_HAS_TRACE BIT(0) /* v2>=j13 || v3 */ +#define STLINK_F_HAS_SWD_SET_FREQ BIT(1) /* v2>=j22 */ +#define STLINK_F_HAS_JTAG_SET_FREQ BIT(2) /* v2>=j24 */ +#define STLINK_F_HAS_MEM_16BIT BIT(3) /* v2>=j26 || v3 */ +#define STLINK_F_HAS_GETLASTRWSTATUS2 BIT(4) /* v2>=j15 || v3 */ +#define STLINK_F_HAS_DAP_REG BIT(5) /* v2>=j24 || v3 */ +#define STLINK_F_QUIRK_JTAG_DP_READ BIT(6) /* v2>=j24 && v2=j28 || v3 */ +#define STLINK_F_HAS_DPBANKSEL BIT(8) /* v2>=j32 || v3>=j2 */ +#define STLINK_F_HAS_RW8_512BYTES BIT(9) /* v3>=j6 */ +#define STLINK_F_FIX_CLOSE_AP BIT(10) /* v2>=j29 || v3 */ /* aliases */ #define STLINK_F_HAS_TARGET_VOLT STLINK_F_HAS_TRACE -- cgit v1.1 From 9847a692a7a937555bc4e66e5e1d5205165b57bc Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Tue, 10 Nov 2020 13:49:13 +0100 Subject: stlink: reorder the flag macro by firmware release The corresponding bit for each macro is changed, but this is not relevant in the code. Change-Id: I7039464f5a3d55d008208f44952aadeb815bd5a3 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6212 Tested-by: jenkins --- src/jtag/drivers/stlink_usb.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 1a19634..7e3280b 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -413,17 +413,17 @@ static inline int stlink_usb_xfer_noerrcheck(void *handle, const uint8_t *buf, i * Map the relevant features, quirks and workaround for specific firmware * version of stlink */ -#define STLINK_F_HAS_TRACE BIT(0) /* v2>=j13 || v3 */ -#define STLINK_F_HAS_SWD_SET_FREQ BIT(1) /* v2>=j22 */ -#define STLINK_F_HAS_JTAG_SET_FREQ BIT(2) /* v2>=j24 */ -#define STLINK_F_HAS_MEM_16BIT BIT(3) /* v2>=j26 || v3 */ -#define STLINK_F_HAS_GETLASTRWSTATUS2 BIT(4) /* v2>=j15 || v3 */ -#define STLINK_F_HAS_DAP_REG BIT(5) /* v2>=j24 || v3 */ -#define STLINK_F_QUIRK_JTAG_DP_READ BIT(6) /* v2>=j24 && v2=j28 || v3 */ -#define STLINK_F_HAS_DPBANKSEL BIT(8) /* v2>=j32 || v3>=j2 */ -#define STLINK_F_HAS_RW8_512BYTES BIT(9) /* v3>=j6 */ -#define STLINK_F_FIX_CLOSE_AP BIT(10) /* v2>=j29 || v3 */ +#define STLINK_F_HAS_TRACE BIT(0) /* v2>=j13 || v3 */ +#define STLINK_F_HAS_GETLASTRWSTATUS2 BIT(1) /* v2>=j15 || v3 */ +#define STLINK_F_HAS_SWD_SET_FREQ BIT(2) /* v2>=j22 */ +#define STLINK_F_HAS_JTAG_SET_FREQ BIT(3) /* v2>=j24 */ +#define STLINK_F_QUIRK_JTAG_DP_READ BIT(4) /* v2>=j24 && v2=j24 || v3 */ +#define STLINK_F_HAS_MEM_16BIT BIT(6) /* v2>=j26 || v3 */ +#define STLINK_F_HAS_AP_INIT BIT(7) /* v2>=j28 || v3 */ +#define STLINK_F_FIX_CLOSE_AP BIT(8) /* v2>=j29 || v3 */ +#define STLINK_F_HAS_DPBANKSEL BIT(9) /* v2>=j32 || v3>=j2 */ +#define STLINK_F_HAS_RW8_512BYTES BIT(10) /* v3>=j6 */ /* aliases */ #define STLINK_F_HAS_TARGET_VOLT STLINK_F_HAS_TRACE -- cgit v1.1 From 3b4e40120bc9c56442d1e177ecfbc8c4faa0ac7f Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Thu, 20 May 2021 18:29:10 +0200 Subject: tcl/board: Add ST NUCLEO-8S208RB Change-Id: I384c6ad9b4cbabbc004160677f600d8c4bd3eb71 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6268 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/board/st_nucleo_8s208rb.cfg | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 tcl/board/st_nucleo_8s208rb.cfg diff --git a/tcl/board/st_nucleo_8s208rb.cfg b/tcl/board/st_nucleo_8s208rb.cfg new file mode 100644 index 0000000..0d3c0c9 --- /dev/null +++ b/tcl/board/st_nucleo_8s208rb.cfg @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip. +# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html + +source [find interface/stlink-dap.cfg] + +transport select swim + +# 128 KiB flash and 2 KiB EEPROM +set FLASHEND 0x27fff +set EEPROMEND 0x47ff + +source [find target/stm8s.cfg] + +reset_config srst_only -- cgit v1.1 From b40dc09dd9e05497bf956ca91f7153aa34b24854 Mon Sep 17 00:00:00 2001 From: micbis Date: Wed, 26 May 2021 19:11:05 +0200 Subject: target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands When a WAIT occurs the commands after the WAIT are replayed and the STICKYORUN is cleared. However if another WAIT occurs during the command replay, the command itself is resent but the STICKYORUN bit shall also be cleared. If this is not done, the MEM-AP hangs. Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1 Signed-off-by: micbis Reviewed-on: http://openocd.zylin.com/6278 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- src/target/adi_v5_jtag.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index 6dede97..239253d 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -574,6 +574,13 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap) retval = ERROR_JTAG_DEVICE_ERROR; break; } + LOG_INFO("DAP transaction stalled during replay (WAIT) - resending"); + /* clear the sticky overrun condition */ + retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC, + DP_CTRL_STAT, DPAP_WRITE, + dap->dp_ctrl_stat | SSTICKYORUN, NULL, 0); + if (retval != ERROR_OK) + break; } while (timeval_ms() - time_now < 1000); if (retval == ERROR_OK) { -- cgit v1.1 From 1fb736f6c5a69f743dd90e68045f7b4e6a0f8c78 Mon Sep 17 00:00:00 2001 From: Chengyu Zheng Date: Wed, 14 Dec 2016 12:18:10 +0100 Subject: target/cortex_a: add support for watchpoints The current implementation of OpenOCD does not support watchpoints for cortex_a architecture. So, I replaced the add_watchpoint and remove_watchpoint with the specific implementation for the cortex a and using the breakpoint implementation and the arm documentation [1] as reference. In particular, I have made the following changes: * added the following functions - cortex_a_add_watchpoint This wrapper function check whether there are any watchpoint available on the target device by calling cortex_a_set_watchpoint. - cortex_a_set_watchpoint This function is responsible for settings the watchpoint register pair. In particular, it sets the WVR and the WCR registers with the cortex_a_dap command. - cortex_a_remove_watchpoint This wrapper function the selected watchpoint on the target device by calling cortex_a_unset_watchpoint. - cortex_a_unset_watchpoint This function sets both the WVR and the WCR registers to zero, thus unsetting the watchpoint. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html Change-Id: I86611dab474cb84836662af572b17636dc68e282 Signed-off-by: Chengyu Zheng Reviewed-on: http://openocd.zylin.com/3913 Reviewed-by: Antonio Borneo Reviewed-by: Matthias Welwarsky Reviewed-by: Marc Schink Tested-by: jenkins --- src/target/arm_dpm.c | 8 ++- src/target/armv7a.c | 2 - src/target/cortex_a.c | 190 ++++++++++++++++++++++++++++++++++++++++++++++++-- src/target/cortex_a.h | 10 +++ 4 files changed, 201 insertions(+), 9 deletions(-) diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index e172fad..058f0df 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -1088,9 +1088,11 @@ int arm_dpm_setup(struct arm_dpm *dpm) target->type->remove_breakpoint = dpm_remove_breakpoint; } - /* watchpoint setup */ - target->type->add_watchpoint = dpm_add_watchpoint; - target->type->remove_watchpoint = dpm_remove_watchpoint; + /* watchpoint setup -- optional until it works everywhere */ + if (!target->type->add_watchpoint) { + target->type->add_watchpoint = dpm_add_watchpoint; + target->type->remove_watchpoint = dpm_remove_watchpoint; + } /* FIXME add vector catch support */ diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 5c9f308..5f7b008 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -570,8 +570,6 @@ int armv7a_arch_state(struct target *target) if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); - if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv7a->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 5018a91..9e8248a 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -23,6 +23,9 @@ * Copyright (C) 2013 Kamal Dasu * * kdasu.kdev@gmail.com * * * + * Copyright (C) 2016 Chengyu Zheng * + * chengyu.zheng@polimi.it : watchpoint support * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -80,6 +83,16 @@ static int cortex_a_virt2phys(struct target *target, static int cortex_a_read_cpu_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +static unsigned int ilog2(unsigned int x) +{ + unsigned int y = 0; + x /= 2; + while (x) { + ++y; + x /= 2; + } + return y; +} /* restore cp15_control_reg at resume */ static int cortex_a_restore_cp15_control_reg(struct target *target) @@ -1658,6 +1671,161 @@ static int cortex_a_remove_breakpoint(struct target *target, struct breakpoint * return ERROR_OK; } +/** + * Sets a watchpoint for an Cortex-A target in one of the watchpoint units. It is + * considered a bug to call this function when there are no available watchpoint + * units. + * + * @param target Pointer to an Cortex-A target to set a watchpoint on + * @param watchpoint Pointer to the watchpoint to be set + * @return Error status if watchpoint set fails or the result of executing the + * JTAG queue + */ +static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *watchpoint) +{ + int retval = ERROR_OK; + int wrp_i = 0; + uint32_t control; + uint8_t address_mask = ilog2(watchpoint->length); + uint8_t byte_address_select = 0xFF; + uint8_t load_store_access_control = 0x3; + struct cortex_a_common *cortex_a = target_to_cortex_a(target); + struct armv7a_common *armv7a = &cortex_a->armv7a_common; + struct cortex_a_wrp *wrp_list = cortex_a->wrp_list; + + if (watchpoint->set) { + LOG_WARNING("watchpoint already set"); + return retval; + } + + /* check available context WRPs */ + while (wrp_list[wrp_i].used && (wrp_i < cortex_a->wrp_num)) + wrp_i++; + + if (wrp_i >= cortex_a->wrp_num) { + LOG_ERROR("ERROR Can not find free Watchpoint Register Pair"); + return ERROR_FAIL; + } + + if (address_mask == 0x1 || address_mask == 0x2) { + LOG_WARNING("length must be a power of 2 and different than 2 and 4"); + return ERROR_FAIL; + } + + watchpoint->set = wrp_i + 1; + control = (address_mask << 24) | + (byte_address_select << 5) | + (load_store_access_control << 3) | + (0x3 << 1) | 1; + wrp_list[wrp_i].used = 1; + wrp_list[wrp_i].value = (watchpoint->address & 0xFFFFFFFC); + wrp_list[wrp_i].control = control; + + retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn, + wrp_list[wrp_i].value); + if (retval != ERROR_OK) + return retval; + + retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn, + wrp_list[wrp_i].control); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("wp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i, + wrp_list[wrp_i].control, + wrp_list[wrp_i].value); + + return ERROR_OK; +} + +/** + * Unset an existing watchpoint and clear the used watchpoint unit. + * + * @param target Pointer to the target to have the watchpoint removed + * @param watchpoint Pointer to the watchpoint to be removed + * @return Error status while trying to unset the watchpoint or the result of + * executing the JTAG queue + */ +static int cortex_a_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) +{ + int retval; + struct cortex_a_common *cortex_a = target_to_cortex_a(target); + struct armv7a_common *armv7a = &cortex_a->armv7a_common; + struct cortex_a_wrp *wrp_list = cortex_a->wrp_list; + + if (!watchpoint->set) { + LOG_WARNING("watchpoint not set"); + return ERROR_OK; + } + + int wrp_i = watchpoint->set - 1; + if (wrp_i < 0 || wrp_i >= cortex_a->wrp_num) { + LOG_DEBUG("Invalid WRP number in watchpoint"); + return ERROR_OK; + } + LOG_DEBUG("wrp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, wrp_i, + wrp_list[wrp_i].control, wrp_list[wrp_i].value); + wrp_list[wrp_i].used = 0; + wrp_list[wrp_i].value = 0; + wrp_list[wrp_i].control = 0; + retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_WCR_BASE + 4 * wrp_list[wrp_i].WRPn, + wrp_list[wrp_i].control); + if (retval != ERROR_OK) + return retval; + retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_WVR_BASE + 4 * wrp_list[wrp_i].WRPn, + wrp_list[wrp_i].value); + if (retval != ERROR_OK) + return retval; + watchpoint->set = 0; + + return ERROR_OK; +} + +/** + * Add a watchpoint to an Cortex-A target. If there are no watchpoint units + * available, an error response is returned. + * + * @param target Pointer to the Cortex-A target to add a watchpoint to + * @param watchpoint Pointer to the watchpoint to be added + * @return Error status while trying to add the watchpoint + */ +static int cortex_a_add_watchpoint(struct target *target, struct watchpoint *watchpoint) +{ + struct cortex_a_common *cortex_a = target_to_cortex_a(target); + + if (cortex_a->wrp_num_available < 1) { + LOG_INFO("no hardware watchpoint available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + cortex_a->wrp_num_available--; + return cortex_a_set_watchpoint(target, watchpoint); +} + +/** + * Remove a watchpoint from an Cortex-A target. The watchpoint will be unset and + * the used watchpoint unit will be reopened. + * + * @param target Pointer to the target to remove a watchpoint from + * @param watchpoint Pointer to the watchpoint to be removed + * @return Result of trying to unset the watchpoint + */ +static int cortex_a_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) +{ + struct cortex_a_common *cortex_a = target_to_cortex_a(target); + + if (watchpoint->set) { + cortex_a->wrp_num_available++; + cortex_a_unset_watchpoint(target, watchpoint); + } + return ERROR_OK; +} + + /* * Cortex-A Reset functions */ @@ -2837,6 +3005,20 @@ static int cortex_a_examine_first(struct target *target) LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num); + /* Setup Watchpoint Register Pairs */ + cortex_a->wrp_num = ((didr >> 28) & 0x0F) + 1; + cortex_a->wrp_num_available = cortex_a->brp_num; + free(cortex_a->wrp_list); + cortex_a->wrp_list = calloc(cortex_a->wrp_num, sizeof(struct cortex_a_wrp)); + for (i = 0; i < cortex_a->wrp_num; i++) { + cortex_a->wrp_list[i].used = 0; + cortex_a->wrp_list[i].value = 0; + cortex_a->wrp_list[i].control = 0; + cortex_a->wrp_list[i].WRPn = i; + } + + LOG_DEBUG("Configured %i hw watchpoints", cortex_a->wrp_num); + /* select debug_ap as default */ swjdp->apsel = armv7a->debug_ap->ap_num; @@ -3173,8 +3355,8 @@ struct target_type cortexa_target = { .add_context_breakpoint = cortex_a_add_context_breakpoint, .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint, .remove_breakpoint = cortex_a_remove_breakpoint, - .add_watchpoint = NULL, - .remove_watchpoint = NULL, + .add_watchpoint = cortex_a_add_watchpoint, + .remove_watchpoint = cortex_a_remove_watchpoint, .commands = cortex_a_command_handlers, .target_create = cortex_a_target_create, @@ -3250,8 +3432,8 @@ struct target_type cortexr4_target = { .add_context_breakpoint = cortex_a_add_context_breakpoint, .add_hybrid_breakpoint = cortex_a_add_hybrid_breakpoint, .remove_breakpoint = cortex_a_remove_breakpoint, - .add_watchpoint = NULL, - .remove_watchpoint = NULL, + .add_watchpoint = cortex_a_add_watchpoint, + .remove_watchpoint = cortex_a_remove_watchpoint, .commands = cortex_r4_command_handlers, .target_create = cortex_r4_target_create, diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index 197a599..dd135ec 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -71,6 +71,13 @@ struct cortex_a_brp { uint8_t BRPn; }; +struct cortex_a_wrp { + int used; + uint32_t value; + uint32_t control; + uint8_t WRPn; +}; + struct cortex_a_common { int common_magic; @@ -92,6 +99,9 @@ struct cortex_a_common { int brp_num; int brp_num_available; struct cortex_a_brp *brp_list; + int wrp_num; + int wrp_num_available; + struct cortex_a_wrp *wrp_list; uint32_t cpuid; uint32_t didr; -- cgit v1.1 From ffaef5809c68d81359de5573d3971a4b6bb521c3 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 29 Apr 2021 09:22:00 +0200 Subject: target/cortex_a: fix number of watchpoints Decrement the available watchpoints only when succeed setting it. Initialize the available watchpoint with the correct value. Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6196 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- src/target/cortex_a.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 9e8248a..78daed3 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1802,8 +1802,12 @@ static int cortex_a_add_watchpoint(struct target *target, struct watchpoint *wat return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } + int retval = cortex_a_set_watchpoint(target, watchpoint); + if (retval != ERROR_OK) + return retval; + cortex_a->wrp_num_available--; - return cortex_a_set_watchpoint(target, watchpoint); + return ERROR_OK; } /** @@ -3007,7 +3011,7 @@ static int cortex_a_examine_first(struct target *target) /* Setup Watchpoint Register Pairs */ cortex_a->wrp_num = ((didr >> 28) & 0x0F) + 1; - cortex_a->wrp_num_available = cortex_a->brp_num; + cortex_a->wrp_num_available = cortex_a->wrp_num; free(cortex_a->wrp_list); cortex_a->wrp_list = calloc(cortex_a->wrp_num, sizeof(struct cortex_a_wrp)); for (i = 0; i < cortex_a->wrp_num; i++) { -- cgit v1.1 From 0c64bb2583a67b551a482ddc13a08dc71a143da3 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 29 Apr 2021 10:49:50 +0200 Subject: target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes Use byte address select for 1 and 2 bytes length. Use normal mode for 4 bytes length. Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6197 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- src/target/cortex_a.c | 46 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 78daed3..9a48cc8 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -61,6 +61,7 @@ #include "jtag/interface.h" #include "transport/transport.h" #include "smp.h" +#include #include static int cortex_a_poll(struct target *target); @@ -1686,8 +1687,9 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat int retval = ERROR_OK; int wrp_i = 0; uint32_t control; - uint8_t address_mask = ilog2(watchpoint->length); - uint8_t byte_address_select = 0xFF; + uint32_t address; + uint8_t address_mask; + uint8_t byte_address_select; uint8_t load_store_access_control = 0x3; struct cortex_a_common *cortex_a = target_to_cortex_a(target); struct armv7a_common *armv7a = &cortex_a->armv7a_common; @@ -1707,18 +1709,52 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat return ERROR_FAIL; } - if (address_mask == 0x1 || address_mask == 0x2) { - LOG_WARNING("length must be a power of 2 and different than 2 and 4"); + if (watchpoint->length == 0 || watchpoint->length > 0x80000000U || + (watchpoint->length & (watchpoint->length - 1))) { + LOG_WARNING("watchpoint length must be a power of 2"); return ERROR_FAIL; } + if (watchpoint->address & (watchpoint->length - 1)) { + LOG_WARNING("watchpoint address must be aligned at length"); + return ERROR_FAIL; + } + + /* FIXME: ARM DDI 0406C: address_mask is optional. What to do if it's missing? */ + /* handle wp length 1 and 2 through byte select */ + switch (watchpoint->length) { + case 1: + byte_address_select = BIT(watchpoint->address & 0x3); + address = watchpoint->address & ~0x3; + address_mask = 0; + break; + + case 2: + byte_address_select = 0x03 << (watchpoint->address & 0x2); + address = watchpoint->address & ~0x3; + address_mask = 0; + break; + + case 4: + byte_address_select = 0x0f; + address = watchpoint->address; + address_mask = 0; + break; + + default: + byte_address_select = 0xff; + address = watchpoint->address; + address_mask = ilog2(watchpoint->length); + break; + } + watchpoint->set = wrp_i + 1; control = (address_mask << 24) | (byte_address_select << 5) | (load_store_access_control << 3) | (0x3 << 1) | 1; wrp_list[wrp_i].used = 1; - wrp_list[wrp_i].value = (watchpoint->address & 0xFFFFFFFC); + wrp_list[wrp_i].value = address; wrp_list[wrp_i].control = control; retval = cortex_a_dap_write_memap_register_u32(target, armv7a->debug_base -- cgit v1.1 From 3bd26ebb59e2932b361b40176b818174f561f901 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Fri, 7 May 2021 16:17:32 +0200 Subject: target/cortex_a: fix memory leak on watchpoints The memory allocated to hold the watchpoints is not freed at OpenOCD exit. Free the watchpoint memory at OpenOCD exit. Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6210 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- src/target/cortex_a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 9a48cc8..35f1499 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -3181,6 +3181,7 @@ static void cortex_a_deinit_target(struct target *target) dscr & ~DSCR_HALT_DBG_MODE); } + free(cortex_a->wrp_list); free(cortex_a->brp_list); arm_free_reg_cache(dpm->arm); free(dpm->dbp); -- cgit v1.1 From b8e18d292eb6a3459a018f504f2f62d6a25c26b2 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 25 Apr 2021 00:06:00 +0200 Subject: helper/jim-nvp: comply with coding style [1/2] The helper jim-nvp does not comply with OpenOCD coding style due to typedef of struct and CamelCase symbol names. While it's trivial fixing the helper and all its current use in the code, changing these APIs will potentially break a number of patches pending in gerrit. Gerrit will not trigger any alert, but the code will generate compile error after the merge. Add the compile flag "-Wno-error=deprecated-declarations" to keep as warning (not as error) the use of "deprecated" functions and types. Rename all the CamelCase symbols is lowercase and provide struct prototypes in place of the typedef. Add a DEPRECATED section to 'jim-nvp.h' where the old CamelCase symbols and the old typedef are re-declared with compile attribute 'deprecated'. With this change OpenOCD compiles, but generates warnings. The remaining changes allover OpenOCD code will be fixed in a separate patch for easier review. The patches merged later that still use the old deprecated API will compile with warnings. This will permit to identify and fix these cases. Change-Id: I786385d0f662dbb1be5be313ae42623156d68ce5 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6183 Tested-by: jenkins Reviewed-by: Marc Schink --- configure.ac | 1 + src/helper/jim-nvp.c | 106 ++++++++++----------- src/helper/jim-nvp.h | 254 +++++++++++++++++++++++++++++++++++++++------------ 3 files changed, 251 insertions(+), 110 deletions(-) diff --git a/configure.ac b/configure.ac index 2a455fa..bd2e5c4 100644 --- a/configure.ac +++ b/configure.ac @@ -758,6 +758,7 @@ AS_IF([test "x${gcc_wextra}" = "xyes"], [ GCC_WARNINGS="${GCC_WARNINGS} -Wredundant-decls" GCC_WARNINGS="${GCC_WARNINGS} -Wpointer-arith" GCC_WARNINGS="${GCC_WARNINGS} -Wundef" + GCC_WARNINGS="${GCC_WARNINGS} -Wno-error=deprecated-declarations" ]) AS_IF([test "x${gcc_werror}" = "xyes"], [ GCC_WARNINGS="${GCC_WARNINGS} -Werror" diff --git a/src/helper/jim-nvp.c b/src/helper/jim-nvp.c index 2caf18b..746af8e 100644 --- a/src/helper/jim-nvp.c +++ b/src/helper/jim-nvp.c @@ -44,59 +44,59 @@ #include #include -int Jim_GetNvp(Jim_Interp *interp, - Jim_Obj *objPtr, const Jim_Nvp *nvp_table, const Jim_Nvp **result) +int jim_get_nvp(Jim_Interp *interp, + Jim_Obj *objptr, const struct jim_nvp *nvp_table, const struct jim_nvp **result) { - Jim_Nvp *n; + struct jim_nvp *n; int e; - e = Jim_Nvp_name2value_obj(interp, nvp_table, objPtr, &n); + e = jim_nvp_name2value_obj(interp, nvp_table, objptr, &n); if (e == JIM_ERR) return e; /* Success? found? */ if (n->name) { /* remove const */ - *result = (Jim_Nvp *) n; + *result = (struct jim_nvp *)n; return JIM_OK; } else return JIM_ERR; } -Jim_Nvp *Jim_Nvp_name2value_simple(const Jim_Nvp *p, const char *name) +struct jim_nvp *jim_nvp_name2value_simple(const struct jim_nvp *p, const char *name) { while (p->name) { if (0 == strcmp(name, p->name)) break; p++; } - return (Jim_Nvp *) (p); + return (struct jim_nvp *)p; } -Jim_Nvp *Jim_Nvp_name2value_nocase_simple(const Jim_Nvp *p, const char *name) +struct jim_nvp *jim_nvp_name2value_nocase_simple(const struct jim_nvp *p, const char *name) { while (p->name) { if (0 == strcasecmp(name, p->name)) break; p++; } - return (Jim_Nvp *) (p); + return (struct jim_nvp *)p; } -int Jim_Nvp_name2value_obj(Jim_Interp *interp, const Jim_Nvp *p, Jim_Obj *o, Jim_Nvp **result) +int jim_nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result) { - return Jim_Nvp_name2value(interp, p, Jim_String(o), result); + return jim_nvp_name2value(interp, p, Jim_String(o), result); } -int Jim_Nvp_name2value(Jim_Interp *interp, const Jim_Nvp *_p, const char *name, Jim_Nvp **result) +int jim_nvp_name2value(Jim_Interp *interp, const struct jim_nvp *_p, const char *name, struct jim_nvp **result) { - const Jim_Nvp *p; + const struct jim_nvp *p; - p = Jim_Nvp_name2value_simple(_p, name); + p = jim_nvp_name2value_simple(_p, name); /* result */ if (result) - *result = (Jim_Nvp *) (p); + *result = (struct jim_nvp *)p; /* found? */ if (p->name) @@ -105,23 +105,23 @@ int Jim_Nvp_name2value(Jim_Interp *interp, const Jim_Nvp *_p, const char *name, return JIM_ERR; } -int Jim_Nvp_name2value_obj_nocase(Jim_Interp *interp, - const Jim_Nvp *p, +int jim_nvp_name2value_obj_nocase(Jim_Interp *interp, + const struct jim_nvp *p, Jim_Obj *o, - Jim_Nvp **puthere) + struct jim_nvp **puthere) { - return Jim_Nvp_name2value_nocase(interp, p, Jim_String(o), puthere); + return jim_nvp_name2value_nocase(interp, p, Jim_String(o), puthere); } -int Jim_Nvp_name2value_nocase(Jim_Interp *interp, const Jim_Nvp *_p, const char *name, - Jim_Nvp **puthere) +int jim_nvp_name2value_nocase(Jim_Interp *interp, const struct jim_nvp *_p, const char *name, + struct jim_nvp **puthere) { - const Jim_Nvp *p; + const struct jim_nvp *p; - p = Jim_Nvp_name2value_nocase_simple(_p, name); + p = jim_nvp_name2value_nocase_simple(_p, name); if (puthere) - *puthere = (Jim_Nvp *) (p); + *puthere = (struct jim_nvp *)p; /* found */ if (p->name) return JIM_OK; @@ -129,7 +129,7 @@ int Jim_Nvp_name2value_nocase(Jim_Interp *interp, const Jim_Nvp *_p, const char return JIM_ERR; } -int Jim_Nvp_value2name_obj(Jim_Interp *interp, const Jim_Nvp *p, Jim_Obj *o, Jim_Nvp **result) +int jim_nvp_value2name_obj(Jim_Interp *interp, const struct jim_nvp *p, Jim_Obj *o, struct jim_nvp **result) { int e; jim_wide w; @@ -138,27 +138,27 @@ int Jim_Nvp_value2name_obj(Jim_Interp *interp, const Jim_Nvp *p, Jim_Obj *o, Jim if (e != JIM_OK) return e; - return Jim_Nvp_value2name(interp, p, w, result); + return jim_nvp_value2name(interp, p, w, result); } -Jim_Nvp *Jim_Nvp_value2name_simple(const Jim_Nvp *p, int value) +struct jim_nvp *jim_nvp_value2name_simple(const struct jim_nvp *p, int value) { while (p->name) { if (value == p->value) break; p++; } - return (Jim_Nvp *) (p); + return (struct jim_nvp *)p; } -int Jim_Nvp_value2name(Jim_Interp *interp, const Jim_Nvp *_p, int value, Jim_Nvp **result) +int jim_nvp_value2name(Jim_Interp *interp, const struct jim_nvp *_p, int value, struct jim_nvp **result) { - const Jim_Nvp *p; + const struct jim_nvp *p; - p = Jim_Nvp_value2name_simple(_p, value); + p = jim_nvp_value2name_simple(_p, value); if (result) - *result = (Jim_Nvp *) (p); + *result = (struct jim_nvp *)p; if (p->name) return JIM_OK; @@ -166,7 +166,7 @@ int Jim_Nvp_value2name(Jim_Interp *interp, const Jim_Nvp *_p, int value, Jim_Nvp return JIM_ERR; } -int Jim_GetOpt_Setup(Jim_GetOptInfo *p, Jim_Interp *interp, int argc, Jim_Obj *const *argv) +int jim_getopt_setup(struct jim_getopt_info *p, Jim_Interp *interp, int argc, Jim_Obj *const *argv) { memset(p, 0, sizeof(*p)); p->interp = interp; @@ -176,7 +176,7 @@ int Jim_GetOpt_Setup(Jim_GetOptInfo *p, Jim_Interp *interp, int argc, Jim_Obj *c return JIM_OK; } -void Jim_GetOpt_Debug(Jim_GetOptInfo *p) +void jim_getopt_debug(struct jim_getopt_info *p) { int x; @@ -186,7 +186,7 @@ void Jim_GetOpt_Debug(Jim_GetOptInfo *p) fprintf(stderr, "-------\n"); } -int Jim_GetOpt_Obj(Jim_GetOptInfo *goi, Jim_Obj **puthere) +int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere) { Jim_Obj *o; @@ -205,13 +205,13 @@ int Jim_GetOpt_Obj(Jim_GetOptInfo *goi, Jim_Obj **puthere) return JIM_ERR; } -int Jim_GetOpt_String(Jim_GetOptInfo *goi, const char **puthere, int *len) +int jim_getopt_string(struct jim_getopt_info *goi, const char **puthere, int *len) { int r; Jim_Obj *o; const char *cp; - r = Jim_GetOpt_Obj(goi, &o); + r = jim_getopt_obj(goi, &o); if (r == JIM_OK) { cp = Jim_GetString(o, len); if (puthere) { @@ -221,7 +221,7 @@ int Jim_GetOpt_String(Jim_GetOptInfo *goi, const char **puthere, int *len) return r; } -int Jim_GetOpt_Double(Jim_GetOptInfo *goi, double *puthere) +int jim_getopt_double(struct jim_getopt_info *goi, double *puthere) { int r; Jim_Obj *o; @@ -230,7 +230,7 @@ int Jim_GetOpt_Double(Jim_GetOptInfo *goi, double *puthere) if (puthere == NULL) puthere = &_safe; - r = Jim_GetOpt_Obj(goi, &o); + r = jim_getopt_obj(goi, &o); if (r == JIM_OK) { r = Jim_GetDouble(goi->interp, o, puthere); if (r != JIM_OK) @@ -239,7 +239,7 @@ int Jim_GetOpt_Double(Jim_GetOptInfo *goi, double *puthere) return r; } -int Jim_GetOpt_Wide(Jim_GetOptInfo *goi, jim_wide *puthere) +int jim_getopt_wide(struct jim_getopt_info *goi, jim_wide *puthere) { int r; Jim_Obj *o; @@ -248,37 +248,37 @@ int Jim_GetOpt_Wide(Jim_GetOptInfo *goi, jim_wide *puthere) if (puthere == NULL) puthere = &_safe; - r = Jim_GetOpt_Obj(goi, &o); + r = jim_getopt_obj(goi, &o); if (r == JIM_OK) r = Jim_GetWide(goi->interp, o, puthere); return r; } -int Jim_GetOpt_Nvp(Jim_GetOptInfo *goi, const Jim_Nvp *nvp, Jim_Nvp **puthere) +int jim_getopt_nvp(struct jim_getopt_info *goi, const struct jim_nvp *nvp, struct jim_nvp **puthere) { - Jim_Nvp *_safe; + struct jim_nvp *_safe; Jim_Obj *o; int e; if (puthere == NULL) puthere = &_safe; - e = Jim_GetOpt_Obj(goi, &o); + e = jim_getopt_obj(goi, &o); if (e == JIM_OK) - e = Jim_Nvp_name2value_obj(goi->interp, nvp, o, puthere); + e = jim_nvp_name2value_obj(goi->interp, nvp, o, puthere); return e; } -void Jim_GetOpt_NvpUnknown(Jim_GetOptInfo *goi, const Jim_Nvp *nvptable, int hadprefix) +void jim_getopt_nvp_unknown(struct jim_getopt_info *goi, const struct jim_nvp *nvptable, int hadprefix) { if (hadprefix) - Jim_SetResult_NvpUnknown(goi->interp, goi->argv[-2], goi->argv[-1], nvptable); + jim_set_result_nvp_unknown(goi->interp, goi->argv[-2], goi->argv[-1], nvptable); else - Jim_SetResult_NvpUnknown(goi->interp, NULL, goi->argv[-1], nvptable); + jim_set_result_nvp_unknown(goi->interp, NULL, goi->argv[-1], nvptable); } -int Jim_GetOpt_Enum(Jim_GetOptInfo *goi, const char *const *lookup, int *puthere) +int jim_getopt_enum(struct jim_getopt_info *goi, const char *const *lookup, int *puthere) { int _safe; Jim_Obj *o; @@ -286,14 +286,14 @@ int Jim_GetOpt_Enum(Jim_GetOptInfo *goi, const char *const *lookup, int *puthere if (puthere == NULL) puthere = &_safe; - e = Jim_GetOpt_Obj(goi, &o); + e = jim_getopt_obj(goi, &o); if (e == JIM_OK) e = Jim_GetEnum(goi->interp, o, lookup, puthere, "option", JIM_ERRMSG); return e; } -void Jim_SetResult_NvpUnknown(Jim_Interp *interp, - Jim_Obj *param_name, Jim_Obj *param_value, const Jim_Nvp *nvp) +void jim_set_result_nvp_unknown(Jim_Interp *interp, + Jim_Obj *param_name, Jim_Obj *param_value, const struct jim_nvp *nvp) { if (param_name) Jim_SetResultFormatted(interp, @@ -318,7 +318,7 @@ void Jim_SetResult_NvpUnknown(Jim_Interp *interp, } } -const char *Jim_Debug_ArgvString(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +const char *jim_debug_argv_string(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { static Jim_Obj *debug_string_obj; diff --git a/src/helper/jim-nvp.h b/src/helper/jim-nvp.h index 4c4dc8f..00e4af9 100644 --- a/src/helper/jim-nvp.h +++ b/src/helper/jim-nvp.h @@ -62,7 +62,7 @@ * * Example: * \code - * const Jim_Nvp yn[] = { + * const struct jim_nvp yn[] = { * { "yes", 1 }, * { "no" , 0 }, * { "yep", 1 }, @@ -70,60 +70,60 @@ * { NULL, -1 }, * }; * - * Jim_Nvp *result - * e = Jim_Nvp_name2value(interp, yn, "y", &result); + * struct jim_nvp *result + * e = jim_nvp_name2value(interp, yn, "y", &result); * returns &yn[0]; - * e = Jim_Nvp_name2value(interp, yn, "n", &result); + * e = jim_nvp_name2value(interp, yn, "n", &result); * returns &yn[1]; - * e = Jim_Nvp_name2value(interp, yn, "Blah", &result); + * e = jim_nvp_name2value(interp, yn, "Blah", &result); * returns &yn[4]; * \endcode * * During the number2name operation, the first matching value is returned. */ -typedef struct { +struct jim_nvp { const char *name; int value; -} Jim_Nvp; +}; -int Jim_GetNvp(Jim_Interp *interp, - Jim_Obj *objPtr, - const Jim_Nvp *nvp_table, - const Jim_Nvp **result); +int jim_get_nvp(Jim_Interp *interp, + Jim_Obj *objptr, + const struct jim_nvp *nvp_table, + const struct jim_nvp **result); /* Name Value Pairs Operations */ -Jim_Nvp *Jim_Nvp_name2value_simple(const Jim_Nvp *nvp_table, const char *name); -Jim_Nvp *Jim_Nvp_name2value_nocase_simple(const Jim_Nvp *nvp_table, const char *name); -Jim_Nvp *Jim_Nvp_value2name_simple(const Jim_Nvp *nvp_table, int v); +struct jim_nvp *jim_nvp_name2value_simple(const struct jim_nvp *nvp_table, const char *name); +struct jim_nvp *jim_nvp_name2value_nocase_simple(const struct jim_nvp *nvp_table, const char *name); +struct jim_nvp *jim_nvp_value2name_simple(const struct jim_nvp *nvp_table, int v); -int Jim_Nvp_name2value(Jim_Interp *interp, - const Jim_Nvp *nvp_table, +int jim_nvp_name2value(Jim_Interp *interp, + const struct jim_nvp *nvp_table, const char *name, - Jim_Nvp **result); -int Jim_Nvp_name2value_nocase(Jim_Interp *interp, - const Jim_Nvp *nvp_table, + struct jim_nvp **result); +int jim_nvp_name2value_nocase(Jim_Interp *interp, + const struct jim_nvp *nvp_table, const char *name, - Jim_Nvp **result); -int Jim_Nvp_value2name(Jim_Interp *interp, const Jim_Nvp *nvp_table, int value, Jim_Nvp **result); + struct jim_nvp **result); +int jim_nvp_value2name(Jim_Interp *interp, const struct jim_nvp *nvp_table, int value, struct jim_nvp **result); -int Jim_Nvp_name2value_obj(Jim_Interp *interp, - const Jim_Nvp *nvp_table, +int jim_nvp_name2value_obj(Jim_Interp *interp, + const struct jim_nvp *nvp_table, Jim_Obj *name_obj, - Jim_Nvp **result); -int Jim_Nvp_name2value_obj_nocase(Jim_Interp *interp, - const Jim_Nvp *nvp_table, + struct jim_nvp **result); +int jim_nvp_name2value_obj_nocase(Jim_Interp *interp, + const struct jim_nvp *nvp_table, Jim_Obj *name_obj, - Jim_Nvp **result); -int Jim_Nvp_value2name_obj(Jim_Interp *interp, - const Jim_Nvp *nvp_table, + struct jim_nvp **result); +int jim_nvp_value2name_obj(Jim_Interp *interp, + const struct jim_nvp *nvp_table, Jim_Obj *value_obj, - Jim_Nvp **result); + struct jim_nvp **result); /** prints a nice 'unknown' parameter error message to the 'result' */ -void Jim_SetResult_NvpUnknown(Jim_Interp *interp, +void jim_set_result_nvp_unknown(Jim_Interp *interp, Jim_Obj *param_name, Jim_Obj *param_value, - const Jim_Nvp *nvp_table); + const struct jim_nvp *nvp_table); /** Debug: convert argc/argv into a printable string for printf() debug * @@ -142,7 +142,7 @@ void Jim_SetResult_NvpUnknown(Jim_Interp *interp, * fclose(fp); * \endcode */ -const char *Jim_Debug_ArgvString(Jim_Interp *interp, int argc, Jim_Obj *const *argv); +const char *jim_debug_argv_string(Jim_Interp *interp, int argc, Jim_Obj *const *argv); /** A TCL -ish GetOpt like code. @@ -157,25 +157,25 @@ const char *Jim_Debug_ArgvString(Jim_Interp *interp, int argc, Jim_Obj *const *a * Only supports tcl type options, like "-foo 123" */ -typedef struct jim_getopt { +struct jim_getopt_info { Jim_Interp *interp; int argc; Jim_Obj *const *argv; int isconfigure; /* non-zero if configure */ -} Jim_GetOptInfo; +}; /** GetOpt - how to. * * Example (short and incomplete): * \code - * Jim_GetOptInfo goi; + * struct jim_getopt_info goi; * - * Jim_GetOpt_Setup(&goi, interp, argc, argv); + * jim_getopt_setup(&goi, interp, argc, argv); * * while (goi.argc) { - * e = Jim_GetOpt_Nvp(&goi, nvp_options, &n); + * e = jim_getopt_nvp(&goi, nvp_options, &n); * if (e != JIM_OK) { - * Jim_GetOpt_NvpUnknown(&goi, nvp_options, 0); + * jim_getopt_nvp_unknown(&goi, nvp_options, 0); * return e; * } * @@ -187,16 +187,16 @@ typedef struct jim_getopt { * if (goi.argc < 1) { * .. not enough args error .. * } - * Jim_GetOpt_String(&goi, &cp, NULL); + * jim_getopt_string(&goi, &cp, NULL); * printf("FIRSTNAME: %s\n", cp); * case AGE: - * Jim_GetOpt_Wide(&goi, &w); + * jim_getopt_wide(&goi, &w); * printf("AGE: %d\n", (int)(w)); * break; * case POLITICS: - * e = Jim_GetOpt_Nvp(&goi, nvp_politics, &n); + * e = jim_getopt_nvp(&goi, nvp_politics, &n); * if (e != JIM_OK) { - * Jim_GetOpt_NvpUnknown(&goi, nvp_politics, 1); + * jim_getopt_nvp_unknown(&goi, nvp_politics, 1); * return e; * } * } @@ -214,13 +214,13 @@ typedef struct jim_getopt { * \param argv - argv (will be copied) * * \code - * Jim_GetOptInfo goi; + * struct jim_getopt_info goi; * * Jim_GetOptSetup(&goi, interp, argc, argv); * \endcode */ -int Jim_GetOpt_Setup(Jim_GetOptInfo *goi, +int jim_getopt_setup(struct jim_getopt_info *goi, Jim_Interp *interp, int argc, Jim_Obj *const *argv); @@ -229,7 +229,7 @@ int Jim_GetOpt_Setup(Jim_GetOptInfo *goi, /** Debug - Dump parameters to stderr * \param goi - current parameters */ -void Jim_GetOpt_Debug(Jim_GetOptInfo *goi); +void jim_getopt_debug(struct jim_getopt_info *goi); /** Remove argv[0] from the list. * @@ -237,7 +237,7 @@ void Jim_GetOpt_Debug(Jim_GetOptInfo *goi); * \param puthere - where param is put * */ -int Jim_GetOpt_Obj(Jim_GetOptInfo *goi, Jim_Obj **puthere); +int jim_getopt_obj(struct jim_getopt_info *goi, Jim_Obj **puthere); /** Remove argv[0] as string. * @@ -245,7 +245,7 @@ int Jim_GetOpt_Obj(Jim_GetOptInfo *goi, Jim_Obj **puthere); * \param puthere - where param is put * \param len - return its length */ -int Jim_GetOpt_String(Jim_GetOptInfo *goi, const char **puthere, int *len); +int jim_getopt_string(struct jim_getopt_info *goi, const char **puthere, int *len); /** Remove argv[0] as double. * @@ -253,14 +253,14 @@ int Jim_GetOpt_String(Jim_GetOptInfo *goi, const char **puthere, int *len); * \param puthere - where param is put. * */ -int Jim_GetOpt_Double(Jim_GetOptInfo *goi, double *puthere); +int jim_getopt_double(struct jim_getopt_info *goi, double *puthere); /** Remove argv[0] as wide. * * \param goi - get opt info * \param puthere - where param is put. */ -int Jim_GetOpt_Wide(Jim_GetOptInfo *goi, jim_wide *puthere); +int jim_getopt_wide(struct jim_getopt_info *goi, jim_wide *puthere); /** Remove argv[0] as NVP. * @@ -269,7 +269,7 @@ int Jim_GetOpt_Wide(Jim_GetOptInfo *goi, jim_wide *puthere); * \param puthere - where param is put. * */ -int Jim_GetOpt_Nvp(Jim_GetOptInfo *goi, const Jim_Nvp *lookup, Jim_Nvp **puthere); +int jim_getopt_nvp(struct jim_getopt_info *goi, const struct jim_nvp *lookup, struct jim_nvp **puthere); /** Create an appropriate error message for an NVP. * @@ -289,20 +289,20 @@ int Jim_GetOpt_Nvp(Jim_GetOptInfo *goi, const Jim_Nvp *lookup, Jim_Nvp **puthere * * while (goi.argc) { * // Get the next option - * e = Jim_GetOpt_Nvp(&goi, cmd_options, &n); + * e = jim_getopt_nvp(&goi, cmd_options, &n); * if (e != JIM_OK) { * // option was not recognized * // pass 'hadprefix = 0' because there is no prefix - * Jim_GetOpt_NvpUnknown(&goi, cmd_options, 0); + * jim_getopt_nvp_unknown(&goi, cmd_options, 0); * return e; * } * * switch (n->value) { * case OPT_SEX: * // handle: --sex male | female | lots | needmore - * e = Jim_GetOpt_Nvp(&goi, &nvp_sex, &n); + * e = jim_getopt_nvp(&goi, &nvp_sex, &n); * if (e != JIM_OK) { - * Jim_GetOpt_NvpUnknown(&ogi, nvp_sex, 1); + * jim_getopt_nvp_unknown(&ogi, nvp_sex, 1); * return e; * } * printf("Code: (%d) is %s\n", n->value, n->name); @@ -314,7 +314,7 @@ int Jim_GetOpt_Nvp(Jim_GetOptInfo *goi, const Jim_Nvp *lookup, Jim_Nvp **puthere * \endcode * */ -void Jim_GetOpt_NvpUnknown(Jim_GetOptInfo *goi, const Jim_Nvp *lookup, int hadprefix); +void jim_getopt_nvp_unknown(struct jim_getopt_info *goi, const struct jim_nvp *lookup, int hadprefix); /** Remove argv[0] as Enum @@ -324,6 +324,146 @@ void Jim_GetOpt_NvpUnknown(Jim_GetOptInfo *goi, const Jim_Nvp *lookup, int hadpr * \param puthere - where param is put. * */ -int Jim_GetOpt_Enum(Jim_GetOptInfo *goi, const char *const *lookup, int *puthere); +int jim_getopt_enum(struct jim_getopt_info *goi, const char *const *lookup, int *puthere); + +/* + * DEPRECATED API + * Do not use these API anymore, as they do not comply with OpenOCD coding style + * They are listed here to avoid breaking build after merge of patches already queued in gerrit + */ + +static inline __attribute__ ((deprecated)) +const char *Jim_Debug_ArgvString(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +{ + return jim_debug_argv_string(interp, argc, argv); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetNvp(Jim_Interp *interp, Jim_Obj *objptr, const struct jim_nvp *nvp_table, const struct jim_nvp **result) +{ + return jim_get_nvp(interp, objptr, nvp_table, result); +} + +static inline __attribute__ ((deprecated)) +void Jim_GetOpt_Debug(struct jim_getopt_info *goi) +{ + jim_getopt_debug(goi); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Double(struct jim_getopt_info *goi, double *puthere) +{ + return jim_getopt_double(goi, puthere); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Enum(struct jim_getopt_info *goi, const char *const *lookup, int *puthere) +{ + return jim_getopt_enum(goi, lookup, puthere); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Nvp(struct jim_getopt_info *goi, const struct jim_nvp *lookup, struct jim_nvp **puthere) +{ + return jim_getopt_nvp(goi, lookup, puthere); +} + +static inline __attribute__ ((deprecated)) +void Jim_GetOpt_NvpUnknown(struct jim_getopt_info *goi, const struct jim_nvp *lookup, int hadprefix) +{ + jim_getopt_nvp_unknown(goi, lookup, hadprefix); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Obj(struct jim_getopt_info *goi, Jim_Obj **puthere) +{ + return jim_getopt_obj(goi, puthere); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Setup(struct jim_getopt_info *goi, Jim_Interp *interp, int argc, Jim_Obj *const *argv) +{ + return jim_getopt_setup(goi, interp, argc, argv); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_String(struct jim_getopt_info *goi, const char **puthere, int *len) +{ + return jim_getopt_string(goi, puthere, len); +} + +static inline __attribute__ ((deprecated)) +int Jim_GetOpt_Wide(struct jim_getopt_info *goi, jim_wide *puthere) +{ + return jim_getopt_wide(goi, puthere); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_name2value(Jim_Interp *interp, const struct jim_nvp *nvp_table, const char *name, struct jim_nvp **result) +{ + return jim_nvp_name2value(interp, nvp_table, name, result); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_name2value_nocase(Jim_Interp *interp, const struct jim_nvp *nvp_table, const char *name, + struct jim_nvp **result) +{ + return jim_nvp_name2value_nocase(interp, nvp_table, name, result); +} + +static inline __attribute__ ((deprecated)) +struct jim_nvp *Jim_Nvp_name2value_nocase_simple(const struct jim_nvp *nvp_table, const char *name) +{ + return jim_nvp_name2value_nocase_simple(nvp_table, name); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_name2value_obj(Jim_Interp *interp, const struct jim_nvp *nvp_table, Jim_Obj *name_obj, + struct jim_nvp **result) +{ + return jim_nvp_name2value_obj(interp, nvp_table, name_obj, result); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_name2value_obj_nocase(Jim_Interp *interp, const struct jim_nvp *nvp_table, Jim_Obj *name_obj, + struct jim_nvp **result) +{ + return jim_nvp_name2value_obj_nocase(interp, nvp_table, name_obj, result); +} + +static inline __attribute__ ((deprecated)) +struct jim_nvp *Jim_Nvp_name2value_simple(const struct jim_nvp *nvp_table, const char *name) +{ + return jim_nvp_name2value_simple(nvp_table, name); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_value2name(Jim_Interp *interp, const struct jim_nvp *nvp_table, int value, struct jim_nvp **result) +{ + return jim_nvp_value2name(interp, nvp_table, value, result); +} + +static inline __attribute__ ((deprecated)) +int Jim_Nvp_value2name_obj(Jim_Interp *interp, const struct jim_nvp *nvp_table, Jim_Obj *value_obj, + struct jim_nvp **result) +{ + return jim_nvp_value2name_obj(interp, nvp_table, value_obj, result); +} + +static inline __attribute__ ((deprecated)) +struct jim_nvp *Jim_Nvp_value2name_simple(const struct jim_nvp *nvp_table, int v) +{ + return jim_nvp_value2name_simple(nvp_table, v); +} + +static inline __attribute__ ((deprecated)) +void Jim_SetResult_NvpUnknown(Jim_Interp *interp, Jim_Obj *param_name, Jim_Obj *param_value, + const struct jim_nvp *nvp_table) +{ + jim_set_result_nvp_unknown(interp, param_name, param_value, nvp_table); +} + +typedef struct jim_getopt_info Jim_GetOptInfo __attribute__ ((deprecated)); +typedef struct jim_nvp Jim_Nvp __attribute__ ((deprecated)); #endif /* OPENOCD_HELPER_JIM_NVP_H */ -- cgit v1.1 From 9e7b31479ba7100f41a5b88b32571cf765cdb3ee Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Sun, 25 Apr 2021 00:48:14 +0200 Subject: helper/jim-nvp: comply with coding style [2/2] With the API fixed to comply with OpenOCD coding style, fix all the references in the code. Patch generated automatically with the script below. The list is in reverse order to replace a common prefix after the replacement of the symbols with the same prefix. %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- (cat << EOF Jim_SetResult_NvpUnknown jim_set_result_nvp_unknown Jim_Nvp_value2name_simple jim_nvp_value2name_simple Jim_Nvp_value2name_obj jim_nvp_value2name_obj Jim_Nvp_value2name jim_nvp_value2name Jim_Nvp_name2value_simple jim_nvp_name2value_simple Jim_Nvp_name2value_obj_nocase jim_nvp_name2value_obj_nocase Jim_Nvp_name2value_obj jim_nvp_name2value_obj Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple Jim_Nvp_name2value_nocase jim_nvp_name2value_nocase Jim_Nvp_name2value jim_nvp_name2value Jim_Nvp struct jim_nvp Jim_GetOpt_Wide jim_getopt_wide Jim_GetOpt_String jim_getopt_string Jim_GetOpt_Setup jim_getopt_setup Jim_GetOpt_Obj jim_getopt_obj Jim_GetOpt_NvpUnknown jim_getopt_nvp_unknown Jim_GetOpt_Nvp jim_getopt_nvp Jim_GetOpt_Enum jim_getopt_enum Jim_GetOpt_Double jim_getopt_double Jim_GetOpt_Debug jim_getopt_debug Jim_GetOptInfo struct jim_getopt_info Jim_GetNvp jim_get_nvp Jim_Debug_ArgvString jim_debug_argv_string EOF ) | while read a b; do sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? ) done %<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<--- Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6184 Reviewed-by: Marc Schink Tested-by: jenkins --- src/jtag/adapter.c | 4 +- src/jtag/aice/aice_transport.c | 30 ++++----- src/jtag/drivers/ftdi.c | 8 +-- src/jtag/hla/hla_tcl.c | 24 +++---- src/jtag/tcl.c | 72 ++++++++++---------- src/rtos/rtos.c | 4 +- src/rtos/rtos.h | 2 +- src/target/aarch64.c | 20 +++--- src/target/arc_cmd.c | 82 +++++++++++------------ src/target/arm_adi_v5.c | 20 +++--- src/target/arm_adi_v5.h | 4 +- src/target/arm_cti.c | 10 +-- src/target/arm_dap.c | 20 +++--- src/target/arm_tpiu_swo.c | 70 +++++++++---------- src/target/armv8.c | 10 +-- src/target/cortex_a.c | 16 ++--- src/target/cortex_m.c | 8 +-- src/target/nds32_cmd.c | 42 ++++++------ src/target/stm8.c | 34 +++++----- src/target/target.c | 148 ++++++++++++++++++++--------------------- src/target/target_type.h | 4 +- 21 files changed, 316 insertions(+), 316 deletions(-) diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index 0dcb78f..03bb1a9 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -51,8 +51,8 @@ const char * const jtag_only[] = { "jtag", NULL }; static int jim_adapter_name(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); /* return the name of the interface */ /* TCL code might need to know the exact type... */ diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c index c02a42f..322d8ae 100644 --- a/src/jtag/aice/aice_transport.c +++ b/src/jtag/aice/aice_transport.c @@ -30,11 +30,11 @@ #include /* */ -static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, +static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, struct jtag_tap *pTap) { jim_wide w; - int e = Jim_GetOpt_Wide(goi, &w); + int e = jim_getopt_wide(goi, &w); if (e != JIM_OK) { Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", n->name); @@ -63,14 +63,14 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, #define NTAP_OPT_EXPECTED_ID 0 /* */ -static int jim_aice_newtap_cmd(Jim_GetOptInfo *goi) +static int jim_aice_newtap_cmd(struct jim_getopt_info *goi) { struct jtag_tap *pTap; int x; int e; - Jim_Nvp *n; + struct jim_nvp *n; char *cp; - const Jim_Nvp opts[] = { + const struct jim_nvp opts[] = { {.name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID}, {.name = NULL, .value = -1}, }; @@ -92,10 +92,10 @@ static int jim_aice_newtap_cmd(Jim_GetOptInfo *goi) } const char *tmp; - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->chip = strdup(tmp); - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->tapname = strdup(tmp); /* name + dot + name + null */ @@ -108,9 +108,9 @@ static int jim_aice_newtap_cmd(Jim_GetOptInfo *goi) pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc); while (goi->argc) { - e = Jim_GetOpt_Nvp(goi, opts, &n); + e = jim_getopt_nvp(goi, opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, opts, 0); + jim_getopt_nvp_unknown(goi, opts, 0); free(cp); free(pTap); return e; @@ -138,8 +138,8 @@ static int jim_aice_newtap_cmd(Jim_GetOptInfo *goi) /* */ static int jim_aice_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); return jim_aice_newtap_cmd(&goi); } @@ -246,8 +246,8 @@ static int aice_init_reset(struct command_context *cmd_ctx) static int jim_aice_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { int e = ERROR_OK; - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc != 0) { Jim_WrongNumArgs(goi.interp, 1, goi.argv - 1, "(no params)"); return JIM_ERR; @@ -265,8 +265,8 @@ static int jim_aice_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj * const static int jim_aice_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc != 0) { Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters"); return JIM_ERR; diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c index 210d0f7..25406a4 100644 --- a/src/jtag/drivers/ftdi.c +++ b/src/jtag/drivers/ftdi.c @@ -926,22 +926,22 @@ COMMAND_HANDLER(ftdi_handle_vid_pid_command) COMMAND_HANDLER(ftdi_handle_tdo_sample_edge_command) { - Jim_Nvp *n; - static const Jim_Nvp nvp_ftdi_jtag_modes[] = { + struct jim_nvp *n; + static const struct jim_nvp nvp_ftdi_jtag_modes[] = { { .name = "rising", .value = JTAG_MODE }, { .name = "falling", .value = JTAG_MODE_ALT }, { .name = NULL, .value = -1 }, }; if (CMD_ARGC > 0) { - n = Jim_Nvp_name2value_simple(nvp_ftdi_jtag_modes, CMD_ARGV[0]); + n = jim_nvp_name2value_simple(nvp_ftdi_jtag_modes, CMD_ARGV[0]); if (n->name == NULL) return ERROR_COMMAND_SYNTAX_ERROR; ftdi_jtag_mode = n->value; } - n = Jim_Nvp_value2name_simple(nvp_ftdi_jtag_modes, ftdi_jtag_mode); + n = jim_nvp_value2name_simple(nvp_ftdi_jtag_modes, ftdi_jtag_mode); command_print(CMD, "ftdi samples TDO on %s edge of TCK", n->name); return ERROR_OK; diff --git a/src/jtag/hla/hla_tcl.c b/src/jtag/hla/hla_tcl.c index 73f78fc..2998498 100644 --- a/src/jtag/hla/hla_tcl.c +++ b/src/jtag/hla/hla_tcl.c @@ -28,11 +28,11 @@ #include #include -static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, +static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, struct jtag_tap *pTap) { jim_wide w; - int e = Jim_GetOpt_Wide(goi, &w); + int e = jim_getopt_wide(goi, &w); if (e != JIM_OK) { Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", n->name); @@ -60,14 +60,14 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, #define NTAP_OPT_EXPECTED_ID 5 #define NTAP_OPT_VERSION 6 -static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi) +static int jim_hl_newtap_cmd(struct jim_getopt_info *goi) { struct jtag_tap *pTap; int x; int e; - Jim_Nvp *n; + struct jim_nvp *n; char *cp; - const Jim_Nvp opts[] = { + const struct jim_nvp opts[] = { { .name = "-irlen", .value = NTAP_OPT_IRLEN }, { .name = "-irmask", .value = NTAP_OPT_IRMASK }, { .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE }, @@ -95,10 +95,10 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi) } const char *tmp; - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->chip = strdup(tmp); - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->tapname = strdup(tmp); /* name + dot + name + null */ @@ -111,9 +111,9 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi) pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc); while (goi->argc) { - e = Jim_GetOpt_Nvp(goi, opts, &n); + e = jim_getopt_nvp(goi, opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, opts, 0); + jim_getopt_nvp_unknown(goi, opts, 0); free(cp); free(pTap); return e; @@ -132,7 +132,7 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi) case NTAP_OPT_IRMASK: case NTAP_OPT_IRCAPTURE: /* dummy read to ignore the next argument */ - Jim_GetOpt_Wide(goi, NULL); + jim_getopt_wide(goi, NULL); break; } /* switch (n->value) */ } /* while (goi->argc) */ @@ -146,7 +146,7 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi) int jim_hl_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); return jim_hl_newtap_cmd(&goi); } diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 5dc2f14..970bd37 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -49,7 +49,7 @@ * Holds support for accessing JTAG-specific mechanisms from TCl scripts. */ -static const Jim_Nvp nvp_jtag_tap_event[] = { +static const struct jim_nvp nvp_jtag_tap_event[] = { { .value = JTAG_TRST_ASSERTED, .name = "post-reset" }, { .value = JTAG_TAP_EVENT_SETUP, .name = "setup" }, { .value = JTAG_TAP_EVENT_ENABLE, .name = "tap-enable" }, @@ -310,24 +310,24 @@ enum jtag_tap_cfg_param { JCFG_IDCODE, }; -static Jim_Nvp nvp_config_opts[] = { +static struct jim_nvp nvp_config_opts[] = { { .name = "-event", .value = JCFG_EVENT }, { .name = "-idcode", .value = JCFG_IDCODE }, { .name = NULL, .value = -1 } }; -static int jtag_tap_configure_event(Jim_GetOptInfo *goi, struct jtag_tap *tap) +static int jtag_tap_configure_event(struct jim_getopt_info *goi, struct jtag_tap *tap) { if (goi->argc == 0) { Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-event ..."); return JIM_ERR; } - Jim_Nvp *n; - int e = Jim_GetOpt_Nvp(goi, nvp_jtag_tap_event, &n); + struct jim_nvp *n; + int e = jim_getopt_nvp(goi, nvp_jtag_tap_event, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_jtag_tap_event, 1); + jim_getopt_nvp_unknown(goi, nvp_jtag_tap_event, 1); return e; } @@ -369,7 +369,7 @@ static int jtag_tap_configure_event(Jim_GetOptInfo *goi, struct jtag_tap *tap) jteap->event = n->value; Jim_Obj *o; - Jim_GetOpt_Obj(goi, &o); + jim_getopt_obj(goi, &o); jteap->body = Jim_DuplicateObj(goi->interp, o); Jim_IncrRefCount(jteap->body); @@ -386,16 +386,16 @@ static int jtag_tap_configure_event(Jim_GetOptInfo *goi, struct jtag_tap *tap) return JIM_OK; } -static int jtag_tap_configure_cmd(Jim_GetOptInfo *goi, struct jtag_tap *tap) +static int jtag_tap_configure_cmd(struct jim_getopt_info *goi, struct jtag_tap *tap) { /* parse config or cget options */ while (goi->argc > 0) { Jim_SetEmptyResult(goi->interp); - Jim_Nvp *n; - int e = Jim_GetOpt_Nvp(goi, nvp_config_opts, &n); + struct jim_nvp *n; + int e = jim_getopt_nvp(goi, nvp_config_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_config_opts, 0); + jim_getopt_nvp_unknown(goi, nvp_config_opts, 0); return e; } @@ -439,11 +439,11 @@ static int is_bad_irval(int ir_length, jim_wide w) return (w & v) != 0; } -static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, +static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi, struct jtag_tap *pTap) { jim_wide w; - int e = Jim_GetOpt_Wide(goi, &w); + int e = jim_getopt_wide(goi, &w); if (e != JIM_OK) { Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", n->name); return e; @@ -470,11 +470,11 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, #define NTAP_OPT_EXPECTED_ID 5 #define NTAP_OPT_VERSION 6 -static int jim_newtap_ir_param(Jim_Nvp *n, Jim_GetOptInfo *goi, +static int jim_newtap_ir_param(struct jim_nvp *n, struct jim_getopt_info *goi, struct jtag_tap *pTap) { jim_wide w; - int e = Jim_GetOpt_Wide(goi, &w); + int e = jim_getopt_wide(goi, &w); if (e != JIM_OK) { Jim_SetResultFormatted(goi->interp, "option: %s bad parameter", n->name); @@ -516,14 +516,14 @@ static int jim_newtap_ir_param(Jim_Nvp *n, Jim_GetOptInfo *goi, return JIM_OK; } -static int jim_newtap_cmd(Jim_GetOptInfo *goi) +static int jim_newtap_cmd(struct jim_getopt_info *goi) { struct jtag_tap *pTap; int x; int e; - Jim_Nvp *n; + struct jim_nvp *n; char *cp; - const Jim_Nvp opts[] = { + const struct jim_nvp opts[] = { { .name = "-irlen", .value = NTAP_OPT_IRLEN }, { .name = "-irmask", .value = NTAP_OPT_IRMASK }, { .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE }, @@ -550,10 +550,10 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi) } const char *tmp; - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->chip = strdup(tmp); - Jim_GetOpt_String(goi, &tmp, NULL); + jim_getopt_string(goi, &tmp, NULL); pTap->tapname = strdup(tmp); /* name + dot + name + null */ @@ -580,9 +580,9 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi) pTap->ir_capture_value = 0x01; while (goi->argc) { - e = Jim_GetOpt_Nvp(goi, opts, &n); + e = jim_getopt_nvp(goi, opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, opts, 0); + jim_getopt_nvp_unknown(goi, opts, 0); free(cp); free(pTap); return e; @@ -644,7 +644,7 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e) if (jteap->event != e) continue; - Jim_Nvp *nvp = Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e); + struct jim_nvp *nvp = jim_nvp_value2name_simple(nvp_jtag_tap_event, e); LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s", tap->dotted_name, e, nvp->name, Jim_GetString(jteap->body, NULL)); @@ -678,8 +678,8 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e) static int jim_jtag_arp_init(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); if (goi.argc != 0) { Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)"); return JIM_ERR; @@ -697,8 +697,8 @@ static int jim_jtag_arp_init(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_jtag_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { int e = ERROR_OK; - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); if (goi.argc != 0) { Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)"); return JIM_ERR; @@ -719,8 +719,8 @@ static int jim_jtag_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj *const int jim_jtag_newtap(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); return jim_newtap_cmd(&goi); } @@ -759,8 +759,8 @@ int jim_jtag_tap_enabler(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { struct command *c = jim_to_command(interp); const char *cmd_name = c->name; - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); if (goi.argc != 1) { Jim_SetResultFormatted(goi.interp, "usage: %s ", cmd_name); return JIM_ERR; @@ -797,8 +797,8 @@ int jim_jtag_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { struct command *c = jim_to_command(interp); const char *cmd_name = c->name; - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); goi.isconfigure = !strcmp(cmd_name, "configure"); if (goi.argc < 2 + goi.isconfigure) { Jim_WrongNumArgs(goi.interp, 0, NULL, @@ -809,7 +809,7 @@ int jim_jtag_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv) struct jtag_tap *t; Jim_Obj *o; - Jim_GetOpt_Obj(&goi, &o); + jim_getopt_obj(&goi, &o); t = jtag_tap_by_jim_obj(goi.interp, o); if (t == NULL) return JIM_ERR; @@ -819,8 +819,8 @@ int jim_jtag_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_jtag_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc-1, argv + 1); if (goi.argc != 0) { Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters"); return JIM_ERR; diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c index fdb3862..0374e9b 100644 --- a/src/rtos/rtos.c +++ b/src/rtos/rtos.c @@ -122,7 +122,7 @@ static int os_alloc_create(struct target *target, struct rtos_type *ostype) return ret; } -int rtos_create(Jim_GetOptInfo *goi, struct target *target) +int rtos_create(struct jim_getopt_info *goi, struct target *target) { int x; const char *cp; @@ -136,7 +136,7 @@ int rtos_create(Jim_GetOptInfo *goi, struct target *target) os_free(target); - e = Jim_GetOpt_String(goi, &cp, NULL); + e = jim_getopt_string(goi, &cp, NULL); if (e != JIM_OK) return e; diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h index b3fd01f..20f7de7 100644 --- a/src/rtos/rtos.h +++ b/src/rtos/rtos.h @@ -110,7 +110,7 @@ struct rtos_register_stacking { #define GDB_THREAD_PACKET_NOT_CONSUMED (-40) -int rtos_create(Jim_GetOptInfo *goi, struct target *target); +int rtos_create(struct jim_getopt_info *goi, struct target *target); void rtos_destroy(struct target *target); int rtos_set_reg(struct connection *connection, int reg_num, uint8_t *reg_value); diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 612924f..ef00fd1 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -2785,15 +2785,15 @@ enum aarch64_cfg_param { CFG_CTI, }; -static const Jim_Nvp nvp_config_opts[] = { +static const struct jim_nvp nvp_config_opts[] = { { .name = "-cti", .value = CFG_CTI }, { .name = NULL, .value = -1 } }; -static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi) +static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *goi) { struct aarch64_private_config *pc; - Jim_Nvp *n; + struct jim_nvp *n; int e; pc = (struct aarch64_private_config *)target->private_config; @@ -2824,12 +2824,12 @@ static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi) Jim_SetEmptyResult(goi->interp); /* check first if topmost item is for us */ - e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts, + e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts, goi->argv[0], &n); if (e != JIM_OK) return JIM_CONTINUE; - e = Jim_GetOpt_Obj(goi, NULL); + e = jim_getopt_obj(goi, NULL); if (e != JIM_OK) return e; @@ -2838,7 +2838,7 @@ static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi) if (goi->isconfigure) { Jim_Obj *o_cti; struct arm_cti *cti; - e = Jim_GetOpt_Obj(goi, &o_cti); + e = jim_getopt_obj(goi, &o_cti); if (e != JIM_OK) return e; cti = cti_instance_by_jim_obj(goi->interp, o_cti); @@ -2930,15 +2930,15 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command) struct target *target = get_current_target(CMD_CTX); struct aarch64_common *aarch64 = target_to_aarch64(target); - static const Jim_Nvp nvp_maskisr_modes[] = { + static const struct jim_nvp nvp_maskisr_modes[] = { { .name = "off", .value = AARCH64_ISRMASK_OFF }, { .name = "on", .value = AARCH64_ISRMASK_ON }, { .name = NULL, .value = -1 }, }; - const Jim_Nvp *n; + const struct jim_nvp *n; if (CMD_ARGC > 0) { - n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); if (n->name == NULL) { LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; @@ -2947,7 +2947,7 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command) aarch64->isrmasking_mode = n->value; } - n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode); + n = jim_nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode); command_print(CMD, "aarch64 interrupt mask %s", n->name); return ERROR_OK; diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c index 5c5247b..26c67c6 100644 --- a/src/target/arc_cmd.c +++ b/src/target/arc_cmd.c @@ -22,10 +22,10 @@ * ------------------------------------------------------------------------- */ -static int arc_cmd_jim_get_uint32(Jim_GetOptInfo *goi, uint32_t *value) +static int arc_cmd_jim_get_uint32(struct jim_getopt_info *goi, uint32_t *value) { jim_wide value_wide; - JIM_CHECK_RETVAL(Jim_GetOpt_Wide(goi, &value_wide)); + JIM_CHECK_RETVAL(jim_getopt_wide(goi, &value_wide)); *value = (uint32_t)value_wide; return JIM_OK; } @@ -40,7 +40,7 @@ enum add_reg_type_flags { CFG_ADD_REG_TYPE_FLAGS_FLAG, }; -static Jim_Nvp nvp_add_reg_type_flags_opts[] = { +static struct jim_nvp nvp_add_reg_type_flags_opts[] = { { .name = "-name", .value = CFG_ADD_REG_TYPE_FLAGS_NAME }, { .name = "-flag", .value = CFG_ADD_REG_TYPE_FLAGS_FLAG }, { .name = NULL, .value = -1 } @@ -64,7 +64,7 @@ static const char *validate_register(const struct arc_reg_desc * const reg, bool /* Helper function to read the name of register type or register from * configure files */ -static int jim_arc_read_reg_name_field(Jim_GetOptInfo *goi, +static int jim_arc_read_reg_name_field(struct jim_getopt_info *goi, const char **name, int *name_len) { int e = JIM_OK; @@ -73,12 +73,12 @@ static int jim_arc_read_reg_name_field(Jim_GetOptInfo *goi, Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-name ..."); return JIM_ERR; } - e = Jim_GetOpt_String(goi, name, name_len); + e = jim_getopt_string(goi, name, name_len); return e; } /* Helper function to read bitfields/flags of register type. */ -static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_name, int *field_name_len, +static int jim_arc_read_reg_type_field(struct jim_getopt_info *goi, const char **field_name, int *field_name_len, struct arc_reg_bitfield *bitfields, int cur_field, int type) { jim_wide start_pos, end_pos; @@ -90,12 +90,12 @@ static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_n return JIM_ERR; } - e = Jim_GetOpt_String(goi, field_name, field_name_len); + e = jim_getopt_string(goi, field_name, field_name_len); if (e != JIM_OK) return e; /* read start position of bitfield/flag */ - e = Jim_GetOpt_Wide(goi, &start_pos); + e = jim_getopt_wide(goi, &start_pos); if (e != JIM_OK) return e; @@ -108,7 +108,7 @@ static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_n * than bitfields[cur_field].end remains start */ if ((strcmp(Jim_String(goi->argv[0]), "-flag") && type == CFG_ADD_REG_TYPE_FLAG) || (type == CFG_ADD_REG_TYPE_STRUCT)) { - e = Jim_GetOpt_Wide(goi, &end_pos); + e = jim_getopt_wide(goi, &end_pos); if (e != JIM_OK) { Jim_SetResultFormatted(goi->interp, "Error reading end position"); return e; @@ -125,8 +125,8 @@ static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_n static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); LOG_DEBUG("-"); @@ -179,10 +179,10 @@ static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc, flags->size = 4; /* For now ARC has only 32-bit registers */ while (goi.argc > 0 && e == JIM_OK) { - Jim_Nvp *n; - e = Jim_GetOpt_Nvp(&goi, nvp_add_reg_type_flags_opts, &n); + struct jim_nvp *n; + e = jim_getopt_nvp(&goi, nvp_add_reg_type_flags_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_add_reg_type_flags_opts, 0); + jim_getopt_nvp_unknown(&goi, nvp_add_reg_type_flags_opts, 0); continue; } @@ -272,7 +272,7 @@ enum add_reg_type_struct { CFG_ADD_REG_TYPE_STRUCT_BITFIELD, }; -static Jim_Nvp nvp_add_reg_type_struct_opts[] = { +static struct jim_nvp nvp_add_reg_type_struct_opts[] = { { .name = "-name", .value = CFG_ADD_REG_TYPE_STRUCT_NAME }, { .name = "-bitfield", .value = CFG_ADD_REG_TYPE_STRUCT_BITFIELD }, { .name = NULL, .value = -1 } @@ -286,8 +286,8 @@ static int jim_arc_set_aux_reg(Jim_Interp *interp, int argc, Jim_Obj * const *ar uint32_t regnum; uint32_t value; - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); if (goi.argc != 2) { Jim_SetResultFormatted(goi.interp, @@ -325,8 +325,8 @@ static int jim_arc_get_aux_reg(Jim_Interp *interp, int argc, Jim_Obj * const *ar uint32_t regnum; uint32_t value; - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); if (goi.argc != 1) { Jim_SetResultFormatted(goi.interp, @@ -362,8 +362,8 @@ static int jim_arc_get_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *a uint32_t regnum; uint32_t value; - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); if (goi.argc != 1) { Jim_SetResultFormatted(goi.interp, @@ -405,8 +405,8 @@ static int jim_arc_set_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *a uint32_t regnum; uint32_t value; - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); if (goi.argc != 2) { Jim_SetResultFormatted(goi.interp, @@ -491,8 +491,8 @@ static const struct command_registration arc_jtag_command_group[] = { static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); LOG_DEBUG("-"); @@ -545,10 +545,10 @@ static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc, struct_type->size = 4; /* For now ARC has only 32-bit registers */ while (goi.argc > 0 && e == JIM_OK) { - Jim_Nvp *n; - e = Jim_GetOpt_Nvp(&goi, nvp_add_reg_type_struct_opts, &n); + struct jim_nvp *n; + e = jim_getopt_nvp(&goi, nvp_add_reg_type_struct_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_add_reg_type_struct_opts, 0); + jim_getopt_nvp_unknown(&goi, nvp_add_reg_type_struct_opts, 0); continue; } @@ -642,7 +642,7 @@ enum opts_add_reg { CFG_ADD_REG_GENERAL, }; -static Jim_Nvp opts_nvp_add_reg[] = { +static struct jim_nvp opts_nvp_add_reg[] = { { .name = "-name", .value = CFG_ADD_REG_NAME }, { .name = "-num", .value = CFG_ADD_REG_ARCH_NUM }, { .name = "-core", .value = CFG_ADD_REG_IS_CORE }, @@ -662,8 +662,8 @@ void free_reg_desc(struct arc_reg_desc *r) static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + struct jim_getopt_info goi; + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); struct arc_reg_desc *reg = calloc(1, sizeof(*reg)); if (!reg) { @@ -692,10 +692,10 @@ static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) /* Parse options. */ while (goi.argc > 0) { - Jim_Nvp *n; - e = Jim_GetOpt_Nvp(&goi, opts_nvp_add_reg, &n); + struct jim_nvp *n; + e = jim_getopt_nvp(&goi, opts_nvp_add_reg, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, opts_nvp_add_reg, 0); + jim_getopt_nvp_unknown(&goi, opts_nvp_add_reg, 0); free_reg_desc(reg); return e; } @@ -732,7 +732,7 @@ static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv) return JIM_ERR; } - e = Jim_GetOpt_Wide(&goi, &archnum); + e = jim_getopt_wide(&goi, &archnum); if (e != JIM_OK) { free_reg_desc(reg); return e; @@ -845,12 +845,12 @@ COMMAND_HANDLER(arc_set_reg_exists) * Reads struct type register field */ static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; + struct jim_getopt_info goi; const char *reg_name, *field_name; uint32_t value; int retval; - JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1)); + JIM_CHECK_RETVAL(jim_getopt_setup(&goi, interp, argc-1, argv+1)); LOG_DEBUG("Reading register field"); if (goi.argc != 2) { @@ -863,8 +863,8 @@ static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const * return ERROR_COMMAND_SYNTAX_ERROR; } - JIM_CHECK_RETVAL(Jim_GetOpt_String(&goi, ®_name, NULL)); - JIM_CHECK_RETVAL(Jim_GetOpt_String(&goi, &field_name, NULL)); + JIM_CHECK_RETVAL(jim_getopt_string(&goi, ®_name, NULL)); + JIM_CHECK_RETVAL(jim_getopt_string(&goi, &field_name, NULL)); assert(reg_name); assert(field_name); @@ -932,8 +932,8 @@ COMMAND_HANDLER(arc_l2_cache_disable_auto_cmd) static int jim_handle_actionpoints_num(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); LOG_DEBUG("-"); diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 6569fcc..35d686e 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1500,7 +1500,7 @@ enum adiv5_cfg_param { CFG_CTIBASE, /* DEPRECATED */ }; -static const Jim_Nvp nvp_config_opts[] = { +static const struct jim_nvp nvp_config_opts[] = { { .name = "-dap", .value = CFG_DAP }, { .name = "-ap-num", .value = CFG_AP_NUM }, { .name = "-baseaddr", .value = CFG_BASEADDR }, @@ -1508,7 +1508,7 @@ static const Jim_Nvp nvp_config_opts[] = { { .name = NULL, .value = -1 } }; -static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, +static int adiv5_jim_spot_configure(struct jim_getopt_info *goi, struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p) { if (!goi->argc) @@ -1516,8 +1516,8 @@ static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, Jim_SetEmptyResult(goi->interp); - Jim_Nvp *n; - int e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts, + struct jim_nvp *n; + int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts, goi->argv[0], &n); if (e != JIM_OK) return JIM_CONTINUE; @@ -1526,7 +1526,7 @@ static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE)) return JIM_CONTINUE; - e = Jim_GetOpt_Obj(goi, NULL); + e = jim_getopt_obj(goi, NULL); if (e != JIM_OK) return e; @@ -1535,7 +1535,7 @@ static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, if (goi->isconfigure) { Jim_Obj *o_t; struct adiv5_dap *dap; - e = Jim_GetOpt_Obj(goi, &o_t); + e = jim_getopt_obj(goi, &o_t); if (e != JIM_OK) return e; dap = dap_instance_by_jim_obj(goi->interp, o_t); @@ -1563,7 +1563,7 @@ static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, case CFG_AP_NUM: if (goi->isconfigure) { jim_wide ap_num; - e = Jim_GetOpt_Wide(goi, &ap_num); + e = jim_getopt_wide(goi, &ap_num); if (e != JIM_OK) return e; if (ap_num < 0 || ap_num > DP_APSEL_MAX) { @@ -1588,7 +1588,7 @@ static int adiv5_jim_spot_configure(Jim_GetOptInfo *goi, case CFG_BASEADDR: if (goi->isconfigure) { jim_wide base; - e = Jim_GetOpt_Wide(goi, &base); + e = jim_getopt_wide(goi, &base); if (e != JIM_OK) return e; *base_p = (uint32_t)base; @@ -1607,7 +1607,7 @@ err_no_param: return JIM_ERR; } -int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi) +int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi) { struct adiv5_private_config *pc; int e; @@ -1651,7 +1651,7 @@ int adiv5_verify_config(struct adiv5_private_config *pc) } int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg, - Jim_GetOptInfo *goi) + struct jim_getopt_info *goi) { return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base); } diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 00e4ea2..ce9155a 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -602,7 +602,7 @@ struct adiv5_private_config { }; extern int adiv5_verify_config(struct adiv5_private_config *pc); -extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi); +extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi); struct adiv5_mem_ap_spot { struct adiv5_dap *dap; @@ -612,6 +612,6 @@ struct adiv5_mem_ap_spot { extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p); extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg, - Jim_GetOptInfo *goi); + struct jim_getopt_info *goi); #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */ diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c index ee9d8aa..30212cb 100644 --- a/src/target/arm_cti.c +++ b/src/target/arm_cti.c @@ -430,7 +430,7 @@ static const struct command_registration cti_instance_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static int cti_configure(Jim_GetOptInfo *goi, struct arm_cti *cti) +static int cti_configure(struct jim_getopt_info *goi, struct arm_cti *cti) { /* parse config or cget options ... */ while (goi->argc > 0) { @@ -446,7 +446,7 @@ static int cti_configure(Jim_GetOptInfo *goi, struct arm_cti *cti) return JIM_OK; } -static int cti_create(Jim_GetOptInfo *goi) +static int cti_create(struct jim_getopt_info *goi) { struct command_context *cmd_ctx; static struct arm_cti *cti; @@ -463,7 +463,7 @@ static int cti_create(Jim_GetOptInfo *goi) return JIM_ERR; } /* COMMAND */ - Jim_GetOpt_Obj(goi, &new_cmd); + jim_getopt_obj(goi, &new_cmd); /* does this command exist? */ cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG); if (cmd) { @@ -518,8 +518,8 @@ static int cti_create(Jim_GetOptInfo *goi) static int jim_cti_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 2) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, " [ ...]"); diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index a9277e7..747733d 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -156,31 +156,31 @@ enum dap_cfg_param { CFG_IGNORE_SYSPWRUPACK, }; -static const Jim_Nvp nvp_config_opts[] = { +static const struct jim_nvp nvp_config_opts[] = { { .name = "-chain-position", .value = CFG_CHAIN_POSITION }, { .name = "-ignore-syspwrupack", .value = CFG_IGNORE_SYSPWRUPACK }, { .name = NULL, .value = -1 } }; -static int dap_configure(Jim_GetOptInfo *goi, struct arm_dap_object *dap) +static int dap_configure(struct jim_getopt_info *goi, struct arm_dap_object *dap) { struct jtag_tap *tap = NULL; - Jim_Nvp *n; + struct jim_nvp *n; int e; /* parse config or cget options ... */ while (goi->argc > 0) { Jim_SetEmptyResult(goi->interp); - e = Jim_GetOpt_Nvp(goi, nvp_config_opts, &n); + e = jim_getopt_nvp(goi, nvp_config_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_config_opts, 0); + jim_getopt_nvp_unknown(goi, nvp_config_opts, 0); return e; } switch (n->value) { case CFG_CHAIN_POSITION: { Jim_Obj *o_t; - e = Jim_GetOpt_Obj(goi, &o_t); + e = jim_getopt_obj(goi, &o_t); if (e != JIM_OK) return e; tap = jtag_tap_by_jim_obj(goi->interp, o_t); @@ -210,7 +210,7 @@ static int dap_configure(Jim_GetOptInfo *goi, struct arm_dap_object *dap) return JIM_OK; } -static int dap_create(Jim_GetOptInfo *goi) +static int dap_create(struct jim_getopt_info *goi) { struct command_context *cmd_ctx; static struct arm_dap_object *dap; @@ -227,7 +227,7 @@ static int dap_create(Jim_GetOptInfo *goi) return JIM_ERR; } /* COMMAND */ - Jim_GetOpt_Obj(goi, &new_cmd); + jim_getopt_obj(goi, &new_cmd); /* does this command exist? */ cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG); if (cmd) { @@ -276,8 +276,8 @@ static int dap_create(Jim_GetOptInfo *goi) static int jim_dap_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 2) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, " [ ...]"); diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c index f935086..6d1e94f 100644 --- a/src/target/arm_tpiu_swo.c +++ b/src/target/arm_tpiu_swo.c @@ -73,7 +73,7 @@ enum arm_tpiu_swo_event { TPIU_SWO_EVENT_POST_DISABLE, }; -static const Jim_Nvp nvp_arm_tpiu_swo_event[] = { +static const struct jim_nvp nvp_arm_tpiu_swo_event[] = { { .value = TPIU_SWO_EVENT_PRE_ENABLE, .name = "pre-enable" }, { .value = TPIU_SWO_EVENT_POST_ENABLE, .name = "post-enable" }, { .value = TPIU_SWO_EVENT_PRE_DISABLE, .name = "pre-disable" }, @@ -168,7 +168,7 @@ static void arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_ LOG_DEBUG("TPIU/SWO: %s event: %s (%d) action : %s", obj->name, - Jim_Nvp_value2name_simple(nvp_arm_tpiu_swo_event, event)->name, + jim_nvp_value2name_simple(nvp_arm_tpiu_swo_event, event)->name, event, Jim_GetString(ea->body, NULL)); @@ -185,7 +185,7 @@ static void arm_tpiu_swo_handle_event(struct arm_tpiu_swo_object *obj, enum arm_ Jim_MakeErrorMessage(ea->interp); LOG_USER("Error executing event %s on TPIU/SWO %s:\n%s", - Jim_Nvp_value2name_simple(nvp_arm_tpiu_swo_event, event)->name, + jim_nvp_value2name_simple(nvp_arm_tpiu_swo_event, event)->name, obj->name, Jim_GetString(Jim_GetResult(ea->interp), NULL)); /* clean both error code and stacktrace before return */ @@ -297,7 +297,7 @@ COMMAND_HANDLER(handle_arm_tpiu_swo_event_list) "----------------------------------------"); for (struct arm_tpiu_swo_event_action *ea = obj->event_action; ea; ea = ea->next) { - Jim_Nvp *opt = Jim_Nvp_value2name_simple(nvp_arm_tpiu_swo_event, ea->event); + struct jim_nvp *opt = jim_nvp_value2name_simple(nvp_arm_tpiu_swo_event, ea->event); command_print(CMD, "%-25s | %s", opt->name, Jim_GetString(ea->body, NULL)); } @@ -315,7 +315,7 @@ enum arm_tpiu_swo_cfg_param { CFG_EVENT, }; -static const Jim_Nvp nvp_arm_tpiu_swo_config_opts[] = { +static const struct jim_nvp nvp_arm_tpiu_swo_config_opts[] = { { .name = "-port-width", .value = CFG_PORT_WIDTH }, { .name = "-protocol", .value = CFG_PROTOCOL }, { .name = "-formatter", .value = CFG_FORMATTER }, @@ -323,21 +323,21 @@ static const Jim_Nvp nvp_arm_tpiu_swo_config_opts[] = { { .name = "-pin-freq", .value = CFG_BITRATE }, { .name = "-output", .value = CFG_OUTFILE }, { .name = "-event", .value = CFG_EVENT }, - /* handled by mem_ap_spot, added for Jim_GetOpt_NvpUnknown() */ + /* handled by mem_ap_spot, added for jim_getopt_nvp_unknown() */ { .name = "-dap", .value = -1 }, { .name = "-ap-num", .value = -1 }, { .name = "-baseaddr", .value = -1 }, { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_arm_tpiu_swo_protocol_opts[] = { +static const struct jim_nvp nvp_arm_tpiu_swo_protocol_opts[] = { { .name = "sync", .value = TPIU_SPPR_PROTOCOL_SYNC }, { .name = "uart", .value = TPIU_SPPR_PROTOCOL_UART }, { .name = "manchester", .value = TPIU_SPPR_PROTOCOL_MANCHESTER }, { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_arm_tpiu_swo_bool_opts[] = { +static const struct jim_nvp nvp_arm_tpiu_swo_bool_opts[] = { { .name = "on", .value = 1 }, { .name = "yes", .value = 1 }, { .name = "1", .value = 1 }, @@ -349,7 +349,7 @@ static const Jim_Nvp nvp_arm_tpiu_swo_bool_opts[] = { { .name = NULL, .value = -1 }, }; -static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_object *obj) +static int arm_tpiu_swo_configure(struct jim_getopt_info *goi, struct arm_tpiu_swo_object *obj) { assert(obj != NULL); @@ -368,10 +368,10 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec if (e == JIM_ERR) return e; - Jim_Nvp *n; - e = Jim_GetOpt_Nvp(goi, nvp_arm_tpiu_swo_config_opts, &n); + struct jim_nvp *n; + e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_config_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_arm_tpiu_swo_config_opts, 0); + jim_getopt_nvp_unknown(goi, nvp_arm_tpiu_swo_config_opts, 0); return e; } @@ -379,7 +379,7 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec case CFG_PORT_WIDTH: if (goi->isconfigure) { jim_wide port_width; - e = Jim_GetOpt_Wide(goi, &port_width); + e = jim_getopt_wide(goi, &port_width); if (e != JIM_OK) return e; if (port_width < 1 || port_width > 32) { @@ -395,16 +395,16 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec break; case CFG_PROTOCOL: if (goi->isconfigure) { - Jim_Nvp *p; - e = Jim_GetOpt_Nvp(goi, nvp_arm_tpiu_swo_protocol_opts, &p); + struct jim_nvp *p; + e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_protocol_opts, &p); if (e != JIM_OK) return e; obj->pin_protocol = p->value; } else { if (goi->argc) goto err_no_params; - Jim_Nvp *p; - e = Jim_Nvp_value2name(goi->interp, nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol, &p); + struct jim_nvp *p; + e = jim_nvp_value2name(goi->interp, nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol, &p); if (e != JIM_OK) { Jim_SetResultString(goi->interp, "protocol error", -1); return JIM_ERR; @@ -414,16 +414,16 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec break; case CFG_FORMATTER: if (goi->isconfigure) { - Jim_Nvp *p; - e = Jim_GetOpt_Nvp(goi, nvp_arm_tpiu_swo_bool_opts, &p); + struct jim_nvp *p; + e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_bool_opts, &p); if (e != JIM_OK) return e; obj->en_formatter = p->value; } else { if (goi->argc) goto err_no_params; - Jim_Nvp *p; - e = Jim_Nvp_value2name(goi->interp, nvp_arm_tpiu_swo_bool_opts, obj->en_formatter, &p); + struct jim_nvp *p; + e = jim_nvp_value2name(goi->interp, nvp_arm_tpiu_swo_bool_opts, obj->en_formatter, &p); if (e != JIM_OK) { Jim_SetResultString(goi->interp, "formatter error", -1); return JIM_ERR; @@ -434,7 +434,7 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec case CFG_TRACECLKIN: if (goi->isconfigure) { jim_wide clk; - e = Jim_GetOpt_Wide(goi, &clk); + e = jim_getopt_wide(goi, &clk); if (e != JIM_OK) return e; obj->traceclkin_freq = clk; @@ -447,7 +447,7 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec case CFG_BITRATE: if (goi->isconfigure) { jim_wide clk; - e = Jim_GetOpt_Wide(goi, &clk); + e = jim_getopt_wide(goi, &clk); if (e != JIM_OK) return e; obj->swo_pin_freq = clk; @@ -460,7 +460,7 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec case CFG_OUTFILE: if (goi->isconfigure) { const char *s; - e = Jim_GetOpt_String(goi, &s, NULL); + e = jim_getopt_string(goi, &s, NULL); if (e != JIM_OK) return e; if (s[0] == ':') { @@ -498,13 +498,13 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec } { - Jim_Nvp *p; + struct jim_nvp *p; Jim_Obj *o; struct arm_tpiu_swo_event_action *ea = obj->event_action; - e = Jim_GetOpt_Nvp(goi, nvp_arm_tpiu_swo_event, &p); + e = jim_getopt_nvp(goi, nvp_arm_tpiu_swo_event, &p); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_arm_tpiu_swo_event, 1); + jim_getopt_nvp_unknown(goi, nvp_arm_tpiu_swo_event, 1); return e; } @@ -529,7 +529,7 @@ static int arm_tpiu_swo_configure(Jim_GetOptInfo *goi, struct arm_tpiu_swo_objec Jim_DecrRefCount(ea->interp, ea->body); ea->event = p->value; ea->interp = goi->interp; - Jim_GetOpt_Obj(goi, &o); + jim_getopt_obj(goi, &o); ea->body = Jim_DuplicateObj(goi->interp, o); Jim_IncrRefCount(ea->body); } else { @@ -551,9 +551,9 @@ err_no_params: static int jim_arm_tpiu_swo_configure(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { struct command *c = jim_to_command(interp); - Jim_GetOptInfo goi; + struct jim_getopt_info goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); goi.isconfigure = !strcmp(c->name, "configure"); if (goi.argc < 1) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, @@ -670,8 +670,8 @@ static int jim_arm_tpiu_swo_enable(Jim_Interp *interp, int argc, Jim_Obj *const value = 0; } if (!value) { - Jim_Nvp *p; - Jim_Nvp_value2name(interp, nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol, &p); + struct jim_nvp *p; + jim_nvp_value2name(interp, nvp_arm_tpiu_swo_protocol_opts, obj->pin_protocol, &p); LOG_ERROR("%s does not support protocol %s", obj->name, p->name); return JIM_ERR; } @@ -897,8 +897,8 @@ static int arm_tpiu_swo_create(Jim_Interp *interp, struct arm_tpiu_swo_object *o static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 1) { Jim_WrongNumArgs(goi.interp, 1, goi.argv, "?name? ..options..."); return JIM_ERR; @@ -915,7 +915,7 @@ static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const obj->port_width = 1; Jim_Obj *n; - Jim_GetOpt_Obj(&goi, &n); + jim_getopt_obj(&goi, &n); obj->name = strdup(Jim_GetString(n, NULL)); if (!obj->name) { LOG_ERROR("Out of memory"); diff --git a/src/target/armv8.c b/src/target/armv8.c index 0c5cf34..6d60a1c 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1025,7 +1025,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) unsigned int argp = 0; int retval; - static const Jim_Nvp nvp_ecatch_modes[] = { + static const struct jim_nvp nvp_ecatch_modes[] = { { .name = "off", .value = 0 }, { .name = "nsec_el1", .value = (1 << 5) }, { .name = "nsec_el2", .value = (2 << 5) }, @@ -1035,7 +1035,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) { .name = "sec_el13", .value = (5 << 1) }, { .name = NULL, .value = -1 }, }; - const Jim_Nvp *n; + const struct jim_nvp *n; if (CMD_ARGC == 0) { const char *sec = NULL, *nsec = NULL; @@ -1045,11 +1045,11 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) if (retval != ERROR_OK) return retval; - n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f); + n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f); if (n->name != NULL) sec = n->name; - n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0); + n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0); if (n->name != NULL) nsec = n->name; @@ -1063,7 +1063,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command) } while (CMD_ARGC > argp) { - n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); + n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); if (n->name == NULL) { LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]); return ERROR_FAIL; diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 35f1499..6b76656 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -3259,15 +3259,15 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) struct target *target = get_current_target(CMD_CTX); struct cortex_a_common *cortex_a = target_to_cortex_a(target); - static const Jim_Nvp nvp_maskisr_modes[] = { + static const struct jim_nvp nvp_maskisr_modes[] = { { .name = "off", .value = CORTEX_A_ISRMASK_OFF }, { .name = "on", .value = CORTEX_A_ISRMASK_ON }, { .name = NULL, .value = -1 }, }; - const Jim_Nvp *n; + const struct jim_nvp *n; if (CMD_ARGC > 0) { - n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); if (n->name == NULL) { LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; @@ -3276,7 +3276,7 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) cortex_a->isrmasking_mode = n->value; } - n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode); + n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode); command_print(CMD, "cortex_a interrupt mask %s", n->name); return ERROR_OK; @@ -3287,22 +3287,22 @@ COMMAND_HANDLER(handle_cortex_a_dacrfixup_command) struct target *target = get_current_target(CMD_CTX); struct cortex_a_common *cortex_a = target_to_cortex_a(target); - static const Jim_Nvp nvp_dacrfixup_modes[] = { + static const struct jim_nvp nvp_dacrfixup_modes[] = { { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF }, { .name = "on", .value = CORTEX_A_DACRFIXUP_ON }, { .name = NULL, .value = -1 }, }; - const Jim_Nvp *n; + const struct jim_nvp *n; if (CMD_ARGC > 0) { - n = Jim_Nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]); + n = jim_nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]); if (n->name == NULL) return ERROR_COMMAND_SYNTAX_ERROR; cortex_a->dacrfixup_mode = n->value; } - n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode); + n = jim_nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode); command_print(CMD, "cortex_a domain access control fixup %s", n->name); return ERROR_OK; diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 9f9bc0d..941fef1 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -2398,14 +2398,14 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command) struct cortex_m_common *cortex_m = target_to_cm(target); int retval; - static const Jim_Nvp nvp_maskisr_modes[] = { + static const struct jim_nvp nvp_maskisr_modes[] = { { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO }, { .name = "off", .value = CORTEX_M_ISRMASK_OFF }, { .name = "on", .value = CORTEX_M_ISRMASK_ON }, { .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY }, { .name = NULL, .value = -1 }, }; - const Jim_Nvp *n; + const struct jim_nvp *n; retval = cortex_m_verify_pointer(CMD, cortex_m); @@ -2418,14 +2418,14 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command) } if (CMD_ARGC > 0) { - n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); + n = jim_nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); if (n->name == NULL) return ERROR_COMMAND_SYNTAX_ERROR; cortex_m->isrmasking_mode = n->value; cortex_m_set_maskints_for_halt(target); } - n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode); + n = jim_nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode); command_print(CMD, "cortex_m interrupt mask %s", n->name); return ERROR_OK; diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index 246dbd0..f7647c3 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -681,8 +681,8 @@ static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *a { const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 3) { Jim_SetResultFormatted(goi.interp, @@ -692,12 +692,12 @@ static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *a int e; jim_wide address; - e = Jim_GetOpt_Wide(&goi, &address); + e = jim_getopt_wide(&goi, &address); if (e != JIM_OK) return e; jim_wide count; - e = Jim_GetOpt_Wide(&goi, &count); + e = jim_getopt_wide(&goi, &count); if (e != JIM_OK) return e; @@ -708,7 +708,7 @@ static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *a jim_wide i; for (i = 0; i < count; i++) { jim_wide tmp; - e = Jim_GetOpt_Wide(&goi, &tmp); + e = jim_getopt_wide(&goi, &tmp); if (e != JIM_OK) { free(data); return e; @@ -738,8 +738,8 @@ static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const * { const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 3) { Jim_SetResultFormatted(goi.interp, @@ -749,7 +749,7 @@ static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const * int e; jim_wide num_of_pairs; - e = Jim_GetOpt_Wide(&goi, &num_of_pairs); + e = jim_getopt_wide(&goi, &num_of_pairs); if (e != JIM_OK) return e; @@ -765,12 +765,12 @@ static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const * aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK); for (i = 0; i < num_of_pairs; i++) { jim_wide tmp; - e = Jim_GetOpt_Wide(&goi, &tmp); + e = jim_getopt_wide(&goi, &tmp); if (e != JIM_OK) break; address = (uint32_t)tmp; - e = Jim_GetOpt_Wide(&goi, &tmp); + e = jim_getopt_wide(&goi, &tmp); if (e != JIM_OK) break; data = (uint32_t)tmp; @@ -792,8 +792,8 @@ static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *ar { const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 2) { Jim_SetResultFormatted(goi.interp, @@ -803,12 +803,12 @@ static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *ar int e; jim_wide address; - e = Jim_GetOpt_Wide(&goi, &address); + e = jim_getopt_wide(&goi, &address); if (e != JIM_OK) return e; jim_wide count; - e = Jim_GetOpt_Wide(&goi, &count); + e = jim_getopt_wide(&goi, &count); if (e != JIM_OK) return e; @@ -840,8 +840,8 @@ static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const * { const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 1) { Jim_SetResultFormatted(goi.interp, @@ -852,7 +852,7 @@ static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const * int e; const char *edm_sr_name; int edm_sr_name_len; - e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len); + e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len); if (e != JIM_OK) return e; @@ -888,8 +888,8 @@ static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const { const char *cmd_name = Jim_GetString(argv[0], NULL); - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 2) { Jim_SetResultFormatted(goi.interp, @@ -900,12 +900,12 @@ static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const int e; const char *edm_sr_name; int edm_sr_name_len; - e = Jim_GetOpt_String(&goi, &edm_sr_name, &edm_sr_name_len); + e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len); if (e != JIM_OK) return e; jim_wide value; - e = Jim_GetOpt_Wide(&goi, &value); + e = jim_getopt_wide(&goi, &value); if (e != JIM_OK) return e; diff --git a/src/target/stm8.c b/src/target/stm8.c index 2a34ff6..00b524e 100644 --- a/src/target/stm8.c +++ b/src/target/stm8.c @@ -1945,7 +1945,7 @@ static int stm8_run_algorithm(struct target *target, int num_mem_params, return ERROR_OK; } -static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) +static int stm8_jim_configure(struct target *target, struct jim_getopt_info *goi) { struct stm8_common *stm8 = target_to_stm8(target); jim_wide w; @@ -1954,7 +1954,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) arg = Jim_GetString(goi->argv[0], NULL); if (!strcmp(arg, "-blocksize")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -1964,7 +1964,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -1973,7 +1973,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-flashstart")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -1983,7 +1983,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -1992,7 +1992,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-flashend")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2002,7 +2002,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -2011,7 +2011,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-eepromstart")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2021,7 +2021,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -2030,7 +2030,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-eepromend")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2040,7 +2040,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -2049,7 +2049,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-optionstart")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2059,7 +2059,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -2068,7 +2068,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-optionend")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2078,7 +2078,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; @@ -2087,7 +2087,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-enable_step_irq")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; @@ -2096,7 +2096,7 @@ static int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi) return JIM_OK; } if (!strcmp(arg, "-enable_stm8l")) { - e = Jim_GetOpt_String(goi, &arg, NULL); + e = jim_getopt_string(goi, &arg, NULL); if (e != JIM_OK) return e; diff --git a/src/target/target.c b/src/target/target.c index 1c1deee..1547b29 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -158,7 +158,7 @@ static LIST_HEAD(target_reset_callback_list); static LIST_HEAD(target_trace_callback_list); static const int polling_interval = 100; -static const Jim_Nvp nvp_assert[] = { +static const struct jim_nvp nvp_assert[] = { { .name = "assert", NVP_ASSERT }, { .name = "deassert", NVP_DEASSERT }, { .name = "T", NVP_ASSERT }, @@ -168,7 +168,7 @@ static const Jim_Nvp nvp_assert[] = { { .name = NULL, .value = -1 } }; -static const Jim_Nvp nvp_error_target[] = { +static const struct jim_nvp nvp_error_target[] = { { .value = ERROR_TARGET_INVALID, .name = "err-invalid" }, { .value = ERROR_TARGET_INIT_FAILED, .name = "err-init-failed" }, { .value = ERROR_TARGET_TIMEOUT, .name = "err-timeout" }, @@ -185,16 +185,16 @@ static const Jim_Nvp nvp_error_target[] = { static const char *target_strerror_safe(int err) { - const Jim_Nvp *n; + const struct jim_nvp *n; - n = Jim_Nvp_value2name_simple(nvp_error_target, err); + n = jim_nvp_value2name_simple(nvp_error_target, err); if (n->name == NULL) return "unknown"; else return n->name; } -static const Jim_Nvp nvp_target_event[] = { +static const struct jim_nvp nvp_target_event[] = { { .value = TARGET_EVENT_GDB_HALT, .name = "gdb-halt" }, { .value = TARGET_EVENT_HALTED, .name = "halted" }, @@ -237,7 +237,7 @@ static const Jim_Nvp nvp_target_event[] = { { .name = NULL, .value = -1 } }; -static const Jim_Nvp nvp_target_state[] = { +static const struct jim_nvp nvp_target_state[] = { { .name = "unknown", .value = TARGET_UNKNOWN }, { .name = "running", .value = TARGET_RUNNING }, { .name = "halted", .value = TARGET_HALTED }, @@ -246,7 +246,7 @@ static const Jim_Nvp nvp_target_state[] = { { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_target_debug_reason[] = { +static const struct jim_nvp nvp_target_debug_reason[] = { { .name = "debug-request", .value = DBG_REASON_DBGRQ }, { .name = "breakpoint", .value = DBG_REASON_BREAKPOINT }, { .name = "watchpoint", .value = DBG_REASON_WATCHPOINT }, @@ -259,7 +259,7 @@ static const Jim_Nvp nvp_target_debug_reason[] = { { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_target_endian[] = { +static const struct jim_nvp nvp_target_endian[] = { { .name = "big", .value = TARGET_BIG_ENDIAN }, { .name = "little", .value = TARGET_LITTLE_ENDIAN }, { .name = "be", .value = TARGET_BIG_ENDIAN }, @@ -267,7 +267,7 @@ static const Jim_Nvp nvp_target_endian[] = { { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_reset_modes[] = { +static const struct jim_nvp nvp_reset_modes[] = { { .name = "unknown", .value = RESET_UNKNOWN }, { .name = "run", .value = RESET_RUN }, { .name = "halt", .value = RESET_HALT }, @@ -279,7 +279,7 @@ const char *debug_reason_name(struct target *t) { const char *cp; - cp = Jim_Nvp_value2name_simple(nvp_target_debug_reason, + cp = jim_nvp_value2name_simple(nvp_target_debug_reason, t->debug_reason)->name; if (!cp) { LOG_ERROR("Invalid debug reason: %d", (int)(t->debug_reason)); @@ -291,7 +291,7 @@ const char *debug_reason_name(struct target *t) const char *target_state_name(struct target *t) { const char *cp; - cp = Jim_Nvp_value2name_simple(nvp_target_state, t->state)->name; + cp = jim_nvp_value2name_simple(nvp_target_state, t->state)->name; if (!cp) { LOG_ERROR("Invalid target state: %d", (int)(t->state)); cp = "(*BUG*unknown*BUG*)"; @@ -306,7 +306,7 @@ const char *target_state_name(struct target *t) const char *target_event_name(enum target_event event) { const char *cp; - cp = Jim_Nvp_value2name_simple(nvp_target_event, event)->name; + cp = jim_nvp_value2name_simple(nvp_target_event, event)->name; if (!cp) { LOG_ERROR("Invalid target event: %d", (int)(event)); cp = "(*BUG*unknown*BUG*)"; @@ -317,7 +317,7 @@ const char *target_event_name(enum target_event event) const char *target_reset_mode_name(enum target_reset_mode reset_mode) { const char *cp; - cp = Jim_Nvp_value2name_simple(nvp_reset_modes, reset_mode)->name; + cp = jim_nvp_value2name_simple(nvp_reset_modes, reset_mode)->name; if (!cp) { LOG_ERROR("Invalid target reset mode: %d", (int)(reset_mode)); cp = "(*BUG*unknown*BUG*)"; @@ -661,8 +661,8 @@ static int target_process_reset(struct command_invocation *cmd, enum target_rese { char buf[100]; int retval; - Jim_Nvp *n; - n = Jim_Nvp_value2name_simple(nvp_reset_modes, reset_mode); + struct jim_nvp *n; + n = jim_nvp_value2name_simple(nvp_reset_modes, reset_mode); if (n->name == NULL) { LOG_ERROR("invalid reset mode"); return ERROR_FAIL; @@ -1823,7 +1823,7 @@ int target_call_event_callbacks(struct target *target, enum target_event event) } LOG_DEBUG("target event %i (%s) for core %s", event, - Jim_Nvp_value2name_simple(nvp_target_event, event)->name, + jim_nvp_value2name_simple(nvp_target_event, event)->name, target_name(target)); target_handle_event(target, event); @@ -1842,7 +1842,7 @@ int target_call_reset_callbacks(struct target *target, enum target_reset_mode re struct target_reset_callback *callback; LOG_DEBUG("target reset %i (%s)", reset_mode, - Jim_Nvp_value2name_simple(nvp_reset_modes, reset_mode)->name); + jim_nvp_value2name_simple(nvp_reset_modes, reset_mode)->name); list_for_each_entry(callback, &target_reset_callback_list, list) callback->callback(target, reset_mode, callback->priv); @@ -2859,7 +2859,7 @@ COMMAND_HANDLER(handle_targets_command) marker, target_name(target), target_type_name(target), - Jim_Nvp_value2name_simple(nvp_target_endian, + jim_nvp_value2name_simple(nvp_target_endian, target->endianness)->name, target->tap->dotted_name, state); @@ -3239,7 +3239,7 @@ int target_wait_state(struct target *target, enum target_state state, int ms) once = false; then = timeval_ms(); LOG_DEBUG("waiting for target %s...", - Jim_Nvp_value2name_simple(nvp_target_state, state)->name); + jim_nvp_value2name_simple(nvp_target_state, state)->name); } if (cur-then > 500) @@ -3247,7 +3247,7 @@ int target_wait_state(struct target *target, enum target_state state, int ms) if ((cur-then) > ms) { LOG_ERROR("timed out while waiting for target %s", - Jim_Nvp_value2name_simple(nvp_target_state, state)->name); + jim_nvp_value2name_simple(nvp_target_state, state)->name); return ERROR_FAIL; } } @@ -3297,8 +3297,8 @@ COMMAND_HANDLER(handle_reset_command) enum target_reset_mode reset_mode = RESET_RUN; if (CMD_ARGC == 1) { - const Jim_Nvp *n; - n = Jim_Nvp_name2value_simple(nvp_reset_modes, CMD_ARGV[0]); + const struct jim_nvp *n; + n = jim_nvp_name2value_simple(nvp_reset_modes, CMD_ARGV[0]); if ((n->name == NULL) || (n->value == RESET_UNKNOWN)) return ERROR_COMMAND_SYNTAX_ERROR; reset_mode = n->value; @@ -4775,7 +4775,7 @@ void target_handle_event(struct target *target, enum target_event e) target_name(target), target_type_name(target), e, - Jim_Nvp_value2name_simple(nvp_target_event, e)->name, + jim_nvp_value2name_simple(nvp_target_event, e)->name, Jim_GetString(teap->body, NULL)); /* Override current target by the target an event @@ -4799,7 +4799,7 @@ void target_handle_event(struct target *target, enum target_event e) if (retval != JIM_OK) { Jim_MakeErrorMessage(teap->interp); LOG_USER("Error executing event %s on target %s:\n%s", - Jim_Nvp_value2name_simple(nvp_target_event, e)->name, + jim_nvp_value2name_simple(nvp_target_event, e)->name, target_name(target), Jim_GetString(Jim_GetResult(teap->interp), NULL)); /* clean both error code and stacktrace before return */ @@ -4840,7 +4840,7 @@ enum target_cfg_param { TCFG_GDB_MAX_CONNECTIONS, }; -static Jim_Nvp nvp_config_opts[] = { +static struct jim_nvp nvp_config_opts[] = { { .name = "-type", .value = TCFG_TYPE }, { .name = "-event", .value = TCFG_EVENT }, { .name = "-work-area-virt", .value = TCFG_WORK_AREA_VIRT }, @@ -4858,9 +4858,9 @@ static Jim_Nvp nvp_config_opts[] = { { .name = NULL, .value = -1 } }; -static int target_configure(Jim_GetOptInfo *goi, struct target *target) +static int target_configure(struct jim_getopt_info *goi, struct target *target) { - Jim_Nvp *n; + struct jim_nvp *n; Jim_Obj *o; jim_wide w; int e; @@ -4868,7 +4868,7 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) /* parse config or cget options ... */ while (goi->argc > 0) { Jim_SetEmptyResult(goi->interp); - /* Jim_GetOpt_Debug(goi); */ + /* jim_getopt_debug(goi); */ if (target->type->target_jim_configure) { /* target defines a configure function */ @@ -4884,9 +4884,9 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) } /* otherwise we 'continue' below */ } - e = Jim_GetOpt_Nvp(goi, nvp_config_opts, &n); + e = jim_getopt_nvp(goi, nvp_config_opts, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_config_opts, 0); + jim_getopt_nvp_unknown(goi, nvp_config_opts, 0); return e; } switch (n->value) { @@ -4915,9 +4915,9 @@ no_params: return JIM_ERR; } - e = Jim_GetOpt_Nvp(goi, nvp_target_event, &n); + e = jim_getopt_nvp(goi, nvp_target_event, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_target_event, 1); + jim_getopt_nvp_unknown(goi, nvp_target_event, 1); return e; } @@ -4958,7 +4958,7 @@ no_params: } teap->event = n->value; teap->interp = goi->interp; - Jim_GetOpt_Obj(goi, &o); + jim_getopt_obj(goi, &o); if (teap->body) Jim_DecrRefCount(teap->interp, teap->body); teap->body = Jim_DuplicateObj(goi->interp, o); @@ -4994,7 +4994,7 @@ no_params: case TCFG_WORK_AREA_VIRT: if (goi->isconfigure) { target_free_all_working_areas(target); - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->working_area_virt = w; @@ -5010,7 +5010,7 @@ no_params: case TCFG_WORK_AREA_PHYS: if (goi->isconfigure) { target_free_all_working_areas(target); - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->working_area_phys = w; @@ -5026,7 +5026,7 @@ no_params: case TCFG_WORK_AREA_SIZE: if (goi->isconfigure) { target_free_all_working_areas(target); - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->working_area_size = w; @@ -5041,7 +5041,7 @@ no_params: case TCFG_WORK_AREA_BACKUP: if (goi->isconfigure) { target_free_all_working_areas(target); - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; /* make this exactly 1 or 0 */ @@ -5057,9 +5057,9 @@ no_params: case TCFG_ENDIAN: if (goi->isconfigure) { - e = Jim_GetOpt_Nvp(goi, nvp_target_endian, &n); + e = jim_getopt_nvp(goi, nvp_target_endian, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(goi, nvp_target_endian, 1); + jim_getopt_nvp_unknown(goi, nvp_target_endian, 1); return e; } target->endianness = n->value; @@ -5067,10 +5067,10 @@ no_params: if (goi->argc != 0) goto no_params; } - n = Jim_Nvp_value2name_simple(nvp_target_endian, target->endianness); + n = jim_nvp_value2name_simple(nvp_target_endian, target->endianness); if (n->name == NULL) { target->endianness = TARGET_LITTLE_ENDIAN; - n = Jim_Nvp_value2name_simple(nvp_target_endian, target->endianness); + n = jim_nvp_value2name_simple(nvp_target_endian, target->endianness); } Jim_SetResultString(goi->interp, n->name, -1); /* loop for more */ @@ -5078,7 +5078,7 @@ no_params: case TCFG_COREID: if (goi->isconfigure) { - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->coreid = (int32_t)w; @@ -5102,7 +5102,7 @@ no_params: } target_free_all_working_areas(target); - e = Jim_GetOpt_Obj(goi, &o_t); + e = jim_getopt_obj(goi, &o_t); if (e != JIM_OK) return e; tap = jtag_tap_by_jim_obj(goi->interp, o_t); @@ -5119,7 +5119,7 @@ no_params: break; case TCFG_DBGBASE: if (goi->isconfigure) { - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->dbgbase = (uint32_t)w; @@ -5156,7 +5156,7 @@ no_params: } const char *s; - e = Jim_GetOpt_String(goi, &s, NULL); + e = jim_getopt_string(goi, &s, NULL); if (e != JIM_OK) return e; free(target->gdb_port_override); @@ -5177,7 +5177,7 @@ no_params: return JIM_ERR; } - e = Jim_GetOpt_Wide(goi, &w); + e = jim_getopt_wide(goi, &w); if (e != JIM_OK) return e; target->gdb_max_connections = (w < 0) ? CONNECTION_LIMIT_UNLIMITED : (int)w; @@ -5198,9 +5198,9 @@ no_params: static int jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { struct command *c = jim_to_command(interp); - Jim_GetOptInfo goi; + struct jim_getopt_info goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); goi.isconfigure = !strcmp(c->name, "configure"); if (goi.argc < 1) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, @@ -5241,8 +5241,8 @@ static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv { bool allow_defer = false; - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc > 1) { const char *cmd_name = Jim_GetString(argv[0], NULL); Jim_SetResultFormatted(goi.interp, @@ -5253,7 +5253,7 @@ static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv strcmp(Jim_GetString(argv[1], NULL), "allow-defer") == 0) { /* consume it */ Jim_Obj *obj; - int e = Jim_GetOpt_Obj(&goi, &obj); + int e = jim_getopt_obj(&goi, &obj); if (e != JIM_OK) return e; allow_defer = true; @@ -5337,8 +5337,8 @@ static int jim_target_poll(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc != 2) { Jim_WrongNumArgs(interp, 0, argv, @@ -5346,15 +5346,15 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return JIM_ERR; } - Jim_Nvp *n; - int e = Jim_GetOpt_Nvp(&goi, nvp_assert, &n); + struct jim_nvp *n; + int e = jim_getopt_nvp(&goi, nvp_assert, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_assert, 1); + jim_getopt_nvp_unknown(&goi, nvp_assert, 1); return e; } /* the halt or not param */ jim_wide a; - e = Jim_GetOpt_Wide(&goi, &a); + e = jim_getopt_wide(&goi, &a); if (e != JIM_OK) return e; @@ -5404,8 +5404,8 @@ static int jim_target_halt(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); /* params: statename timeoutmsecs */ if (goi.argc != 2) { @@ -5415,14 +5415,14 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a return JIM_ERR; } - Jim_Nvp *n; - int e = Jim_GetOpt_Nvp(&goi, nvp_target_state, &n); + struct jim_nvp *n; + int e = jim_getopt_nvp(&goi, nvp_target_state, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_target_state, 1); + jim_getopt_nvp_unknown(&goi, nvp_target_state, 1); return e; } jim_wide a; - e = Jim_GetOpt_Wide(&goi, &a); + e = jim_getopt_wide(&goi, &a); if (e != JIM_OK) return e; struct command_context *cmd_ctx = current_command_context(interp); @@ -5457,7 +5457,7 @@ COMMAND_HANDLER(handle_target_event_list) command_print(CMD, "------------------------- | " "----------------------------------------"); while (teap) { - Jim_Nvp *opt = Jim_Nvp_value2name_simple(nvp_target_event, teap->event); + struct jim_nvp *opt = jim_nvp_value2name_simple(nvp_target_event, teap->event); command_print(CMD, "%-25s | %s", opt->name, Jim_GetString(teap->body, NULL)); teap = teap->next; @@ -5479,17 +5479,17 @@ static int jim_target_current_state(Jim_Interp *interp, int argc, Jim_Obj *const } static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc != 1) { const char *cmd_name = Jim_GetString(argv[0], NULL); Jim_SetResultFormatted(goi.interp, "%s ", cmd_name); return JIM_ERR; } - Jim_Nvp *n; - int e = Jim_GetOpt_Nvp(&goi, nvp_target_event, &n); + struct jim_nvp *n; + int e = jim_getopt_nvp(&goi, nvp_target_event, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_target_event, 1); + jim_getopt_nvp_unknown(&goi, nvp_target_event, 1); return e; } struct command_context *cmd_ctx = current_command_context(interp); @@ -5658,7 +5658,7 @@ static const struct command_registration target_instance_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -static int target_create(Jim_GetOptInfo *goi) +static int target_create(struct jim_getopt_info *goi) { Jim_Obj *new_cmd; Jim_Cmd *cmd; @@ -5677,7 +5677,7 @@ static int target_create(Jim_GetOptInfo *goi) } /* COMMAND */ - Jim_GetOpt_Obj(goi, &new_cmd); + jim_getopt_obj(goi, &new_cmd); /* does this command exist? */ cmd = Jim_GetCommand(goi->interp, new_cmd, JIM_ERRMSG); if (cmd) { @@ -5687,7 +5687,7 @@ static int target_create(Jim_GetOptInfo *goi) } /* TYPE */ - e = Jim_GetOpt_String(goi, &cp, NULL); + e = jim_getopt_string(goi, &cp, NULL); if (e != JIM_OK) return e; struct transport *tr = get_current_transport(); @@ -5991,8 +5991,8 @@ static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_target_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - Jim_GetOptInfo goi; - Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); + struct jim_getopt_info goi; + jim_getopt_setup(&goi, interp, argc - 1, argv + 1); if (goi.argc < 3) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, " [ ...]"); diff --git a/src/target/target_type.h b/src/target/target_type.h index 1948121..cc51c04 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -210,11 +210,11 @@ struct target_type { /* called for various config parameters */ /* returns JIM_CONTINUE - if option not understood */ /* otherwise: JIM_OK, or JIM_ERR, */ - int (*target_jim_configure)(struct target *target, Jim_GetOptInfo *goi); + int (*target_jim_configure)(struct target *target, struct jim_getopt_info *goi); /* target commands specifically handled by the target */ /* returns JIM_OK, or JIM_ERR, or JIM_CONTINUE - if option not understood */ - int (*target_jim_commands)(struct target *target, Jim_GetOptInfo *goi); + int (*target_jim_commands)(struct target *target, struct jim_getopt_info *goi); /** * This method is used to perform target setup that requires -- cgit v1.1 From fad1eaaa42ad5a52d1d9e38b1e94ab027fad5b24 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 27 May 2021 15:25:43 +0200 Subject: server/telnet: fix autocomplete for jimtcl commands Current autocomplete filters-out some command reported by "info commands". One of the filter rule concerns the command's private data. Every command registered by OpenOCD has its 'struct command' as private data. By ignoring commands without private data, we loose several TCL commands registered by jimtcl, e.g. 'foreach', 'llength'. By assuming that every command with non-NULL private data has 'struct command' as private data, we risk at best to access inconsistent data, at worst to trigger a segmentation fault. Export the already available functions: - to check if a command has been registered by OpenOCD and - to get the private data. While there, rename jimcmd_is_ocd_command() as jimcmd_is_oocd_command(). Don't filter-out jimtcl commands with no private data. Check the private data only on OpenOCD commands. Change-Id: Ib5bf8d2bc5c12440c0cfae438f637c38724a79b7 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6282 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI --- src/helper/command.c | 8 ++++---- src/helper/command.h | 11 +++++++++++ src/server/telnet_server.c | 26 +++++++++++--------------- 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/src/helper/command.c b/src/helper/command.c index d4f6a0a..43c5a0f 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -62,12 +62,12 @@ static inline bool jimcmd_is_proc(Jim_Cmd *cmd) return cmd->isproc; } -static inline bool jimcmd_is_ocd_command(Jim_Cmd *cmd) +bool jimcmd_is_oocd_command(Jim_Cmd *cmd) { return !cmd->isproc && cmd->u.native.cmdProc == jim_command_dispatch; } -static inline void *jimcmd_privdata(Jim_Cmd *cmd) +void *jimcmd_privdata(Jim_Cmd *cmd) { return cmd->isproc ? NULL : cmd->u.native.privData; } @@ -261,7 +261,7 @@ static struct command *command_find_from_name(Jim_Interp *interp, const char *na Jim_IncrRefCount(jim_name); Jim_Cmd *cmd = Jim_GetCommand(interp, jim_name, JIM_NONE); Jim_DecrRefCount(interp, jim_name); - if (!cmd || jimcmd_is_proc(cmd) || !jimcmd_is_ocd_command(cmd)) + if (!cmd || jimcmd_is_proc(cmd) || !jimcmd_is_oocd_command(cmd)) return NULL; return jimcmd_privdata(cmd); @@ -1020,7 +1020,7 @@ static int jim_command_mode(Jim_Interp *interp, int argc, Jim_Obj *const *argv) Jim_Cmd *cmd = Jim_GetCommand(interp, s, JIM_NONE); Jim_DecrRefCount(interp, s); free(full_name); - if (!cmd || !(jimcmd_is_proc(cmd) || jimcmd_is_ocd_command(cmd))) { + if (!cmd || !(jimcmd_is_proc(cmd) || jimcmd_is_oocd_command(cmd))) { Jim_SetResultString(interp, "unknown", -1); return JIM_OK; } diff --git a/src/helper/command.h b/src/helper/command.h index 068df9d..719c94b 100644 --- a/src/helper/command.h +++ b/src/helper/command.h @@ -85,6 +85,17 @@ struct command_invocation { }; /** + * Return true if the command @c cmd is registered by OpenOCD. + */ +bool jimcmd_is_oocd_command(Jim_Cmd *cmd); + +/** + * Return the pointer to the command's private data specified during the + * registration of command @a cmd . + */ +void *jimcmd_privdata(Jim_Cmd *cmd); + +/** * Command handlers may be defined with more parameters than the base * set provided by command.c. This macro uses C99 magic to allow * defining all such derivative types using this macro. diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c index acb57ef..2ad3791 100644 --- a/src/server/telnet_server.c +++ b/src/server/telnet_server.c @@ -500,22 +500,18 @@ static void telnet_auto_complete(struct connection *connection) bool ignore_cmd = false; Jim_Cmd *jim_cmd = Jim_GetCommand(command_context->interp, elem, JIM_NONE); - if (!jim_cmd) + if (!jim_cmd) { + /* Why we are here? Let's ignore it! */ ignore_cmd = true; - else { - if (!jim_cmd->isproc) { - /* ignore commands without handler - * and those with COMMAND_CONFIG mode */ - /* FIXME it's better to use jimcmd_is_ocd_command(jim_cmd) - * or command_find_from_name(command_context->interp, name) */ - struct command *cmd = jim_cmd->u.native.privData; - if (!cmd) - ignore_cmd = true; - /* make Valgrind happy by checking that cmd is not NULL */ - else if (cmd != NULL && !cmd->handler && !cmd->jim_handler) - ignore_cmd = true; - else if (cmd != NULL && cmd->mode == COMMAND_CONFIG) - ignore_cmd = true; + } else if (jimcmd_is_oocd_command(jim_cmd)) { + struct command *cmd = jimcmd_privdata(jim_cmd); + + if (cmd && !cmd->handler && !cmd->jim_handler) { + /* Initial part of a multi-word command. Ignore it! */ + ignore_cmd = true; + } else if (cmd && cmd->mode == COMMAND_CONFIG) { + /* Not executable after config phase. Ignore it! */ + ignore_cmd = true; } } -- cgit v1.1 From 968f5082dd7304ba3d8f72f481f4f76886779ea9 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Wed, 26 May 2021 14:48:10 +0200 Subject: helper/list.h: align file to Linux v5.12 Main improvement is in the doxygen comments. Minimize the delta with kernel file. Skip the functions hlist_unhashed_lockless() and __list_del_clearprev() that are relevant only in kernel. Remove gcc extension "omitted conditional operand". Change-Id: I2e9ddb54cfe2fa5f7cf18f44726acd144e1f98b9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6276 Reviewed-by: Tested-by: jenkins Reviewed-by: Andreas Fritiofson --- src/helper/list.h | 568 +++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 431 insertions(+), 137 deletions(-) diff --git a/src/helper/list.h b/src/helper/list.h index 7f60464..0949636 100644 --- a/src/helper/list.h +++ b/src/helper/list.h @@ -1,26 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * The content of this file is mainly copied/inspired from Linux kernel + * code in include/linux/list.h, include/linux/types.h + * Last aligned with kernel v5.12: + * - skip the functions hlist_unhashed_lockless() and __list_del_clearprev() + * that are relevant only in kernel; + * - Remove non-standard GCC extension "omitted conditional operand" from + * list_prepare_entry; + * - expand READ_ONCE, WRITE_ONCE, smp_load_acquire, smp_store_release; + * - make comments compatible with doxygen. + */ + #ifndef OPENOCD_HELPER_LIST_H #define OPENOCD_HELPER_LIST_H /* begin local changes */ #include -#define prefetch(x) ((void)x) #define LIST_POISON1 NULL #define LIST_POISON2 NULL struct list_head { struct list_head *next, *prev; }; + struct hlist_head { struct hlist_node *first; }; + struct hlist_node { struct hlist_node *next, **pprev; }; /* end local changes */ /* - * Simple doubly linked list implementation. + * Circular doubly linked list implementation. * * Some of the internal functions ("__xxx") are useful when * manipulating whole lists rather than single entries, as @@ -31,36 +46,58 @@ struct hlist_node { #define LIST_HEAD_INIT(name) { &(name), &(name) } -#define LIST_HEAD(name) \ +#define LIST_HEAD(name) \ struct list_head name = LIST_HEAD_INIT(name) +/** + * INIT_LIST_HEAD - Initialize a list_head structure + * @param list list_head structure to be initialized. + * + * Initializes the list_head to point to itself. If it is a list header, + * the result is an empty list. + */ static inline void INIT_LIST_HEAD(struct list_head *list) { list->next = list; list->prev = list; } +#ifdef CONFIG_DEBUG_LIST +extern bool __list_add_valid(struct list_head *new, + struct list_head *prev, + struct list_head *next); +extern bool __list_del_entry_valid(struct list_head *entry); +#else +static inline bool __list_add_valid(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + return true; +} +static inline bool __list_del_entry_valid(struct list_head *entry) +{ + return true; +} +#endif + /* * Insert a new entry between two known consecutive entries. * * This is only for internal list manipulation where we know * the prev/next entries already! */ -#ifndef CONFIG_DEBUG_LIST static inline void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next) + struct list_head *prev, + struct list_head *next) { + if (!__list_add_valid(new, prev, next)) + return; + next->prev = new; new->next = next; new->prev = prev; prev->next = new; } -#else -extern void __list_add(struct list_head *new, - struct list_head *prev, - struct list_head *next); -#endif /** * list_add - add a new entry @@ -102,28 +139,28 @@ static inline void __list_del(struct list_head *prev, struct list_head *next) prev->next = next; } +/* Ignore kernel __list_del_clearprev() */ + +static inline void __list_del_entry(struct list_head *entry) +{ + if (!__list_del_entry_valid(entry)) + return; + + __list_del(entry->prev, entry->next); +} + /** * list_del - deletes entry from list. * @param entry the element to delete from the list. * Note: list_empty() on entry does not return true after this, the entry is * in an undefined state. */ -#ifndef CONFIG_DEBUG_LIST -static inline void __list_del_entry(struct list_head *entry) -{ - __list_del(entry->prev, entry->next); -} - static inline void list_del(struct list_head *entry) { - __list_del(entry->prev, entry->next); + __list_del_entry(entry); entry->next = LIST_POISON1; entry->prev = LIST_POISON2; } -#else -extern void __list_del_entry(struct list_head *entry); -extern void list_del(struct list_head *entry); -#endif /** * list_replace - replace old entry by new one @@ -133,7 +170,7 @@ extern void list_del(struct list_head *entry); * If @a old was empty, it will be overwritten. */ static inline void list_replace(struct list_head *old, - struct list_head *new) + struct list_head *new) { new->next = old->next; new->next->prev = new; @@ -141,14 +178,38 @@ static inline void list_replace(struct list_head *old, new->prev->next = new; } +/** + * list_replace_init - replace old entry by new one and initialize the old one + * @param old the element to be replaced + * @param new the new element to insert + * + * If @a old was empty, it will be overwritten. + */ static inline void list_replace_init(struct list_head *old, - struct list_head *new) + struct list_head *new) { list_replace(old, new); INIT_LIST_HEAD(old); } /** + * list_swap - replace entry1 with entry2 and re-add entry1 at entry2's position + * @param entry1 the location to place entry2 + * @param entry2 the location to place entry1 + */ +static inline void list_swap(struct list_head *entry1, + struct list_head *entry2) +{ + struct list_head *pos = entry2->prev; + + list_del(entry2); + list_replace(entry1, entry2); + if (pos == entry1) + pos = entry2; + list_add(entry1, pos); +} + +/** * list_del_init - deletes entry from list and reinitialize it. * @param entry the element to delete from the list. */ @@ -175,19 +236,53 @@ static inline void list_move(struct list_head *list, struct list_head *head) * @param head the head that will follow our entry */ static inline void list_move_tail(struct list_head *list, - struct list_head *head) + struct list_head *head) { __list_del_entry(list); list_add_tail(list, head); } /** + * list_bulk_move_tail - move a subsection of a list to its tail + * @param head the head that will follow our entry + * @param first the first entry to move + * @param last the last entry to move, can be the same as first + * + * Move all entries between @a first and including @a last before @a head. + * All three entries must belong to the same linked list. + */ +static inline void list_bulk_move_tail(struct list_head *head, + struct list_head *first, + struct list_head *last) +{ + first->prev->next = last->next; + last->next->prev = first->prev; + + head->prev->next = first; + first->prev = head->prev; + + last->next = head; + head->prev = last; +} + +/** + * list_is_first -- tests whether @a list is the first entry in list @a head + * @param list the entry to test + * @param head the head of the list + */ +static inline int list_is_first(const struct list_head *list, + const struct list_head *head) +{ + return list->prev == head; +} + +/** * list_is_last - tests whether @a list is the last entry in list @a head * @param list the entry to test * @param head the head of the list */ static inline int list_is_last(const struct list_head *list, - const struct list_head *head) + const struct list_head *head) { return list->next == head; } @@ -202,6 +297,24 @@ static inline int list_empty(const struct list_head *head) } /** + * list_del_init_careful - deletes entry from list and reinitialize it. + * @param entry the element to delete from the list. + * + * This is the same as list_del_init(), except designed to be used + * together with list_empty_careful() in a way to guarantee ordering + * of other memory operations. + * + * Any memory operations done before a list_del_init_careful() are + * guaranteed to be visible after a list_empty_careful() test. + */ +static inline void list_del_init_careful(struct list_head *entry) +{ + __list_del_entry(entry); + entry->prev = entry; + entry->next = entry; +} + +/** * list_empty_careful - tests whether a list is empty and not being modified * @param head the list to test * @@ -235,6 +348,24 @@ static inline void list_rotate_left(struct list_head *head) } /** + * list_rotate_to_front() - Rotate list to specific item. + * @param list The desired new front of the list. + * @param head The head of the list. + * + * Rotates list so that @a list becomes the new front of the list. + */ +static inline void list_rotate_to_front(struct list_head *list, + struct list_head *head) +{ + /* + * Deletes the list head from the list denoted by @a head and + * places it as the tail of @a list, this effectively rotates the + * list so that @a list is at the front. + */ + list_move_tail(head, list); +} + +/** * list_is_singular - tests whether a list has just one entry. * @param head the list to test. */ @@ -244,7 +375,7 @@ static inline int list_is_singular(const struct list_head *head) } static inline void __list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) + struct list_head *head, struct list_head *entry) { struct list_head *new_first = entry->next; list->next = head->next; @@ -270,12 +401,12 @@ static inline void __list_cut_position(struct list_head *list, * */ static inline void list_cut_position(struct list_head *list, - struct list_head *head, struct list_head *entry) + struct list_head *head, struct list_head *entry) { if (list_empty(head)) return; if (list_is_singular(head) && - (head->next != entry && head != entry)) + (head->next != entry && head != entry)) return; if (entry == head) INIT_LIST_HEAD(list); @@ -283,9 +414,39 @@ static inline void list_cut_position(struct list_head *list, __list_cut_position(list, head, entry); } +/** + * list_cut_before - cut a list into two, before given entry + * @param list a new list to add all removed entries + * @param head a list with entries + * @param entry an entry within head, could be the head itself + * + * This helper moves the initial part of @a head, up to but + * excluding @a entry, from @a head to @a list. You should pass + * in @a entry an element you know is on @a head. @a list should + * be an empty list or a list you do not care about losing + * its data. + * If @a entry == @a head, all entries on @a head are moved to + * @a list. + */ +static inline void list_cut_before(struct list_head *list, + struct list_head *head, + struct list_head *entry) +{ + if (head->next == entry) { + INIT_LIST_HEAD(list); + return; + } + list->next = head->next; + list->next->prev = list; + list->prev = entry->prev; + list->prev->next = list; + head->next = entry; + entry->prev = head; +} + static inline void __list_splice(const struct list_head *list, - struct list_head *prev, - struct list_head *next) + struct list_head *prev, + struct list_head *next) { struct list_head *first = list->next; struct list_head *last = list->prev; @@ -303,7 +464,7 @@ static inline void __list_splice(const struct list_head *list, * @param head the place to add it in the first list. */ static inline void list_splice(const struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) __list_splice(list, head, head->next); @@ -315,7 +476,7 @@ static inline void list_splice(const struct list_head *list, * @param head the place to add it in the first list. */ static inline void list_splice_tail(struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) __list_splice(list, head->prev, head); @@ -329,7 +490,7 @@ static inline void list_splice_tail(struct list_head *list, * The list at @a list is reinitialised */ static inline void list_splice_init(struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) { __list_splice(list, head, head->next); @@ -346,7 +507,7 @@ static inline void list_splice_init(struct list_head *list, * The list at @a list is reinitialised */ static inline void list_splice_tail_init(struct list_head *list, - struct list_head *head) + struct list_head *head) { if (!list_empty(list)) { __list_splice(list, head->prev, head); @@ -358,7 +519,7 @@ static inline void list_splice_tail_init(struct list_head *list, * list_entry - get the struct for this entry * @param ptr the &struct list_head pointer. * @param type the type of the struct this is embedded in. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. */ #define list_entry(ptr, type, member) \ container_of(ptr, type, member) @@ -367,7 +528,7 @@ static inline void list_splice_tail_init(struct list_head *list, * list_first_entry - get the first element from a list * @param ptr the list head to take the element from. * @param type the type of the struct this is embedded in. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Note, that list is expected to be not empty. */ @@ -375,26 +536,63 @@ static inline void list_splice_tail_init(struct list_head *list, list_entry((ptr)->next, type, member) /** + * list_last_entry - get the last element from a list + * @param ptr the list head to take the element from. + * @param type the type of the struct this is embedded in. + * @param member the name of the list_head within the struct. + * + * Note, that list is expected to be not empty. + */ +#define list_last_entry(ptr, type, member) \ + list_entry((ptr)->prev, type, member) + +/** + * list_first_entry_or_null - get the first element from a list + * @param ptr the list head to take the element from. + * @param type the type of the struct this is embedded in. + * @param member the name of the list_head within the struct. + * + * Note that if the list is empty, it returns NULL. + */ +#define list_first_entry_or_null(ptr, type, member) ({ \ + struct list_head *head__ = (ptr); \ + struct list_head *pos__ = head__->next; \ + pos__ != head__ ? list_entry(pos__, type, member) : NULL; \ +}) + +/** + * list_next_entry - get the next element in list + * @param pos the type * to cursor + * @param member the name of the list_head within the struct. + */ +#define list_next_entry(pos, member) \ + list_entry((pos)->member.next, typeof(*(pos)), member) + +/** + * list_prev_entry - get the prev element in list + * @param pos the type * to cursor + * @param member the name of the list_head within the struct. + */ +#define list_prev_entry(pos, member) \ + list_entry((pos)->member.prev, typeof(*(pos)), member) + +/** * list_for_each - iterate over a list * @param pos the &struct list_head to use as a loop cursor. * @param head the head for your list. */ #define list_for_each(pos, head) \ - for (pos = (head)->next; prefetch(pos->next), pos != (head); \ - pos = pos->next) + for (pos = (head)->next; pos != (head); pos = pos->next) /** - * __list_for_each - iterate over a list + * list_for_each_continue - continue iteration over a list * @param pos the &struct list_head to use as a loop cursor. * @param head the head for your list. * - * This variant differs from list_for_each() in that it's the - * simplest possible list iteration code, no prefetching is done. - * Use this for code that knows the list to be very short (empty - * or 1 entry) most of the time. + * Continue to iterate over a list, continuing after the current position. */ -#define __list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) +#define list_for_each_continue(pos, head) \ + for (pos = pos->next; pos != (head); pos = pos->next) /** * list_for_each_prev - iterate over a list backwards @@ -402,8 +600,7 @@ static inline void list_splice_tail_init(struct list_head *list, * @param head the head for your list. */ #define list_for_each_prev(pos, head) \ - for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ - pos = pos->prev) + for (pos = (head)->prev; pos != (head); pos = pos->prev) /** * list_for_each_safe - iterate over a list safe against removal of list entry @@ -413,7 +610,7 @@ static inline void list_splice_tail_init(struct list_head *list, */ #define list_for_each_safe(pos, n, head) \ for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) + pos = n, n = pos->next) /** * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry @@ -422,148 +619,170 @@ static inline void list_splice_tail_init(struct list_head *list, * @param head the head for your list. */ #define list_for_each_prev_safe(pos, n, head) \ - for (pos = (head)->prev, n = pos->prev; \ - prefetch(pos->prev), pos != (head); \ + for (pos = (head)->prev, n = pos->prev; \ + pos != (head); \ pos = n, n = pos->prev) /** + * list_entry_is_head - test if the entry points to the head of the list + * @param pos the type * to cursor + * @param head the head for your list. + * @param member the name of the list_head within the struct. + */ +#define list_entry_is_head(pos, head, member) \ + (&pos->member == (head)) + +/** * list_for_each_entry - iterate over list of given type * @param pos the type * to use as a loop cursor. * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. */ #define list_for_each_entry(pos, head, member) \ - for (pos = list_entry((head)->next, typeof(*pos), member); \ - prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) + for (pos = list_first_entry(head, typeof(*pos), member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) /** * list_for_each_entry_reverse - iterate backwards over list of given type. * @param pos the type * to use as a loop cursor. * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. */ #define list_for_each_entry_reverse(pos, head, member) \ - for (pos = list_entry((head)->prev, typeof(*pos), member); \ - prefetch(pos->member.prev), &pos->member != (head); \ - pos = list_entry(pos->member.prev, typeof(*pos), member)) + for (pos = list_last_entry(head, typeof(*pos), member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_prev_entry(pos, member)) /** * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() * @param pos the type * to use as a start point * @param head the head of the list - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). */ #define list_prepare_entry(pos, head, member) \ - ((pos) ? : list_entry(head, typeof(*pos), member)) + ((pos) ? (pos) : list_entry(head, typeof(*pos), member)) /** * list_for_each_entry_continue - continue iteration over list of given type * @param pos the type * to use as a loop cursor. * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Continue to iterate over list of given type, continuing after * the current position. */ -#define list_for_each_entry_continue(pos, head, member) \ - for (pos = list_entry(pos->member.next, typeof(*pos), member); \ - prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_next_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) /** * list_for_each_entry_continue_reverse - iterate backwards from the given point * @param pos the type * to use as a loop cursor. * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Start to iterate over list of given type backwards, continuing after * the current position. */ #define list_for_each_entry_continue_reverse(pos, head, member) \ - for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ - prefetch(pos->member.prev), &pos->member != (head); \ - pos = list_entry(pos->member.prev, typeof(*pos), member)) + for (pos = list_prev_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_prev_entry(pos, member)) /** * list_for_each_entry_from - iterate over list of given type from the current point * @param pos the type * to use as a loop cursor. * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Iterate over list of given type, continuing from current position. */ #define list_for_each_entry_from(pos, head, member) \ - for (; prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) + for (; !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) + +/** + * list_for_each_entry_from_reverse - iterate backwards over list of given type + * from the current point + * @param pos the type * to use as a loop cursor. + * @param head the head for your list. + * @param member the name of the list_head within the struct. + * + * Iterate backwards over list of given type, continuing from current position. + */ +#define list_for_each_entry_from_reverse(pos, head, member) \ + for (; !list_entry_is_head(pos, head, member); \ + pos = list_prev_entry(pos, member)) /** * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry * @param pos the type * to use as a loop cursor. * @param n another type * to use as temporary storage * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. */ #define list_for_each_entry_safe(pos, n, head, member) \ - for (pos = list_entry((head)->next, typeof(*pos), member), \ - n = list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = list_entry(n->member.next, typeof(*n), member)) + for (pos = list_first_entry(head, typeof(*pos), member), \ + n = list_next_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = n, n = list_next_entry(n, member)) /** * list_for_each_entry_safe_continue - continue list iteration safe against removal * @param pos the type * to use as a loop cursor. * @param n another type * to use as temporary storage * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Iterate over list of given type, continuing after current point, * safe against removal of list entry. */ -#define list_for_each_entry_safe_continue(pos, n, head, member) \ - for (pos = list_entry(pos->member.next, typeof(*pos), member), \ - n = list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = list_entry(n->member.next, typeof(*n), member)) +#define list_for_each_entry_safe_continue(pos, n, head, member) \ + for (pos = list_next_entry(pos, member), \ + n = list_next_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = n, n = list_next_entry(n, member)) /** * list_for_each_entry_safe_from - iterate over list from current point safe against removal * @param pos the type * to use as a loop cursor. * @param n another type * to use as temporary storage * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Iterate over list of given type from current point, safe against * removal of list entry. */ #define list_for_each_entry_safe_from(pos, n, head, member) \ - for (n = list_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = list_entry(n->member.next, typeof(*n), member)) + for (n = list_next_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = n, n = list_next_entry(n, member)) /** * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal * @param pos the type * to use as a loop cursor. * @param n another type * to use as temporary storage * @param head the head for your list. - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * Iterate backwards over list of given type, safe against removal * of list entry. */ #define list_for_each_entry_safe_reverse(pos, n, head, member) \ - for (pos = list_entry((head)->prev, typeof(*pos), member), \ - n = list_entry(pos->member.prev, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = list_entry(n->member.prev, typeof(*n), member)) + for (pos = list_last_entry(head, typeof(*pos), member), \ + n = list_prev_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = n, n = list_prev_entry(n, member)) /** * list_safe_reset_next - reset a stale list_for_each_entry_safe loop * @param pos the loop cursor used in the list_for_each_entry_safe loop * @param n temporary storage used in list_for_each_entry_safe - * @param member the name of the list_struct within the struct. + * @param member the name of the list_head within the struct. * * list_safe_reset_next is not safe to use in general if the list may be * modified concurrently (eg. the lock is dropped in the loop body). An @@ -572,7 +791,7 @@ static inline void list_splice_tail_init(struct list_head *list, * completing the current iteration of the loop body. */ #define list_safe_reset_next(pos, n, member) \ - n = list_entry(pos->member.next, typeof(*pos), member) + n = list_next_entry(pos, member) /* * Double linked lists with a single pointer list head. @@ -590,11 +809,25 @@ static inline void INIT_HLIST_NODE(struct hlist_node *h) h->pprev = NULL; } +/** + * hlist_unhashed - Has node been removed from list and reinitialized? + * @param h Node to be checked + * + * Not that not all removal functions will leave a node in unhashed + * state. For example, hlist_nulls_del_init_rcu() does leave the + * node in unhashed state, but hlist_nulls_del() does not. + */ static inline int hlist_unhashed(const struct hlist_node *h) { return !h->pprev; } +/* Ignore kernel hlist_unhashed_lockless() */ + +/** + * hlist_empty - Is the specified hlist_head structure an empty hlist? + * @param h Structure to check. + */ static inline int hlist_empty(const struct hlist_head *h) { return !h->first; @@ -604,11 +837,19 @@ static inline void __hlist_del(struct hlist_node *n) { struct hlist_node *next = n->next; struct hlist_node **pprev = n->pprev; + *pprev = next; if (next) next->pprev = pprev; } +/** + * hlist_del - Delete the specified hlist_node from its list + * @param n Node to delete. + * + * Note that this function leaves the node in hashed state. Use + * hlist_del_init() or similar instead to unhash @a n. + */ static inline void hlist_del(struct hlist_node *n) { __hlist_del(n); @@ -616,6 +857,12 @@ static inline void hlist_del(struct hlist_node *n) n->pprev = LIST_POISON2; } +/** + * hlist_del_init - Delete the specified hlist_node from its list and initialize + * @param n Node to delete. + * + * Note that this function leaves the node in unhashed state. + */ static inline void hlist_del_init(struct hlist_node *n) { if (!hlist_unhashed(n)) { @@ -624,6 +871,14 @@ static inline void hlist_del_init(struct hlist_node *n) } } +/** + * hlist_add_head - add a new entry at the beginning of the hlist + * @param n new entry to be added + * @param h hlist head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) { struct hlist_node *first = h->first; @@ -634,9 +889,13 @@ static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) n->pprev = &h->first; } -/* next must be != NULL */ +/** + * hlist_add_before - add a new entry before the one specified + * @param n new entry to be added + * @param next hlist node to add it before, which must be non-NULL + */ static inline void hlist_add_before(struct hlist_node *n, - struct hlist_node *next) + struct hlist_node *next) { n->pprev = next->pprev; n->next = next; @@ -644,29 +903,68 @@ static inline void hlist_add_before(struct hlist_node *n, *(n->pprev) = n; } -static inline void hlist_add_after(struct hlist_node *n, - struct hlist_node *next) +/** + * hlist_add_behind - add a new entry after the one specified + * @param n new entry to be added + * @param prev hlist node to add it after, which must be non-NULL + */ +static inline void hlist_add_behind(struct hlist_node *n, + struct hlist_node *prev) { - next->next = n->next; - n->next = next; - next->pprev = &n->next; + n->next = prev->next; + prev->next = n; + n->pprev = &prev->next; - if (next->next) - next->next->pprev = &next->next; + if (n->next) + n->next->pprev = &n->next; } -/* after that we'll appear to be on some hlist and hlist_del will work */ +/** + * hlist_add_fake - create a fake hlist consisting of a single headless node + * @param n Node to make a fake list out of + * + * This makes @a n appear to be its own predecessor on a headless hlist. + * The point of this is to allow things like hlist_del() to work correctly + * in cases where there is no list. + */ static inline void hlist_add_fake(struct hlist_node *n) { n->pprev = &n->next; } -/* +/** + * hlist_fake: Is this node a fake hlist? + * @param h Node to check for being a self-referential fake hlist. + */ +static inline bool hlist_fake(struct hlist_node *h) +{ + return h->pprev == &h->next; +} + +/** + * hlist_is_singular_node - is node the only element of the specified hlist? + * @param n Node to check for singularity. + * @param h Header for potentially singular list. + * + * Check whether the node is the only node of the head without + * accessing head, thus avoiding unnecessary cache misses. + */ +static inline bool +hlist_is_singular_node(struct hlist_node *n, struct hlist_head *h) +{ + return !n->next && n->pprev == &h->first; +} + +/** + * hlist_move_list - Move an hlist + * @param old hlist_head for old list. + * @param new hlist_head for new list. + * * Move a list from one list head to another. Fixup the pprev * reference of the first entry if it exists. */ static inline void hlist_move_list(struct hlist_head *old, - struct hlist_head *new) + struct hlist_head *new) { new->first = old->first; if (new->first) @@ -677,61 +975,57 @@ static inline void hlist_move_list(struct hlist_head *old, #define hlist_entry(ptr, type, member) container_of(ptr, type, member) #define hlist_for_each(pos, head) \ - for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \ - pos = pos->next) + for (pos = (head)->first; pos ; pos = pos->next) #define hlist_for_each_safe(pos, n, head) \ for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ pos = n) +#define hlist_entry_safe(ptr, type, member) \ + ({ typeof(ptr) ____ptr = (ptr); \ + ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ + }) + /** * hlist_for_each_entry - iterate over list of given type - * @param tpos the type * to use as a loop cursor. - * @param pos the &struct hlist_node to use as a loop cursor. + * @param pos the type * to use as a loop cursor. * @param head the head for your list. * @param member the name of the hlist_node within the struct. */ -#define hlist_for_each_entry(tpos, pos, head, member) \ - for (pos = (head)->first; \ - pos && ({ prefetch(pos->next); 1; }) && \ - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \ - pos = pos->next) +#define hlist_for_each_entry(pos, head, member) \ + for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member);\ + pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) /** * hlist_for_each_entry_continue - iterate over a hlist continuing after current point - * @param tpos the type * to use as a loop cursor. - * @param pos the &struct hlist_node to use as a loop cursor. + * @param pos the type * to use as a loop cursor. * @param member the name of the hlist_node within the struct. */ -#define hlist_for_each_entry_continue(tpos, pos, member) \ - for (pos = (pos)->next; \ - pos && ({ prefetch(pos->next); 1; }) && \ - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \ - pos = pos->next) +#define hlist_for_each_entry_continue(pos, member) \ + for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\ + pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) /** * hlist_for_each_entry_from - iterate over a hlist continuing from current point - * @param tpos the type * to use as a loop cursor. - * @param pos the &struct hlist_node to use as a loop cursor. + * @param pos the type * to use as a loop cursor. * @param member the name of the hlist_node within the struct. */ -#define hlist_for_each_entry_from(tpos, pos, member) \ - for (; pos && ({ prefetch(pos->next); 1; }) && \ - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \ - pos = pos->next) +#define hlist_for_each_entry_from(pos, member) \ + for (; pos; \ + pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) /** * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @param tpos the type * to use as a loop cursor. - * @param pos the &struct hlist_node to use as a loop cursor. - * @param n another &struct hlist_node to use as temporary storage + * @param pos the type * to use as a loop cursor. + * @param n a &struct hlist_node to use as temporary storage * @param head the head for your list. * @param member the name of the hlist_node within the struct. */ -#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \ - for (pos = (head)->first; \ - pos && ({ n = pos->next; 1; }) && \ - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \ - pos = n) +#define hlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = hlist_entry_safe((head)->first, typeof(*pos), member);\ + pos && ({ n = pos->member.next; 1; }); \ + pos = hlist_entry_safe(n, typeof(*pos), member)) #endif /* OPENOCD_HELPER_LIST_H */ -- cgit v1.1 From 6b94d2983171b8421f841ecd0a4fd2d2aa98262e Mon Sep 17 00:00:00 2001 From: Andreas Fritiofson Date: Thu, 27 May 2021 09:45:28 +0200 Subject: contrib: add an example of using list.h Change-Id: Ic3d399d7ad2e4d10677cf78d64968040941b74e5 Signed-off-by: Andreas Fritiofson Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6280 Tested-by: jenkins Reviewed-by: Tim Newsome --- contrib/list_example.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 contrib/list_example.c diff --git a/contrib/list_example.c b/contrib/list_example.c new file mode 100644 index 0000000..0f62b86 --- /dev/null +++ b/contrib/list_example.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (C) 2021 by Andreas Fritiofson */ + +/* + * Simple example of using a circular doubly linked list through list.h + * + * gcc -I ../src/ list_example.c -o list_example + */ + +#include +#include +#include +#include + +static LIST_HEAD(threads); + +struct thread { + int id; + uint64_t tcb_address; + struct list_head lh; +}; + +void insert(struct thread *t) +{ + list_add_tail(&t->lh, &threads); +} + +void remove(struct thread *t) +{ + list_del(&t->lh); +} + +struct thread *lookup_id(int id) +{ + struct thread *t; + list_for_each_entry(t, &threads, lh) { + if (t->id == id) + return t; + } + return NULL; +} + +struct thread *lookup_tcb(uint64_t addr) +{ + struct thread *t; + list_for_each_entry(t, &threads, lh) { + if (t->tcb_address == addr) + return t; + } + return NULL; +} + +int main(void) +{ + struct thread t1 = { .id = 1, .tcb_address = 111111111 }; + struct thread t2 = { .id = 2, .tcb_address = 222222222 }; + struct thread t3 = { .id = 3, .tcb_address = 333333333 }; + + insert(&t1); + insert(&t2); + assert(lookup_id(1) == &t1); + assert(lookup_tcb(111111111) == &t1); + assert(lookup_id(2) == &t2); + assert(lookup_id(42) == NULL); + remove(&t1); + assert(lookup_id(1) == NULL); + insert(&t3); + remove(&t2); + assert(lookup_id(3) == &t3); + assert(lookup_tcb(333333333) == &t3); + assert(lookup_id(2) == NULL); + remove(&t3); + assert(list_empty(&threads)); +} -- cgit v1.1 From b9f4532eb76a987310bbc039230259ed175b8797 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 27 May 2021 14:21:13 +0200 Subject: helper/list.h: add mention to the example in contrib Without such reference, it could be difficult to find the example. Change-Id: Ia9ffb06bc1a45446c2c7b53197ab3400e1d8a9e9 Signed-off-by: Antonio Borneo Reviewed-on: http://openocd.zylin.com/6281 Tested-by: jenkins Reviewed-by: Tim Newsome --- src/helper/list.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/helper/list.h b/src/helper/list.h index 0949636..a7cd4ad 100644 --- a/src/helper/list.h +++ b/src/helper/list.h @@ -10,6 +10,8 @@ * list_prepare_entry; * - expand READ_ONCE, WRITE_ONCE, smp_load_acquire, smp_store_release; * - make comments compatible with doxygen. + * + * There is an example of using this file in contrib/list_example.c. */ #ifndef OPENOCD_HELPER_LIST_H -- cgit v1.1 From e74eaaacbcae8e8ec4063e0d058e2851d35a2af6 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Wed, 26 May 2021 16:10:39 +0100 Subject: tcl/target/stm32f4x: fix hardcoded chip name Fixes: c945d6e61605 ("tcl/target: start using the new TPIU/SWO support") Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6277 Reviewed-by: Antonio Borneo Tested-by: jenkins --- tcl/target/stm32f4x.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg index e94837f..2228de7 100644 --- a/tcl/target/stm32f4x.cfg +++ b/tcl/target/stm32f4x.cfg @@ -38,7 +38,7 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap stm32f4x.dap -ap-num 0 -baseaddr 0xE0040000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 -- cgit v1.1 From a8d3f601136ccfe446041631cb46a62922f46bca Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Thu, 13 May 2021 12:36:27 +0200 Subject: Makefile: add special target .DELETE_ON_ERROR The special .DELETE_ON_ERROR deletes the target file on recipe error. Otherwise, an incomplete output file may be considered up to date the next time around. .DELETE_ON_ERROR provides reasonable protection at virtually no cost. Signed-off-by: R. Diez Change-Id: I67dca47ae5ddf3786993c87b9991b3046a85f00b Reviewed-on: http://openocd.zylin.com/6235 Tested-by: jenkins Reviewed-by: Antonio Borneo --- Makefile.am | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.am b/Makefile.am index a047298..3858093 100644 --- a/Makefile.am +++ b/Makefile.am @@ -2,6 +2,8 @@ # have all needed files, that a GNU package needs AUTOMAKE_OPTIONS = gnu 1.6 +.DELETE_ON_ERROR: + # make sure we pass the correct jimtcl flags to distcheck DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim -- cgit v1.1 From 49820b8afd150af8df3c02c717d86b8d2cdf7cad Mon Sep 17 00:00:00 2001 From: Jan Matyas Date: Fri, 21 May 2021 08:02:29 +0200 Subject: gdb_server: Log both incoming and outgoing GDB packets - Made sure that also outgoing GDB packets are logged, not only the incoming ones. - Improved the treatment of non-printable characters in the packets to make it more robust. Prior to this change: - Outgoing packets were not printed unless OpenOCD was re-compiled with _DEBUG_GDB_IO_. - Non-prinable characters were only treated in incoming 'X' packets. After this change: - Both incoming and outgoing GDB packets are logged on debug_level >= 3, so that both directions of the GDB channel are visible. - Non-printable characters are checked for in every packet so that hey do not interfere with the terminal. Change-Id: I0613e57ae5059b3279b0abcb71276cf5719a8699 Signed-off-by: Jan Matyas Reviewed-on: http://openocd.zylin.com/6269 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/helper/log.c | 13 +++++++++++ src/helper/log.h | 2 ++ src/server/gdb_server.c | 61 +++++++++++++++++++++++++++++++++---------------- 3 files changed, 56 insertions(+), 20 deletions(-) diff --git a/src/helper/log.c b/src/helper/log.c index f5a8062..36b59fe 100644 --- a/src/helper/log.c +++ b/src/helper/log.c @@ -518,3 +518,16 @@ void log_socket_error(const char *socket_desc) LOG_ERROR("Error on socket '%s': errno==%d, message: %s.", socket_desc, error_code, strerror(error_code)); #endif } + +/** + * Find the first non-printable character in the char buffer, return a pointer to it. + * If no such character exists, return NULL. + */ +char *find_nonprint_char(char *buf, unsigned buf_len) +{ + for (unsigned int i = 0; i < buf_len; i++) { + if (!isprint(buf[i])) + return buf + i; + } + return NULL; +} diff --git a/src/helper/log.h b/src/helper/log.h index f2ba0da..34ff835 100644 --- a/src/helper/log.h +++ b/src/helper/log.h @@ -100,6 +100,8 @@ char *alloc_vprintf(const char *fmt, va_list ap); char *alloc_printf(const char *fmt, ...) __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 1, 2))); +char *find_nonprint_char(char *buf, unsigned buf_len); + extern int debug_level; /* Avoid fn call and building parameter list if we're not outputting the information. diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index 00c04e3..d0586d1 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -357,14 +357,50 @@ static int gdb_write(struct connection *connection, void *data, int len) return ERROR_SERVER_REMOTE_CLOSED; } +static void gdb_log_incoming_packet(char *packet) +{ + if (!LOG_LEVEL_IS(LOG_LVL_DEBUG)) + return; + + /* Avoid dumping non-printable characters to the terminal */ + const unsigned packet_len = strlen(packet); + const char *nonprint = find_nonprint_char(packet, packet_len); + if (nonprint) { + /* Does packet at least have a prefix that is printable? + * Look within the first 50 chars of the packet. */ + const char *colon = memchr(packet, ':', MIN(50, packet_len)); + const bool packet_has_prefix = (colon != NULL); + const bool packet_prefix_printable = (packet_has_prefix && nonprint > colon); + + if (packet_prefix_printable) { + const unsigned int prefix_len = colon - packet + 1; /* + 1 to include the ':' */ + const unsigned int payload_len = packet_len - prefix_len; + LOG_DEBUG("received packet: %.*s", prefix_len, packet, payload_len); + } else { + LOG_DEBUG("received packet: ", packet_len); + } + } else { + /* All chars printable, dump the packet as is */ + LOG_DEBUG("received packet: %s", packet); + } +} + +static void gdb_log_outgoing_packet(char *packet_buf, unsigned int packet_len, unsigned char checksum) +{ + if (!LOG_LEVEL_IS(LOG_LVL_DEBUG)) + return; + + if (find_nonprint_char(packet_buf, packet_len)) + LOG_DEBUG("sending packet: $#%2.2x", packet_len, checksum); + else + LOG_DEBUG("sending packet: $%.*s#%2.2x'", packet_len, packet_buf, checksum); +} + static int gdb_put_packet_inner(struct connection *connection, char *buffer, int len) { int i; unsigned char my_checksum = 0; -#ifdef _DEBUG_GDB_IO_ - char *debug_buffer; -#endif int reply; int retval; struct gdb_connection *gdb_con = connection->priv; @@ -400,11 +436,7 @@ static int gdb_put_packet_inner(struct connection *connection, #endif while (1) { -#ifdef _DEBUG_GDB_IO_ - debug_buffer = strndup(buffer, len); - LOG_DEBUG("sending packet '$%s#%2.2x'", debug_buffer, my_checksum); - free(debug_buffer); -#endif + gdb_log_outgoing_packet(buffer, len, my_checksum); char local_buffer[1024]; local_buffer[0] = '$'; @@ -3259,18 +3291,7 @@ static int gdb_input_inner(struct connection *connection) /* terminate with zero */ gdb_packet_buffer[packet_size] = '\0'; - if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) { - if (packet[0] == 'X') { - /* binary packets spew junk into the debug log stream */ - char buf[50]; - int x; - for (x = 0; (x < 49) && (packet[x] != ':'); x++) - buf[x] = packet[x]; - buf[x] = 0; - LOG_DEBUG("received packet: '%s:'", buf); - } else - LOG_DEBUG("received packet: '%s'", packet); - } + gdb_log_incoming_packet(gdb_packet_buffer); if (packet_size > 0) { retval = ERROR_OK; -- cgit v1.1 From 11598cb1be82dcca7995b2b7823a13435079da4f Mon Sep 17 00:00:00 2001 From: micbis Date: Mon, 10 May 2021 10:24:49 +0200 Subject: target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devices Initial support for Renesas RZ/G2 MPU family Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2 Signed-off-by: micbis Reviewed-on: http://openocd.zylin.com/6250 Tested-by: jenkins Reviewed-by: Antonio Borneo --- tcl/target/renesas_rz_g2.cfg | 185 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 tcl/target/renesas_rz_g2.cfg diff --git a/tcl/target/renesas_rz_g2.cfg b/tcl/target/renesas_rz_g2.cfg new file mode 100644 index 0000000..3615aa0 --- /dev/null +++ b/tcl/target/renesas_rz_g2.cfg @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/G2 SOCs +# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7 +# and Cortex-M33 for each SOC +# - Each SOC can boot through the Cortex-A5x cores + +# Supported RZ/G2 SOCs and their cores: +# RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7 +# RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7 +# RZ/G2N: Cortex-A57 x2, Cortex-R7 +# RZ/G2E: Cortex-A53 x2, Cortex-R7 +# RZ/G2L: Cortex-A55 x2, Cortex-M33 + +# Usage: +# There are 2 configuration options: +# SOC: Selects the supported SOC. (Default 'G2L') +# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55' + +transport select jtag +reset_config trst_and_srst srst_gates_jtag +adapter speed 4000 +adapter srst delay 500 + +if { [info exists SOC] } { + set _soc $SOC +} else { + set _soc G2L +} + +set _num_ca57 0 +set _num_ca55 0 +set _num_ca53 0 +set _num_cr7 0 +set _num_cm33 0 + +# Set configuration for each SOC and the default 'BOOT_CORE' +switch $_soc { + G2H { + set _CHIPNAME r8a774ex + set _num_ca57 4 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2M { + set _CHIPNAME r8a774ax + set _num_ca57 2 + set _num_ca53 4 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2N { + set _CHIPNAME r8a774bx + set _num_ca57 2 + set _num_ca53 0 + set _num_cr7 1 + set _boot_core CA57 + set _ap_num 1 + } + G2E { + set _CHIPNAME r8a774c0 + set _num_ca57 0 + set _num_ca53 2 + set _num_cr7 1 + set _boot_core CA53 + set _ap_num 1 + } + G2L { + set _CHIPNAME r9a07g044l + set _num_ca55 2 + set _num_cm33 1 + set _boot_core CA55 + set _ap_num 0 + } + default { + error "'$_soc' is invalid!" + } +} + +# If configured, override the default 'CHIPNAME' +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} + +# If configured, override the default 'BOOT_CORE' +if { [info exists BOOT_CORE] } { + set _boot_core $BOOT_CORE +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x6ba00477 +} + +echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \ + $_num_cm33 CM33(s)" +echo "\tBoot Core - $_boot_core\n" + +set _DAPNAME $_CHIPNAME.dap + + +# TAP and DAP +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \ + -ignore-version +dap create $_DAPNAME -chain-position $_CHIPNAME.cpu +echo "$_CHIPNAME.cpu" + +set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} +set CA55_DBGBASE {0x10E10000 0x10F10000} +set CA55_CTIBASE {0x10E20000 0x10F20000} +set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000} +set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} +set CR7_DBGBASE 0x80910000 +set CR7_CTIBASE 0x80918000 +set CM33_DBGBASE 0xE000E000 +set CM33_CTIBASE 0xE0042000 + +set smp_targets "" + +proc setup_a5x {core_name dbgbase ctibase num boot} { + for { set _core 0 } { $_core < $num } { incr _core } { + set _TARGETNAME $::_CHIPNAME.$core_name.$_core + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \ + -baseaddr [lindex $ctibase $_core] + target create $_TARGETNAME aarch64 -dap $::_DAPNAME \ + -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME + if { $_core > 0 || $boot == 0 } { + $_TARGETNAME configure -defer-examine + } + set ::smp_targets "$::smp_targets $_TARGETNAME" + } +} + +proc setup_cr7 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.r7 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase + target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \ + -ap-num 1 -dbgbase $dbgbase -defer-examine +} + +proc setup_cm33 {dbgbase ctibase} { + set _TARGETNAME $::_CHIPNAME.m33 + set _CTINAME $_TARGETNAME.cti + cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase + target create $_TARGETNAME cortex_m -dap $::_DAPNAME \ + -ap-num 2 -dbgbase $dbgbase -defer-examine +} + +# Organize target list based on the boot core +if { $_boot_core == "CA57" } { + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1 + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA53" } { + setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1 + setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0 + setup_cr7 $CR7_DBGBASE $CR7_CTIBASE +} elseif { $_boot_core == "CA55" } { + setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1 + setup_cm33 $CM33_DBGBASE $CM33_CTIBASE +} +echo "SMP targets:$smp_targets" +eval "target smp $smp_targets" + +if { $_soc == "G2L"} { + target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1 +} + +proc init_reset {mode} { + # Assert both resets: equivalent to a power-on reset + adapter assert trst assert srst + + # Deassert TRST to begin TAP communication + adapter deassert trst assert srst + + # TAP should now be responsive, validate the scan-chain + jtag arp_init +} -- cgit v1.1 From a9fb73a5b0b5bd3ac7b0e14a18b457009fe173f0 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Tue, 3 Nov 2020 14:09:37 +0100 Subject: drivers/jlink: Remove trailing dots This makes the messages consistent with most of the rest of the OpenOCD output. Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6274 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/jtag/drivers/jlink.c | 237 +++++++++++++++++++++++------------------------ 1 file changed, 117 insertions(+), 120 deletions(-) diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c index 8c1a811..6781e14 100644 --- a/src/jtag/drivers/jlink.c +++ b/src/jtag/drivers/jlink.c @@ -282,7 +282,7 @@ static int jlink_execute_command(struct jtag_command *cmd) jlink_execute_sleep(cmd); break; default: - LOG_ERROR("BUG: Unknown JTAG command type encountered."); + LOG_ERROR("BUG: Unknown JTAG command type encountered"); return ERROR_JTAG_QUEUE_FAILED; } @@ -316,7 +316,7 @@ static int jlink_speed(int speed) ret = jaylink_get_speeds(devh, &tmp); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_speeds() failed: %s.", + LOG_ERROR("jaylink_get_speeds() failed: %s", jaylink_strerror(ret)); return ERROR_JTAG_DEVICE_ERROR; } @@ -329,13 +329,13 @@ static int jlink_speed(int speed) if (!speed) { if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ADAPTIVE_CLOCKING)) { - LOG_ERROR("Adaptive clocking is not supported by the device."); + LOG_ERROR("Adaptive clocking is not supported by the device"); return ERROR_JTAG_NOT_IMPLEMENTED; } speed = JAYLINK_SPEED_ADAPTIVE_CLOCKING; } else if (speed > max_speed) { - LOG_INFO("Reduced speed from %d kHz to %d kHz (maximum).", speed, + LOG_INFO("Reduced speed from %d kHz to %d kHz (maximum)", speed, max_speed); speed = max_speed; } @@ -343,7 +343,7 @@ static int jlink_speed(int speed) ret = jaylink_set_speed(devh, speed); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_set_speed() failed: %s.", + LOG_ERROR("jaylink_set_speed() failed: %s", jaylink_strerror(ret)); return ERROR_JTAG_DEVICE_ERROR; } @@ -372,7 +372,7 @@ static bool read_device_config(struct device_config *cfg) ret = jaylink_read_raw_config(devh, (uint8_t *)cfg); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_read_raw_config() failed: %s.", + LOG_ERROR("jaylink_read_raw_config() failed: %s", jaylink_strerror(ret)); return false; } @@ -393,7 +393,7 @@ static int select_interface(void) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SELECT_TIF)) { if (iface != JAYLINK_TIF_JTAG) { - LOG_ERROR("Device supports JTAG transport only."); + LOG_ERROR("Device supports JTAG transport only"); return ERROR_JTAG_INIT_FAILED; } @@ -403,20 +403,20 @@ static int select_interface(void) ret = jaylink_get_available_interfaces(devh, &interfaces); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_available_interfaces() failed: %s.", + LOG_ERROR("jaylink_get_available_interfaces() failed: %s", jaylink_strerror(ret)); return ERROR_JTAG_INIT_FAILED; } if (!(interfaces & (1 << iface))) { - LOG_ERROR("Selected transport is not supported by the device."); + LOG_ERROR("Selected transport is not supported by the device"); return ERROR_JTAG_INIT_FAILED; } ret = jaylink_select_interface(devh, iface, NULL); if (ret < 0) { - LOG_ERROR("jaylink_select_interface() failed: %s.", + LOG_ERROR("jaylink_select_interface() failed: %s", jaylink_strerror(ret)); return ERROR_JTAG_INIT_FAILED; } @@ -437,7 +437,7 @@ static int jlink_register(void) ret = jaylink_register(devh, &conn, connlist, &count); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_register() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_register() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -452,7 +452,7 @@ static int jlink_register(void) if (!handle_found) { LOG_ERROR("Registration failed: maximum number of connections on the " - "device reached."); + "device reached"); return ERROR_FAIL; } @@ -475,13 +475,13 @@ static bool adjust_swd_buffer_size(void) ret = jaylink_get_free_memory(devh, &tmp); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_free_memory() failed: %s.", + LOG_ERROR("jaylink_get_free_memory() failed: %s", jaylink_strerror(ret)); return false; } if (tmp < 143) { - LOG_ERROR("Not enough free device internal memory: %" PRIu32 " bytes.", tmp); + LOG_ERROR("Not enough free device internal memory: %" PRIu32 " bytes", tmp); return false; } @@ -489,7 +489,7 @@ static bool adjust_swd_buffer_size(void) if (tmp != swd_buffer_size) { swd_buffer_size = tmp; - LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes.", + LOG_DEBUG("Adjusted SWD transaction buffer size to %u bytes", swd_buffer_size); } @@ -542,7 +542,7 @@ static bool jlink_usb_location_equal(struct jaylink_device *dev) if (retval == JAYLINK_ERR_NOT_SUPPORTED) { return false; } else if (retval != JAYLINK_OK) { - LOG_WARNING("jaylink_device_get_usb_bus_ports() failed: %s.", + LOG_WARNING("jaylink_device_get_usb_bus_ports() failed: %s", jaylink_strerror(retval)); return false; } @@ -558,7 +558,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) { int ret = jaylink_discovery_scan(jayctx, ifaces); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_discovery_scan() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_discovery_scan() failed: %s", jaylink_strerror(ret)); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; } @@ -568,7 +568,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) ret = jaylink_get_devices(jayctx, &devs, &num_devices); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_devices() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_get_devices() failed: %s", jaylink_strerror(ret)); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; } @@ -576,7 +576,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) use_usb_location = (jtag_usb_get_location() != NULL); if (!use_serial_number && !use_usb_address && !use_usb_location && num_devices > 1) { - LOG_ERROR("Multiple devices found, specify the desired device."); + LOG_ERROR("Multiple devices found, specify the desired device"); jaylink_free_devices(devs, true); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; @@ -594,7 +594,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) if (ret == JAYLINK_ERR_NOT_AVAILABLE) { continue; } else if (ret != JAYLINK_OK) { - LOG_WARNING("jaylink_device_get_serial_number() failed: %s.", + LOG_WARNING("jaylink_device_get_serial_number() failed: %s", jaylink_strerror(ret)); continue; } @@ -610,7 +610,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) if (ret == JAYLINK_ERR_NOT_SUPPORTED) { continue; } else if (ret != JAYLINK_OK) { - LOG_WARNING("jaylink_device_get_usb_address() failed: %s.", + LOG_WARNING("jaylink_device_get_usb_address() failed: %s", jaylink_strerror(ret)); continue; } @@ -629,7 +629,7 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device) break; } - LOG_ERROR("Failed to open device: %s.", jaylink_strerror(ret)); + LOG_ERROR("Failed to open device: %s", jaylink_strerror(ret)); } jaylink_free_devices(devs, true); @@ -645,25 +645,25 @@ static int jlink_init(void) struct jaylink_hardware_status hwstatus; size_t length; - LOG_DEBUG("Using libjaylink %s (compiled with %s).", + LOG_DEBUG("Using libjaylink %s (compiled with %s)", jaylink_version_package_get_string(), JAYLINK_VERSION_PACKAGE_STRING); if (!jaylink_library_has_cap(JAYLINK_CAP_HIF_USB) && use_usb_address) { - LOG_ERROR("J-Link driver does not support USB devices."); + LOG_ERROR("J-Link driver does not support USB devices"); return ERROR_JTAG_INIT_FAILED; } ret = jaylink_init(&jayctx); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_init() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_init() failed: %s", jaylink_strerror(ret)); return ERROR_JTAG_INIT_FAILED; } ret = jaylink_log_set_callback(jayctx, &jaylink_log_handler, NULL); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_log_set_callback() failed: %s.", + LOG_ERROR("jaylink_log_set_callback() failed: %s", jaylink_strerror(ret)); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; @@ -681,7 +681,7 @@ static int jlink_init(void) } if (!found_device) { - LOG_ERROR("No J-Link device found."); + LOG_ERROR("No J-Link device found"); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; } @@ -694,7 +694,7 @@ static int jlink_init(void) ret = jaylink_get_firmware_version(devh, &firmware_version, &length); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_firmware_version() failed: %s.", + LOG_ERROR("jaylink_get_firmware_version() failed: %s", jaylink_strerror(ret)); jaylink_close(devh); jaylink_exit(jayctx); @@ -703,14 +703,14 @@ static int jlink_init(void) LOG_INFO("%s", firmware_version); free(firmware_version); } else { - LOG_WARNING("Device responds empty firmware version string."); + LOG_WARNING("Device responds empty firmware version string"); } memset(caps, 0, JAYLINK_DEV_EXT_CAPS_SIZE); ret = jaylink_get_caps(devh, caps); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_caps() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_get_caps() failed: %s", jaylink_strerror(ret)); jaylink_close(devh); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; @@ -720,7 +720,7 @@ static int jlink_init(void) ret = jaylink_get_extended_caps(devh, caps); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_extended_caps() failed: %s.", + LOG_ERROR("jaylink_get_extended_caps() failed: %s", jaylink_strerror(ret)); jaylink_close(devh); jaylink_exit(jayctx); @@ -734,7 +734,7 @@ static int jlink_init(void) ret = jaylink_get_hardware_version(devh, &hwver); if (ret != JAYLINK_OK) { - LOG_ERROR("Failed to retrieve hardware version: %s.", + LOG_ERROR("Failed to retrieve hardware version: %s", jaylink_strerror(ret)); jaylink_close(devh); jaylink_exit(jayctx); @@ -763,7 +763,7 @@ static int jlink_init(void) if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { if (!read_device_config(&config)) { - LOG_ERROR("Failed to read device configuration data."); + LOG_ERROR("Failed to read device configuration data"); jaylink_close(devh); jaylink_exit(jayctx); return ERROR_JTAG_INIT_FAILED; @@ -775,7 +775,7 @@ static int jlink_init(void) ret = jaylink_get_hardware_status(devh, &hwstatus); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_hardware_status() failed: %s.", + LOG_ERROR("jaylink_get_hardware_status() failed: %s", jaylink_strerror(ret)); jaylink_close(devh); jaylink_exit(jayctx); @@ -837,14 +837,14 @@ static int jlink_quit(void) ret = jaylink_swo_stop(devh); if (ret != JAYLINK_OK) - LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_swo_stop() failed: %s", jaylink_strerror(ret)); } if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_REGISTER)) { ret = jaylink_unregister(devh, &conn, connlist, &count); if (ret != JAYLINK_OK) - LOG_ERROR("jaylink_unregister() failed: %s.", + LOG_ERROR("jaylink_unregister() failed: %s", jaylink_strerror(ret)); } @@ -892,7 +892,7 @@ static void jlink_path_move(int num_states, tap_state_t *path) else if (path[i] == tap_state_transition(tap_get_state(), true)) jlink_clock_data(NULL, 0, &tms, 0, NULL, 0, 1); else { - LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.", + LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_name(tap_get_state()), tap_state_name(path[i])); exit(-1); } @@ -935,7 +935,7 @@ static void jlink_runtest(int num_cycles) static void jlink_reset(int trst, int srst) { - LOG_DEBUG("TRST: %i, SRST: %i.", trst, srst); + LOG_DEBUG("TRST: %i, SRST: %i", trst, srst); /* Signals are active low. */ if (srst == 0) @@ -963,17 +963,17 @@ COMMAND_HANDLER(jlink_usb_command) int tmp; if (CMD_ARGC != 1) { - command_print(CMD, "Need exactly one argument for jlink usb."); + command_print(CMD, "Need exactly one argument for jlink usb"); return ERROR_COMMAND_SYNTAX_ERROR; } if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) { - command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); return ERROR_FAIL; } if (tmp < JAYLINK_USB_ADDRESS_0 || tmp > JAYLINK_USB_ADDRESS_3) { - command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); return ERROR_FAIL; } @@ -990,17 +990,17 @@ COMMAND_HANDLER(jlink_serial_command) int ret; if (CMD_ARGC != 1) { - command_print(CMD, "Need exactly one argument for jlink serial."); + command_print(CMD, "Need exactly one argument for jlink serial"); return ERROR_COMMAND_SYNTAX_ERROR; } ret = jaylink_parse_serial_number(CMD_ARGV[0], &serial_number); if (ret == JAYLINK_ERR) { - command_print(CMD, "Invalid serial number: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid serial number: %s", CMD_ARGV[0]); return ERROR_FAIL; } else if (ret != JAYLINK_OK) { - command_print(CMD, "jaylink_parse_serial_number() failed: %s.", + command_print(CMD, "jaylink_parse_serial_number() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1019,7 +1019,7 @@ COMMAND_HANDLER(jlink_handle_hwstatus_command) ret = jaylink_get_hardware_status(devh, &status); if (ret != JAYLINK_OK) { - command_print(CMD, "jaylink_get_hardware_status() failed: %s.", + command_print(CMD, "jaylink_get_hardware_status() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1032,7 +1032,7 @@ COMMAND_HANDLER(jlink_handle_hwstatus_command) status.tres, status.trst); if (status.target_voltage < 1500) - command_print(CMD, "Target voltage too low. Check target power."); + command_print(CMD, "Target voltage too low. Check target power"); return ERROR_OK; } @@ -1044,19 +1044,19 @@ COMMAND_HANDLER(jlink_handle_free_memory_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_FREE_MEMORY)) { command_print(CMD, "Retrieval of free memory is not supported by " - "the device."); + "the device"); return ERROR_OK; } ret = jaylink_get_free_memory(devh, &tmp); if (ret != JAYLINK_OK) { - command_print(CMD, "jaylink_get_free_memory() failed: %s.", + command_print(CMD, "jaylink_get_free_memory() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } - command_print(CMD, "Device has %" PRIu32 " bytes of free memory.", tmp); + command_print(CMD, "Device has %" PRIu32 " bytes of free memory", tmp); return ERROR_OK; } @@ -1081,7 +1081,7 @@ COMMAND_HANDLER(jlink_handle_jlink_jtag_command) command_print(CMD, "JTAG command version: %i", version); } else if (CMD_ARGC == 1) { if (sscanf(CMD_ARGV[0], "%i", &tmp) != 1) { - command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1093,11 +1093,11 @@ COMMAND_HANDLER(jlink_handle_jlink_jtag_command) jtag_command_version = JAYLINK_JTAG_VERSION_3; break; default: - command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; } } else { - command_print(CMD, "Need exactly one argument for jlink jtag."); + command_print(CMD, "Need exactly one argument for jlink jtag"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1110,14 +1110,13 @@ COMMAND_HANDLER(jlink_handle_target_power_command) int enable; if (CMD_ARGC != 1) { - command_print(CMD, "Need exactly one argument for jlink " - "targetpower."); + command_print(CMD, "Need exactly one argument for jlink targetpower"); return ERROR_COMMAND_SYNTAX_ERROR; } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { command_print(CMD, "Target power supply is not supported by the " - "device."); + "device"); return ERROR_OK; } @@ -1126,14 +1125,14 @@ COMMAND_HANDLER(jlink_handle_target_power_command) } else if (!strcmp(CMD_ARGV[0], "off")) { enable = false; } else { - command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); return ERROR_FAIL; } ret = jaylink_set_target_power(devh, enable); if (ret != JAYLINK_OK) { - command_print(CMD, "jaylink_set_target_power() failed: %s.", + command_print(CMD, "jaylink_set_target_power() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1240,7 +1239,7 @@ static int poll_trace(uint8_t *buf, size_t *size) ret = jaylink_swo_read(devh, buf, &length); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_swo_read() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_swo_read() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1260,7 +1259,7 @@ static uint32_t calculate_trace_buffer_size(void) ret = jaylink_get_free_memory(devh, &tmp); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_get_free_memory() failed: %s.", + LOG_ERROR("jaylink_get_free_memory() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1334,14 +1333,14 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol, if (!enabled) return ERROR_OK; - LOG_ERROR("Trace capturing is not supported by the device."); + LOG_ERROR("Trace capturing is not supported by the device"); return ERROR_FAIL; } ret = jaylink_swo_stop(devh); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_swo_stop() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1357,21 +1356,21 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol, } if (pin_protocol != TPIU_PIN_PROTOCOL_ASYNC_UART) { - LOG_ERROR("Selected pin protocol is not supported."); + LOG_ERROR("Selected pin protocol is not supported"); return ERROR_FAIL; } buffer_size = calculate_trace_buffer_size(); if (!buffer_size) { - LOG_ERROR("Not enough free device memory to start trace capturing."); + LOG_ERROR("Not enough free device memory to start trace capturing"); return ERROR_FAIL; } ret = jaylink_swo_get_speeds(devh, JAYLINK_SWO_MODE_UART, &speed); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_swo_get_speeds() failed: %s.", + LOG_ERROR("jaylink_swo_get_speeds() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } @@ -1382,49 +1381,49 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol, max_freq = speed.freq / speed.min_div; if (*trace_freq > max_freq) { - LOG_INFO("Given SWO frequency too high, using %" PRIu32 " Hz instead.", + LOG_INFO("Given SWO frequency too high, using %" PRIu32 " Hz instead", max_freq); *trace_freq = max_freq; } else if (*trace_freq < min_freq) { - LOG_INFO("Given SWO frequency too low, using %" PRIu32 " Hz instead.", + LOG_INFO("Given SWO frequency too low, using %" PRIu32 " Hz instead", min_freq); *trace_freq = min_freq; } else if (*trace_freq != speed.freq / divider) { *trace_freq = speed.freq / divider; LOG_INFO("Given SWO frequency is not supported by the device, " - "using %u Hz instead.", *trace_freq); + "using %u Hz instead", *trace_freq); } if (!calculate_swo_prescaler(traceclkin_freq, *trace_freq, prescaler)) { LOG_ERROR("SWO frequency is not suitable. Please choose a " - "different frequency or use auto-detection."); + "different frequency or use auto-detection"); return ERROR_FAIL; } } else { - LOG_INFO("Trying to auto-detect SWO frequency."); + LOG_INFO("Trying to auto-detect SWO frequency"); if (!detect_swo_freq_and_prescaler(speed, traceclkin_freq, trace_freq, prescaler)) { LOG_ERROR("Maximum permitted frequency deviation of %.02f %% " - "could not be achieved.", SWO_MAX_FREQ_DEV); - LOG_ERROR("Auto-detection of SWO frequency failed."); + "could not be achieved", SWO_MAX_FREQ_DEV); + LOG_ERROR("Auto-detection of SWO frequency failed"); return ERROR_FAIL; } - LOG_INFO("Using SWO frequency of %u Hz.", *trace_freq); + LOG_INFO("Using SWO frequency of %u Hz", *trace_freq); } ret = jaylink_swo_start(devh, JAYLINK_SWO_MODE_UART, *trace_freq, buffer_size); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_start_swo() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_start_swo() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } - LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing.", + LOG_DEBUG("Using %" PRIu32 " bytes device memory for trace capturing", buffer_size); /* @@ -1443,7 +1442,7 @@ COMMAND_HANDLER(jlink_handle_config_usb_address_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } @@ -1451,19 +1450,18 @@ COMMAND_HANDLER(jlink_handle_config_usb_address_command) show_config_usb_address(CMD); } else if (CMD_ARGC == 1) { if (sscanf(CMD_ARGV[0], "%" SCNd8, &tmp) != 1) { - command_print(CMD, "Invalid USB address: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid USB address: %s", CMD_ARGV[0]); return ERROR_FAIL; } if (tmp > JAYLINK_USB_ADDRESS_3) { - command_print(CMD, "Invalid USB address: %u.", tmp); + command_print(CMD, "Invalid USB address: %u", tmp); return ERROR_FAIL; } tmp_config.usb_address = tmp; } else { - command_print(CMD, "Need exactly one argument for jlink config " - "usb."); + command_print(CMD, "Need exactly one argument for jlink config usb"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1476,13 +1474,13 @@ COMMAND_HANDLER(jlink_handle_config_target_power_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SET_TARGET_POWER)) { command_print(CMD, "Target power supply is not supported by the " - "device."); + "device"); return ERROR_OK; } @@ -1494,14 +1492,14 @@ COMMAND_HANDLER(jlink_handle_config_target_power_command) } else if (!strcmp(CMD_ARGV[0], "off")) { enable = false; } else { - command_print(CMD, "Invalid argument: %s.", CMD_ARGV[0]); + command_print(CMD, "Invalid argument: %s", CMD_ARGV[0]); return ERROR_FAIL; } tmp_config.target_power = enable; } else { command_print(CMD, "Need exactly one argument for jlink config " - "targetpower."); + "targetpower"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1517,13 +1515,13 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ETHERNET)) { command_print(CMD, "Ethernet connectivity is not supported by the " - "device."); + "device"); return ERROR_OK; } @@ -1534,7 +1532,7 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command) if ((strlen(str) != 17) || (str[2] != ':' || str[5] != ':' || str[8] != ':' || str[11] != ':' || str[14] != ':')) { - command_print(CMD, "Invalid MAC address format."); + command_print(CMD, "Invalid MAC address format"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1544,19 +1542,18 @@ COMMAND_HANDLER(jlink_handle_config_mac_address_command) } if (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) { - command_print(CMD, "Invalid MAC address: zero address."); + command_print(CMD, "Invalid MAC address: zero address"); return ERROR_COMMAND_SYNTAX_ERROR; } if (!(0x01 & addr[0])) { - command_print(CMD, "Invalid MAC address: multicast address."); + command_print(CMD, "Invalid MAC address: multicast address"); return ERROR_COMMAND_SYNTAX_ERROR; } memcpy(tmp_config.mac_address, addr, sizeof(addr)); } else { - command_print(CMD, "Need exactly one argument for jlink config " - " mac."); + command_print(CMD, "Need exactly one argument for jlink config mac"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1605,13 +1602,13 @@ COMMAND_HANDLER(jlink_handle_config_ip_address_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_ETHERNET)) { command_print(CMD, "Ethernet connectivity is not supported by the " - "device."); + "device"); return ERROR_OK; } @@ -1662,44 +1659,44 @@ COMMAND_HANDLER(jlink_handle_config_write_command) if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { command_print(CMD, "Reading configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_WRITE_CONFIG)) { command_print(CMD, "Writing configuration is not supported by the " - "device."); + "device"); return ERROR_OK; } if (!memcmp(&config, &tmp_config, sizeof(struct device_config))) { command_print(CMD, "Operation not performed due to no changes in " - "the configuration."); + "the configuration"); return ERROR_OK; } ret = jaylink_write_raw_config(devh, (const uint8_t *)&tmp_config); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_write_raw_config() failed: %s.", + LOG_ERROR("jaylink_write_raw_config() failed: %s", jaylink_strerror(ret)); return ERROR_FAIL; } if (!read_device_config(&config)) { - LOG_ERROR("Failed to read device configuration for verification."); + LOG_ERROR("Failed to read device configuration for verification"); return ERROR_FAIL; } if (memcmp(&config, &tmp_config, sizeof(struct device_config))) { LOG_ERROR("Verification of device configuration failed. Please check " - "your device."); + "your device"); return ERROR_FAIL; } memcpy(&tmp_config, &config, sizeof(struct device_config)); command_print(CMD, "The new device configuration applies after power " - "cycling the J-Link device."); + "cycling the J-Link device"); return ERROR_OK; } @@ -1707,7 +1704,7 @@ COMMAND_HANDLER(jlink_handle_config_write_command) COMMAND_HANDLER(jlink_handle_config_command) { if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_READ_CONFIG)) { - command_print(CMD, "Device doesn't support reading configuration."); + command_print(CMD, "Device doesn't support reading configuration"); return ERROR_OK; } @@ -1730,7 +1727,7 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command) return ERROR_COMMAND_SYNTAX_ERROR; if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_EMUCOM)) { - LOG_ERROR("Device does not support EMUCOM."); + LOG_ERROR("Device does not support EMUCOM"); return ERROR_FAIL; } @@ -1739,21 +1736,21 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command) tmp = strlen(CMD_ARGV[1]); if (tmp % 2 != 0) { - LOG_ERROR("Data must be encoded as hexadecimal pairs."); + LOG_ERROR("Data must be encoded as hexadecimal pairs"); return ERROR_COMMAND_ARGUMENT_INVALID; } buf = malloc(tmp / 2); if (!buf) { - LOG_ERROR("Failed to allocate buffer."); + LOG_ERROR("Failed to allocate buffer"); return ERROR_FAIL; } dummy = unhexify(buf, CMD_ARGV[1], tmp / 2); if (dummy != (tmp / 2)) { - LOG_ERROR("Data must be encoded as hexadecimal pairs."); + LOG_ERROR("Data must be encoded as hexadecimal pairs"); free(buf); return ERROR_COMMAND_ARGUMENT_INVALID; } @@ -1764,15 +1761,15 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command) free(buf); if (ret == JAYLINK_ERR_DEV_NOT_SUPPORTED) { - LOG_ERROR("Channel not supported by the device."); + LOG_ERROR("Channel not supported by the device"); return ERROR_FAIL; } else if (ret != JAYLINK_OK) { - LOG_ERROR("Failed to write to channel: %s.", jaylink_strerror(ret)); + LOG_ERROR("Failed to write to channel: %s", jaylink_strerror(ret)); return ERROR_FAIL; } if (length != (tmp / 2)) - LOG_WARNING("Only %" PRIu32 " bytes written to the channel.", length); + LOG_WARNING("Only %" PRIu32 " bytes written to the channel", length); return ERROR_OK; } @@ -1789,7 +1786,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command) return ERROR_COMMAND_SYNTAX_ERROR; if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_EMUCOM)) { - LOG_ERROR("Device does not support EMUCOM."); + LOG_ERROR("Device does not support EMUCOM"); return ERROR_FAIL; } @@ -1799,23 +1796,23 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command) buf = malloc(length * 3 + 1); if (!buf) { - LOG_ERROR("Failed to allocate buffer."); + LOG_ERROR("Failed to allocate buffer"); return ERROR_FAIL; } ret = jaylink_emucom_read(devh, channel, buf, &length); if (ret == JAYLINK_ERR_DEV_NOT_SUPPORTED) { - LOG_ERROR("Channel is not supported by the device."); + LOG_ERROR("Channel is not supported by the device"); free(buf); return ERROR_FAIL; } else if (ret == JAYLINK_ERR_DEV_NOT_AVAILABLE) { LOG_ERROR("Channel is not available for the requested amount of data. " - "%" PRIu32 " bytes are available.", length); + "%" PRIu32 " bytes are available", length); free(buf); return ERROR_FAIL; } else if (ret != JAYLINK_OK) { - LOG_ERROR("Failed to read from channel: %s.", jaylink_strerror(ret)); + LOG_ERROR("Failed to read from channel: %s", jaylink_strerror(ret)); free(buf); return ERROR_FAIL; } @@ -1823,7 +1820,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command) tmp = hexify((char *)buf + length, buf, length, 2 * length + 1); if (tmp != 2 * length) { - LOG_ERROR("Failed to convert data into hexadecimal string."); + LOG_ERROR("Failed to convert data into hexadecimal string"); free(buf); return ERROR_FAIL; } @@ -2081,7 +2078,7 @@ static int jlink_flush(void) tap_length, jtag_command_version); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_jtag_io() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_jtag_io() failed: %s", jaylink_strerror(ret)); jlink_tap_init(); return ERROR_JTAG_QUEUE_FAILED; } @@ -2092,7 +2089,7 @@ static int jlink_flush(void) buf_set_buf(tdo_buffer, p->first, p->buffer, p->buffer_offset, p->length); - LOG_DEBUG_IO("Pending scan result, length = %d.", p->length); + LOG_DEBUG_IO("Pending scan result, length = %d", p->length); } jlink_tap_init(); @@ -2157,7 +2154,7 @@ static int jlink_swd_switch_seq(enum swd_special_seq seq) s_len = swd_seq_swd_to_jtag_len; break; default: - LOG_ERROR("Sequence %d not supported.", seq); + LOG_ERROR("Sequence %d not supported", seq); return ERROR_FAIL; } @@ -2171,10 +2168,10 @@ static int jlink_swd_run_queue(void) int i; int ret; - LOG_DEBUG("Executing %d queued transactions.", pending_scan_results_length); + LOG_DEBUG("Executing %d queued transactions", pending_scan_results_length); if (queued_retval != ERROR_OK) { - LOG_DEBUG("Skipping due to previous errors: %d.", queued_retval); + LOG_DEBUG("Skipping due to previous errors: %d", queued_retval); goto skip; } @@ -2187,7 +2184,7 @@ static int jlink_swd_run_queue(void) ret = jaylink_swd_io(devh, tms_buffer, tdi_buffer, tdo_buffer, tap_length); if (ret != JAYLINK_OK) { - LOG_ERROR("jaylink_swd_io() failed: %s.", jaylink_strerror(ret)); + LOG_ERROR("jaylink_swd_io() failed: %s", jaylink_strerror(ret)); goto skip; } @@ -2204,7 +2201,7 @@ static int jlink_swd_run_queue(void) int parity = buf_get_u32(tdo_buffer, 3 + 32 + pending_scan_results_buffer[i].first, 1); if (parity != parity_u32(data)) { - LOG_ERROR("SWD: Read data parity mismatch."); + LOG_ERROR("SWD: Read data parity mismatch"); queued_retval = ERROR_FAIL; goto skip; } -- cgit v1.1 From c4dd883c9a919b0b0a36bc538157820225b85610 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Mon, 17 May 2021 12:53:16 +0200 Subject: target: Use 'bool' for 'reset_halt' Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895 Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6262 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/target.c | 2 +- src/target/target.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/target.c b/src/target/target.c index 1547b29..39a07ad 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -5375,7 +5375,7 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) target_reset_examined(target); /* determine if we should halt or not. */ - target->reset_halt = !!a; + target->reset_halt = (a != 0); /* When this happens - all workareas are invalid. */ target_free_all_working_areas_restore(target, 0); diff --git a/src/target/target.h b/src/target/target.h index 046bd99..d86c63e 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -157,7 +157,7 @@ struct target { struct target_event_action *event_action; - int reset_halt; /* attempt resetting the CPU into the halted mode? */ + bool reset_halt; /* attempt resetting the CPU into the halted mode? */ target_addr_t working_area; /* working area (initialised RAM). Evaluated * upon first allocation from virtual/physical address. */ bool working_area_virt_spec; /* virtual address specified? */ -- cgit v1.1 From 6ae38ef7f7ff6fd51d4536ddf60d905ed6ac158e Mon Sep 17 00:00:00 2001 From: Adrian Negreanu Date: Wed, 19 May 2021 13:33:30 +0300 Subject: cmsis_dap: add support for swo commands Replaced mixed snake_case_CamelCase with snake_case. Define variables at first-use location. CMSIS-DAP SWO specification: https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html Change-Id: Ieba79b16efd445143f964b614673d041aae74f92 Signed-off-by: Adrian Negreanu Reviewed-on: http://openocd.zylin.com/5820 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/jtag/drivers/cmsis_dap.c | 532 +++++++++++++++++++++++++++++++++++-------- src/jtag/drivers/cmsis_dap.h | 2 + 2 files changed, 440 insertions(+), 94 deletions(-) diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c index c259375..4062ace 100644 --- a/src/jtag/drivers/cmsis_dap.c +++ b/src/jtag/drivers/cmsis_dap.c @@ -1,4 +1,7 @@ /*************************************************************************** + * Copyright (C) 2021 by Adrian Negreanu * + * groleo@gmail.com * + * * * Copyright (C) 2018 by MickaĆ«l Thomas * * mickael9@gmail.com * * * @@ -41,6 +44,7 @@ #include #include #include +#include #include "cmsis_dap.h" @@ -96,9 +100,12 @@ static bool swd_mode; #define INFO_ID_CAPS 0xf0 /* byte */ #define INFO_ID_PKT_CNT 0xfe /* byte */ #define INFO_ID_PKT_SZ 0xff /* short */ +#define INFO_ID_SWO_BUF_SZ 0xfd /* word */ -#define INFO_CAPS_SWD 0x01 -#define INFO_CAPS_JTAG 0x02 +#define INFO_CAPS_SWD BIT(0) +#define INFO_CAPS_JTAG BIT(1) +#define INFO_CAPS_SWO_UART BIT(2) +#define INFO_CAPS_SWO_MANCHESTER BIT(3) /* CMD_LED */ #define LED_ID_CONNECT 0x00 @@ -163,12 +170,44 @@ static bool swd_mode; #define DAP_OK 0 #define DAP_ERROR 0xFF +/* CMSIS-DAP SWO Commands */ +#define CMD_DAP_SWO_TRANSPORT 0x17 +#define CMD_DAP_SWO_MODE 0x18 +#define CMD_DAP_SWO_BAUDRATE 0x19 +#define CMD_DAP_SWO_CONTROL 0x1A +#define CMD_DAP_SWO_STATUS 0x1B +#define CMD_DAP_SWO_DATA 0x1C +#define CMD_DAP_SWO_EX_STATUS 0x1E + +/* SWO transport mode for reading trace data */ +#define DAP_SWO_TRANSPORT_NONE 0 +#define DAP_SWO_TRANSPORT_DATA 1 +#define DAP_SWO_TRANSPORT_WINUSB 2 + +/* SWO trace capture mode */ +#define DAP_SWO_MODE_OFF 0 +#define DAP_SWO_MODE_UART 1 +#define DAP_SWO_MODE_MANCHESTER 2 + +/* SWO trace data capture */ +#define DAP_SWO_CONTROL_STOP 0 +#define DAP_SWO_CONTROL_START 1 + +/* SWO trace status */ +#define DAP_SWO_STATUS_CAPTURE_INACTIVE 0 +#define DAP_SWO_STATUS_CAPTURE_ACTIVE 1 +#define DAP_SWO_STATUS_CAPTURE_MASK BIT(0) +#define DAP_SWO_STATUS_STREAM_ERROR_MASK BIT(6) +#define DAP_SWO_STATUS_BUFFER_OVERRUN_MASK BIT(7) + /* CMSIS-DAP Vendor Commands * None as yet... */ static const char * const info_caps_str[] = { "SWD Supported", - "JTAG Supported" + "JTAG Supported", + "SWO-UART Supported", + "SWO-MANCHESTER Supported" }; struct pending_transfer_result { @@ -338,9 +377,8 @@ static int cmsis_dap_xfer(struct cmsis_dap *dap, int txlen) return ERROR_OK; } -static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay, uint8_t *input) +static int cmsis_dap_cmd_dap_swj_pins(uint8_t pins, uint8_t mask, uint32_t delay, uint8_t *input) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_SWJ_PINS; @@ -348,8 +386,7 @@ static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay command[2] = mask; h_u32_to_le(&command[3], delay); - retval = cmsis_dap_xfer(cmsis_dap_handle, 7); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 7); if (retval != ERROR_OK) { LOG_ERROR("CMSIS-DAP command CMD_DAP_SWJ_PINS failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -361,9 +398,8 @@ static int cmsis_dap_cmd_DAP_SWJ_Pins(uint8_t pins, uint8_t mask, uint32_t delay return ERROR_OK; } -static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock) +static int cmsis_dap_cmd_dap_swj_clock(uint32_t swj_clock) { - int retval; uint8_t *command = cmsis_dap_handle->command; /* set clock in Hz */ @@ -372,8 +408,7 @@ static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock) command[0] = CMD_DAP_SWJ_CLOCK; h_u32_to_le(&command[1], swj_clock); - retval = cmsis_dap_xfer(cmsis_dap_handle, 5); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 5); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_DAP_SWJ_CLOCK failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -383,9 +418,8 @@ static int cmsis_dap_cmd_DAP_SWJ_Clock(uint32_t swj_clock) } /* clock a sequence of bits out on TMS, to change JTAG states */ -static int cmsis_dap_cmd_DAP_SWJ_Sequence(uint8_t s_len, const uint8_t *sequence) +static int cmsis_dap_cmd_dap_swj_sequence(uint8_t s_len, const uint8_t *sequence) { - int retval; uint8_t *command = cmsis_dap_handle->command; #ifdef CMSIS_DAP_JTAG_DEBUG @@ -400,23 +434,21 @@ static int cmsis_dap_cmd_DAP_SWJ_Sequence(uint8_t s_len, const uint8_t *sequence command[1] = s_len; bit_copy(&command[2], 0, sequence, 0, s_len); - retval = cmsis_dap_xfer(cmsis_dap_handle, 2 + DIV_ROUND_UP(s_len, 8)); + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2 + DIV_ROUND_UP(s_len, 8)); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) return ERROR_FAIL; return ERROR_OK; } -static int cmsis_dap_cmd_DAP_Info(uint8_t info, uint8_t **data) +static int cmsis_dap_cmd_dap_info(uint8_t info, uint8_t **data) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_INFO; command[1] = info; - retval = cmsis_dap_xfer(cmsis_dap_handle, 2); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); if (retval != ERROR_OK) { LOG_ERROR("CMSIS-DAP command CMD_INFO failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -427,17 +459,15 @@ static int cmsis_dap_cmd_DAP_Info(uint8_t info, uint8_t **data) return ERROR_OK; } -static int cmsis_dap_cmd_DAP_LED(uint8_t led, uint8_t state) +static int cmsis_dap_cmd_dap_led(uint8_t led, uint8_t state) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_LED; command[1] = led; command[2] = state; - retval = cmsis_dap_xfer(cmsis_dap_handle, 3); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 3); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_LED failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -446,16 +476,14 @@ static int cmsis_dap_cmd_DAP_LED(uint8_t led, uint8_t state) return ERROR_OK; } -static int cmsis_dap_cmd_DAP_Connect(uint8_t mode) +static int cmsis_dap_cmd_dap_connect(uint8_t mode) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_CONNECT; command[1] = mode; - retval = cmsis_dap_xfer(cmsis_dap_handle, 2); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); if (retval != ERROR_OK) { LOG_ERROR("CMSIS-DAP command CMD_CONNECT failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -469,15 +497,13 @@ static int cmsis_dap_cmd_DAP_Connect(uint8_t mode) return ERROR_OK; } -static int cmsis_dap_cmd_DAP_Disconnect(void) +static int cmsis_dap_cmd_dap_disconnect(void) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_DISCONNECT; - retval = cmsis_dap_xfer(cmsis_dap_handle, 1); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 1); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_DISCONNECT failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -486,9 +512,8 @@ static int cmsis_dap_cmd_DAP_Disconnect(void) return ERROR_OK; } -static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count, uint16_t match_retry) +static int cmsis_dap_cmd_dap_tfer_configure(uint8_t idle, uint16_t retry_count, uint16_t match_retry) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_TFER_CONFIGURE; @@ -496,8 +521,7 @@ static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count, h_u16_to_le(&command[2], retry_count); h_u16_to_le(&command[4], match_retry); - retval = cmsis_dap_xfer(cmsis_dap_handle, 6); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 6); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_TFER_Configure failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -506,16 +530,14 @@ static int cmsis_dap_cmd_DAP_TFER_Configure(uint8_t idle, uint16_t retry_count, return ERROR_OK; } -static int cmsis_dap_cmd_DAP_SWD_Configure(uint8_t cfg) +static int cmsis_dap_cmd_dap_swd_configure(uint8_t cfg) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_SWD_CONFIGURE; command[1] = cfg; - retval = cmsis_dap_xfer(cmsis_dap_handle, 2); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_SWD_Configure failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -525,16 +547,14 @@ static int cmsis_dap_cmd_DAP_SWD_Configure(uint8_t cfg) } #if 0 -static int cmsis_dap_cmd_DAP_Delay(uint16_t delay_us) +static int cmsis_dap_cmd_dap_delay(uint16_t delay_us) { - int retval; uint8_t *command = cmsis_dap_handle->command; command[0] = CMD_DAP_DELAY; h_u16_to_le(&command[1], delay_us); - retval = cmsis_dap_xfer(cmsis_dap_handle, 3); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, 3); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command CMD_Delay failed."); return ERROR_JTAG_DEVICE_ERROR; @@ -546,7 +566,6 @@ static int cmsis_dap_cmd_DAP_Delay(uint16_t delay_us) static int cmsis_dap_metacmd_targetsel(uint32_t instance_id) { - int retval; uint8_t *command = cmsis_dap_handle->command; const uint32_t SEQ_RD = 0x80, SEQ_WR = 0x00; @@ -574,12 +593,171 @@ static int cmsis_dap_metacmd_targetsel(uint32_t instance_id) idx += 4; command[idx++] = parity_u32(instance_id); - retval = cmsis_dap_xfer(cmsis_dap_handle, idx); - + int retval = cmsis_dap_xfer(cmsis_dap_handle, idx); if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { LOG_ERROR("CMSIS-DAP command SWD_Sequence failed."); return ERROR_JTAG_DEVICE_ERROR; } + + return ERROR_OK; +} + +/** + * Sets the SWO transport mode. + * @param[in] transport The transport mode. Can be None, SWO_Data or + * WinUSB (requires CMSIS-DAP v2). + */ +static int cmsis_dap_cmd_dap_swo_transport(uint8_t transport) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_TRANSPORT; + command[1] = transport; + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); + if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Transport(%d) failed.", transport); + return ERROR_JTAG_DEVICE_ERROR; + } + + return ERROR_OK; +} + +/** + * Sets the SWO trace capture mode. + * @param[in] mode Trace capture mode. Can be UART or MANCHESTER. + */ +static int cmsis_dap_cmd_dap_swo_mode(uint8_t mode) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_MODE; + command[1] = mode; + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); + if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Mode(%d) failed.", mode); + return ERROR_JTAG_DEVICE_ERROR; + } + + return ERROR_OK; +} + +/** + * Sets the baudrate for capturing SWO trace data. + * Can be called iteratively to determine supported baudrates. + * @param[in] in_baudrate Requested baudrate. + * @param[out] dev_baudrate Actual baudrate or 0 (baudrate not configured). + * When requested baudrate is not achievable the + * closest configured baudrate can be returned or + * 0 which indicates that baudrate was not configured. + */ +static int cmsis_dap_cmd_dap_swo_baudrate( + uint32_t in_baudrate, + uint32_t *dev_baudrate) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_BAUDRATE; + h_u32_to_le(&command[1], in_baudrate); + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 4); + uint32_t rvbr = le_to_h_u32(&cmsis_dap_handle->response[1]); + if (retval != ERROR_OK || rvbr == 0) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Baudrate(%u) -> %u failed.", in_baudrate, rvbr); + if (dev_baudrate) + *dev_baudrate = 0; + return ERROR_JTAG_DEVICE_ERROR; + } + + if (dev_baudrate) + *dev_baudrate = rvbr; + + return ERROR_OK; +} + +/** + * Controls the SWO trace data capture. + * @param[in] control Start or stop a trace. Starting capture automatically + * flushes any existing trace data in buffers which has + * not yet been read. + */ +static int cmsis_dap_cmd_dap_swo_control(uint8_t control) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_CONTROL; + command[1] = control; + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 2); + if (retval != ERROR_OK || cmsis_dap_handle->response[1] != DAP_OK) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Control(%d) failed.", control); + return ERROR_JTAG_DEVICE_ERROR; + } + + return ERROR_OK; +} + +/** + * Reads the SWO trace status. + * @param[out] trace_status The trace's status. + * Bit0: Trace Capture (1 - active, 0 - inactive). + * Bit6: Trace Stream Error. + * Bit7: Trace Buffer Overrun. + * @param[out] trace_count Number of bytes in Trace Buffer (not yet read). + */ +static int cmsis_dap_cmd_dap_swo_status( + uint8_t *trace_status, + size_t *trace_count) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_STATUS; + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 1); + if (retval != ERROR_OK) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Status failed."); + return ERROR_JTAG_DEVICE_ERROR; + } + + if (trace_status) + *trace_status = cmsis_dap_handle->response[1]; + if (trace_count) + *trace_count = le_to_h_u32(&cmsis_dap_handle->response[2]); + + return ERROR_OK; +} + +/** + * Reads the captured SWO trace data from Trace Buffer. + * @param[in] max_trace_count Maximum number of Trace Data bytes to read. + * @param[out] trace_status The trace's status. + * @param[out] trace_count Number of Trace Data bytes read. + * @param[out] data Trace Data bytes read. + */ +static int cmsis_dap_cmd_dap_swo_data( + size_t max_trace_count, + uint8_t *trace_status, + size_t *trace_count, + uint8_t *data) +{ + uint8_t *command = cmsis_dap_handle->command; + + command[0] = CMD_DAP_SWO_DATA; + h_u16_to_le(&command[1], max_trace_count); + + int retval = cmsis_dap_xfer(cmsis_dap_handle, 3); + if (retval != ERROR_OK) { + LOG_ERROR("CMSIS-DAP: command CMD_SWO_Data failed."); + return ERROR_JTAG_DEVICE_ERROR; + } + + *trace_status = cmsis_dap_handle->response[1]; + *trace_count = le_to_h_u16(&cmsis_dap_handle->response[2]); + + if (*trace_count > 0) + memcpy(data, &cmsis_dap_handle->response[4], *trace_count); + return ERROR_OK; } @@ -620,8 +798,8 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) * able to automatically retry anything (because ARM * has forgotten to implement sticky error flags * clearing). See also comments regarding - * cmsis_dap_cmd_DAP_TFER_Configure() and - * cmsis_dap_cmd_DAP_SWD_Configure() in + * cmsis_dap_cmd_dap_tfer_configure() and + * cmsis_dap_cmd_dap_swd_configure() in * cmsis_dap_init(). */ if (!(cmd & SWD_CMD_RnW) && @@ -640,7 +818,6 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap) } int retval = dap->backend->write(dap, idx, USB_TIMEOUT); - if (retval < 0) { queued_retval = retval; goto skip; @@ -805,7 +982,7 @@ static int cmsis_dap_get_serial_info(void) { uint8_t *data; - int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_SERNUM, &data); + int retval = cmsis_dap_cmd_dap_info(INFO_ID_SERNUM, &data); if (retval != ERROR_OK) return retval; @@ -820,7 +997,7 @@ static int cmsis_dap_get_version_info(void) uint8_t *data; /* INFO_ID_FW_VER - string */ - int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_FW_VER, &data); + int retval = cmsis_dap_cmd_dap_info(INFO_ID_FW_VER, &data); if (retval != ERROR_OK) return retval; @@ -835,7 +1012,7 @@ static int cmsis_dap_get_caps_info(void) uint8_t *data; /* INFO_ID_CAPS - byte */ - int retval = cmsis_dap_cmd_DAP_Info(INFO_ID_CAPS, &data); + int retval = cmsis_dap_cmd_dap_info(INFO_ID_CAPS, &data); if (retval != ERROR_OK) return retval; @@ -848,16 +1025,39 @@ static int cmsis_dap_get_caps_info(void) LOG_INFO("CMSIS-DAP: %s", info_caps_str[0]); if (caps & INFO_CAPS_JTAG) LOG_INFO("CMSIS-DAP: %s", info_caps_str[1]); + if (caps & INFO_CAPS_SWO_UART) + LOG_INFO("CMSIS-DAP: %s", info_caps_str[2]); + if (caps & INFO_CAPS_SWO_MANCHESTER) + LOG_INFO("CMSIS-DAP: %s", info_caps_str[3]); } return ERROR_OK; } +static int cmsis_dap_get_swo_buf_sz(uint32_t *swo_buf_sz) +{ + uint8_t *data; + + /* INFO_ID_SWO_BUF_SZ - word */ + int retval = cmsis_dap_cmd_dap_info(INFO_ID_SWO_BUF_SZ, &data); + if (retval != ERROR_OK) + return retval; + + if (data[0] != 4) + return ERROR_FAIL; + + *swo_buf_sz = le_to_h_u32(&data[1]); + + LOG_INFO("CMSIS-DAP: SWO Trace Buffer Size = %u bytes", *swo_buf_sz); + + return ERROR_OK; +} + static int cmsis_dap_get_status(void) { uint8_t d; - int retval = cmsis_dap_cmd_DAP_SWJ_Pins(0, 0, 0, &d); + int retval = cmsis_dap_cmd_dap_swj_pins(0, 0, 0, &d); if (retval == ERROR_OK) { LOG_INFO("SWCLK/TCK = %d SWDIO/TMS = %d TDI = %d TDO = %d nTRST = %d nRESET = %d", @@ -884,11 +1084,11 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq) * Reconnecting would break connecting under reset. */ /* First disconnect before connecting, Atmel EDBG needs it for SAMD/R/L/C */ - cmsis_dap_cmd_DAP_Disconnect(); + cmsis_dap_cmd_dap_disconnect(); /* When we are reconnecting, DAP_Connect needs to be rerun, at * least on Keil ULINK-ME */ - retval = cmsis_dap_cmd_DAP_Connect(CONNECT_SWD); + retval = cmsis_dap_cmd_dap_connect(CONNECT_SWD); if (retval != ERROR_OK) return retval; } @@ -929,25 +1129,23 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq) return ERROR_FAIL; } - retval = cmsis_dap_cmd_DAP_SWJ_Sequence(s_len, s); + retval = cmsis_dap_cmd_dap_swj_sequence(s_len, s); if (retval != ERROR_OK) return retval; /* Atmel EDBG needs renew clock setting after SWJ_Sequence * otherwise default frequency is used */ - return cmsis_dap_cmd_DAP_SWJ_Clock(jtag_get_speed_khz()); + return cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz()); } static int cmsis_dap_swd_open(void) { - int retval; - if (!(cmsis_dap_handle->caps & INFO_CAPS_SWD)) { LOG_ERROR("CMSIS-DAP: SWD not supported"); return ERROR_JTAG_DEVICE_ERROR; } - retval = cmsis_dap_cmd_DAP_Connect(CONNECT_SWD); + int retval = cmsis_dap_cmd_dap_connect(CONNECT_SWD); if (retval != ERROR_OK) return retval; @@ -959,10 +1157,9 @@ static int cmsis_dap_swd_open(void) static int cmsis_dap_init(void) { - int retval; uint8_t *data; - retval = cmsis_dap_open(); + int retval = cmsis_dap_open(); if (retval != ERROR_OK) return retval; @@ -991,7 +1188,7 @@ static int cmsis_dap_init(void) return ERROR_JTAG_DEVICE_ERROR; } - retval = cmsis_dap_cmd_DAP_Connect(CONNECT_JTAG); + retval = cmsis_dap_cmd_dap_connect(CONNECT_JTAG); if (retval != ERROR_OK) return retval; @@ -1004,7 +1201,7 @@ static int cmsis_dap_init(void) pending_queue_len = 12; /* INFO_ID_PKT_SZ - short */ - retval = cmsis_dap_cmd_DAP_Info(INFO_ID_PKT_SZ, &data); + retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_SZ, &data); if (retval != ERROR_OK) goto init_err; @@ -1027,7 +1224,7 @@ static int cmsis_dap_init(void) } /* INFO_ID_PKT_CNT - byte */ - retval = cmsis_dap_cmd_DAP_Info(INFO_ID_PKT_CNT, &data); + retval = cmsis_dap_cmd_dap_info(INFO_ID_PKT_CNT, &data); if (retval != ERROR_OK) goto init_err; @@ -1055,36 +1252,36 @@ static int cmsis_dap_init(void) /* Now try to connect to the target * TODO: This is all SWD only @ present */ - retval = cmsis_dap_cmd_DAP_SWJ_Clock(jtag_get_speed_khz()); + retval = cmsis_dap_cmd_dap_swj_clock(jtag_get_speed_khz()); if (retval != ERROR_OK) goto init_err; /* Ask CMSIS-DAP to automatically retry on receiving WAIT for * up to 64 times. This must be changed to 0 if sticky * overrun detection is enabled. */ - retval = cmsis_dap_cmd_DAP_TFER_Configure(0, 64, 0); + retval = cmsis_dap_cmd_dap_tfer_configure(0, 64, 0); if (retval != ERROR_OK) goto init_err; if (swd_mode) { /* Data Phase (bit 2) must be set to 1 if sticky overrun * detection is enabled */ - retval = cmsis_dap_cmd_DAP_SWD_Configure(0); /* 1 TRN, no Data Phase */ + retval = cmsis_dap_cmd_dap_swd_configure(0); /* 1 TRN, no Data Phase */ if (retval != ERROR_OK) goto init_err; } /* Both LEDs on */ /* Intentionally not checked for error, debugging will work * without LEDs */ - (void)cmsis_dap_cmd_DAP_LED(LED_ID_CONNECT, LED_ON); - (void)cmsis_dap_cmd_DAP_LED(LED_ID_RUN, LED_ON); + (void)cmsis_dap_cmd_dap_led(LED_ID_CONNECT, LED_ON); + (void)cmsis_dap_cmd_dap_led(LED_ID_RUN, LED_ON); /* support connecting with srst asserted */ enum reset_types jtag_reset_config = jtag_get_reset_config(); if (jtag_reset_config & RESET_CNCT_UNDER_SRST) { if (jtag_reset_config & RESET_SRST_NO_GATING) { - retval = cmsis_dap_cmd_DAP_SWJ_Pins(0, SWJ_PIN_SRST, 0, NULL); + retval = cmsis_dap_cmd_dap_swj_pins(0, SWJ_PIN_SRST, 0, NULL); if (retval != ERROR_OK) goto init_err; LOG_INFO("Connecting under reset"); @@ -1106,10 +1303,11 @@ static int cmsis_dap_swd_init(void) static int cmsis_dap_quit(void) { - cmsis_dap_cmd_DAP_Disconnect(); + cmsis_dap_cmd_dap_disconnect(); + /* Both LEDs off */ - cmsis_dap_cmd_DAP_LED(LED_ID_RUN, LED_OFF); - cmsis_dap_cmd_DAP_LED(LED_ID_CONNECT, LED_OFF); + cmsis_dap_cmd_dap_led(LED_ID_RUN, LED_OFF); + cmsis_dap_cmd_dap_led(LED_ID_CONNECT, LED_OFF); cmsis_dap_close(cmsis_dap_handle); @@ -1127,7 +1325,7 @@ static int cmsis_dap_reset(int trst, int srst) if (!trst) output_pins |= SWJ_PIN_TRST; - int retval = cmsis_dap_cmd_DAP_SWJ_Pins(output_pins, + int retval = cmsis_dap_cmd_dap_swj_pins(output_pins, SWJ_PIN_TRST | SWJ_PIN_SRST, 0, NULL); if (retval != ERROR_OK) LOG_ERROR("CMSIS-DAP: Interface reset failed"); @@ -1137,7 +1335,7 @@ static int cmsis_dap_reset(int trst, int srst) static void cmsis_dap_execute_sleep(struct jtag_command *cmd) { #if 0 - int retval = cmsis_dap_cmd_DAP_Delay(cmd->cmd.sleep->us); + int retval = cmsis_dap_cmd_dap_delay(cmd->cmd.sleep->us); if (retval != ERROR_OK) #endif jtag_sleep(cmd->cmd.sleep->us); @@ -1148,10 +1346,11 @@ static int cmsis_dap_execute_tlr_reset(struct jtag_command *cmd) { LOG_INFO("cmsis-dap JTAG TLR_RESET"); uint8_t seq = 0xff; - int ret = cmsis_dap_cmd_DAP_SWJ_Sequence(8, &seq); - if (ret == ERROR_OK) + + int retval = cmsis_dap_cmd_dap_swj_sequence(8, &seq); + if (retval == ERROR_OK) tap_set_state(TAP_RESET); - return ret; + return retval; } /* Set new end state */ @@ -1369,11 +1568,8 @@ static void cmsis_dap_add_tms_sequence(const uint8_t *sequence, int s_len) /* Move to the end state by queuing a sequence to clock into TMS */ static void cmsis_dap_state_move(void) { - uint8_t tms_scan; - uint8_t tms_scan_bits; - - tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state()); - tms_scan_bits = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); + uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state()); + uint8_t tms_scan_bits = tap_get_tms_path_len(tap_get_state(), tap_get_end_state()); LOG_DEBUG_IO("state move from %s to %s: %d clocks, %02X on tms", tap_state_name(tap_get_state()), tap_state_name(tap_get_end_state()), @@ -1488,11 +1684,10 @@ static void cmsis_dap_execute_scan(struct jtag_command *cmd) static void cmsis_dap_pathmove(int num_states, tap_state_t *path) { - int i; uint8_t tms0 = 0x00; uint8_t tms1 = 0xff; - for (i = 0; i < num_states; i++) { + for (int i = 0; i < num_states; i++) { if (path[i] == tap_state_transition(tap_get_state(), false)) cmsis_dap_add_tms_sequence(&tms0, 1); else if (path[i] == tap_state_transition(tap_get_state(), true)) @@ -1520,12 +1715,10 @@ static void cmsis_dap_execute_pathmove(struct jtag_command *cmd) static void cmsis_dap_stableclocks(int num_cycles) { - int i; - uint8_t tms = tap_get_state() == TAP_RESET; /* TODO: Perform optimizations? */ /* Execute num_cycles. */ - for (i = 0; i < num_cycles; i++) + for (int i = 0; i < num_cycles; i++) cmsis_dap_add_tms_sequence(&tms, 1); } @@ -1565,7 +1758,7 @@ static void cmsis_dap_execute_stableclocks(struct jtag_command *cmd) static void cmsis_dap_execute_tms(struct jtag_command *cmd) { LOG_DEBUG_IO("TMS: %d bits", cmd->cmd.tms->num_bits); - cmsis_dap_cmd_DAP_SWJ_Sequence(cmd->cmd.tms->num_bits, cmd->cmd.tms->bits); + cmsis_dap_cmd_dap_swj_sequence(cmd->cmd.tms->num_bits, cmd->cmd.tms->bits); } /* TODO: Is there need to call cmsis_dap_flush() for the JTAG_PATHMOVE, @@ -1623,7 +1816,7 @@ static int cmsis_dap_speed(int speed) return ERROR_JTAG_NOT_IMPLEMENTED; } - return cmsis_dap_cmd_DAP_SWJ_Clock(speed); + return cmsis_dap_cmd_dap_swj_clock(speed); } static int cmsis_dap_speed_div(int speed, int *khz) @@ -1638,6 +1831,157 @@ static int cmsis_dap_khz(int khz, int *jtag_speed) return ERROR_OK; } +static bool calculate_swo_prescaler(unsigned int traceclkin_freq, + uint32_t trace_freq, uint16_t *prescaler) +{ + unsigned int presc = (traceclkin_freq + trace_freq / 2) / trace_freq; + if (presc == 0 || presc > TPIU_ACPR_MAX_SWOSCALER + 1) + return false; + + /* Probe's UART speed must be within 3% of the TPIU's SWO baud rate. */ + unsigned int max_deviation = (traceclkin_freq * 3) / 100; + if (presc * trace_freq < traceclkin_freq - max_deviation || + presc * trace_freq > traceclkin_freq + max_deviation) + return false; + + *prescaler = presc; + + return true; +} + +/** + * @see adapter_driver::config_trace + */ +static int cmsis_dap_config_trace( + bool trace_enabled, + enum tpiu_pin_protocol pin_protocol, + uint32_t port_size, + unsigned int *swo_freq, + unsigned int traceclkin_hz, + uint16_t *swo_prescaler) +{ + int retval; + + if (!trace_enabled) { + if (cmsis_dap_handle->trace_enabled) { + retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_STOP); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to disable the SWO-trace."); + return retval; + } + } + cmsis_dap_handle->trace_enabled = false; + LOG_INFO("SWO-trace disabled."); + return ERROR_OK; + } + + if (!(cmsis_dap_handle->caps & INFO_CAPS_SWO_UART) && + !(cmsis_dap_handle->caps & INFO_CAPS_SWO_MANCHESTER)) { + LOG_ERROR("SWO-trace is not supported by the device."); + return ERROR_FAIL; + } + + uint8_t swo_mode; + if (pin_protocol == TPIU_PIN_PROTOCOL_ASYNC_UART && + (cmsis_dap_handle->caps & INFO_CAPS_SWO_UART)) { + swo_mode = DAP_SWO_MODE_UART; + } else if (pin_protocol == TPIU_PIN_PROTOCOL_ASYNC_MANCHESTER && + (cmsis_dap_handle->caps & INFO_CAPS_SWO_MANCHESTER)) { + swo_mode = DAP_SWO_MODE_MANCHESTER; + } else { + LOG_ERROR("Selected pin protocol is not supported."); + return ERROR_FAIL; + } + + if (*swo_freq == 0) { + LOG_INFO("SWO-trace frequency autodetection not implemented."); + return ERROR_FAIL; + } + + retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_STOP); + if (retval != ERROR_OK) + return retval; + + cmsis_dap_handle->trace_enabled = false; + + retval = cmsis_dap_get_swo_buf_sz(&cmsis_dap_handle->swo_buf_sz); + if (retval != ERROR_OK) + return retval; + + retval = cmsis_dap_cmd_dap_swo_transport(DAP_SWO_TRANSPORT_DATA); + if (retval != ERROR_OK) + return retval; + + retval = cmsis_dap_cmd_dap_swo_mode(swo_mode); + if (retval != ERROR_OK) + return retval; + + retval = cmsis_dap_cmd_dap_swo_baudrate(*swo_freq, swo_freq); + if (retval != ERROR_OK) + return retval; + + if (!calculate_swo_prescaler(traceclkin_hz, *swo_freq, + swo_prescaler)) { + LOG_ERROR("SWO frequency is not suitable. Please choose a " + "different frequency or use auto-detection."); + return ERROR_FAIL; + } + + LOG_INFO("SWO frequency: %u Hz.", *swo_freq); + LOG_INFO("SWO prescaler: %u.", *swo_prescaler); + + retval = cmsis_dap_cmd_dap_swo_control(DAP_SWO_CONTROL_START); + if (retval != ERROR_OK) + return retval; + + cmsis_dap_handle->trace_enabled = true; + + return ERROR_OK; +} + +/** + * @see adapter_driver::poll_trace + */ +static int cmsis_dap_poll_trace(uint8_t *buf, size_t *size) +{ + uint8_t trace_status; + size_t trace_count; + + if (!cmsis_dap_handle->trace_enabled) { + *size = 0; + return ERROR_OK; + } + + int retval = cmsis_dap_cmd_dap_swo_status(&trace_status, &trace_count); + if (retval != ERROR_OK) + return retval; + if ((trace_status & DAP_SWO_STATUS_CAPTURE_MASK) != DAP_SWO_STATUS_CAPTURE_ACTIVE) + return ERROR_FAIL; + + *size = trace_count < *size ? trace_count : *size; + size_t read_so_far = 0; + do { + size_t rb = 0; + uint32_t packet_size = cmsis_dap_handle->packet_size - 4 /*data-reply*/; + uint32_t remaining = *size - read_so_far; + if (remaining < packet_size) + packet_size = remaining; + retval = cmsis_dap_cmd_dap_swo_data( + packet_size, + &trace_status, + &rb, + &buf[read_so_far]); + if (retval != ERROR_OK) + return retval; + if ((trace_status & DAP_SWO_STATUS_CAPTURE_MASK) != DAP_SWO_STATUS_CAPTURE_ACTIVE) + return ERROR_FAIL; + + read_so_far += rb; + } while (read_so_far < *size); + + return ERROR_OK; +} + COMMAND_HANDLER(cmsis_dap_handle_info_command) { if (cmsis_dap_get_version_info() == ERROR_OK) @@ -1648,14 +1992,12 @@ COMMAND_HANDLER(cmsis_dap_handle_info_command) COMMAND_HANDLER(cmsis_dap_handle_cmd_command) { - int retval; - unsigned i; uint8_t *command = cmsis_dap_handle->command; - for (i = 0; i < CMD_ARGC; i++) + for (unsigned i = 0; i < CMD_ARGC; i++) command[i] = strtoul(CMD_ARGV[i], NULL, 16); - retval = cmsis_dap_xfer(cmsis_dap_handle, CMD_ARGC); + int retval = cmsis_dap_xfer(cmsis_dap_handle, CMD_ARGC); if (retval != ERROR_OK) { LOG_ERROR("CMSIS-DAP command failed."); @@ -1817,6 +2159,8 @@ struct adapter_driver cmsis_dap_adapter_driver = { .speed = cmsis_dap_speed, .khz = cmsis_dap_khz, .speed_div = cmsis_dap_speed_div, + .config_trace = cmsis_dap_config_trace, + .poll_trace = cmsis_dap_poll_trace, .jtag_ops = &cmsis_dap_interface, .swd_ops = &cmsis_dap_swd_driver, diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h index c9f24c8..634a62c 100644 --- a/src/jtag/drivers/cmsis_dap.h +++ b/src/jtag/drivers/cmsis_dap.h @@ -18,6 +18,8 @@ struct cmsis_dap { uint8_t *response; uint8_t caps; uint8_t mode; + uint32_t swo_buf_sz; + bool trace_enabled; }; struct cmsis_dap_backend { -- cgit v1.1 From 358ab3483d2cad0c869585f8a340154690f56569 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 13 May 2021 16:38:51 -0700 Subject: Add target_data_bits(). This is used to compute memory block read alignment, and specifically allows 64-bit targets to ensure that memory block reads are only requested on 64-bit boundaries. Signed-off-by: Tim Newsome Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817 Reviewed-on: http://openocd.zylin.com/6249 Reviewed-by: Marc Schink Tested-by: jenkins Reviewed-by: Jan Matyas Reviewed-by: Xiang W Reviewed-by: Antonio Borneo --- src/target/riscv/riscv.c | 9 +++++++++ src/target/target.c | 21 +++++++++++++++++---- src/target/target.h | 7 +++++++ src/target/target_type.h | 5 +++++ 4 files changed, 38 insertions(+), 4 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index fa07fe8..50535e2 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2813,6 +2813,14 @@ static unsigned riscv_xlen_nonconst(struct target *target) return riscv_xlen(target); } +static unsigned int riscv_data_bits(struct target *target) +{ + RISCV_INFO(r); + if (r->data_bits) + return r->data_bits(target); + return riscv_xlen(target); +} + struct target_type riscv_target = { .name = "riscv", @@ -2857,6 +2865,7 @@ struct target_type riscv_target = { .commands = riscv_command_handlers, .address_bits = riscv_xlen_nonconst, + .data_bits = riscv_data_bits }; /*** RISC-V Interface ***/ diff --git a/src/target/target.c b/src/target/target.c index 39a07ad..63f68eb 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -1506,6 +1506,13 @@ unsigned target_address_bits(struct target *target) return 32; } +unsigned int target_data_bits(struct target *target) +{ + if (target->type->data_bits) + return target->type->data_bits(target); + return 32; +} + static int target_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds) { @@ -2402,10 +2409,13 @@ static int target_write_buffer_default(struct target *target, target_addr_t address, uint32_t count, const uint8_t *buffer) { uint32_t size; + unsigned int data_bytes = target_data_bits(target) / 8; - /* Align up to maximum 4 bytes. The loop condition makes sure the next pass + /* Align up to maximum bytes. The loop condition makes sure the next pass * will have something to do with the size we leave to it. */ - for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) { + for (size = 1; + size < data_bytes && count >= size * 2 + (address & size); + size *= 2) { if (address & size) { int retval = target_write_memory(target, address, size, 1, buffer); if (retval != ERROR_OK) @@ -2463,10 +2473,13 @@ int target_read_buffer(struct target *target, target_addr_t address, uint32_t si static int target_read_buffer_default(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer) { uint32_t size; + unsigned int data_bytes = target_data_bits(target) / 8; - /* Align up to maximum 4 bytes. The loop condition makes sure the next pass + /* Align up to maximum bytes. The loop condition makes sure the next pass * will have something to do with the size we leave to it. */ - for (size = 1; size < 4 && count >= size * 2 + (address & size); size *= 2) { + for (size = 1; + size < data_bytes && count >= size * 2 + (address & size); + size *= 2) { if (address & size) { int retval = target_read_memory(target, address, size, 1, buffer); if (retval != ERROR_OK) diff --git a/src/target/target.h b/src/target/target.h index d86c63e..18a9516 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -684,6 +684,13 @@ target_addr_t target_address_max(struct target *target); */ unsigned target_address_bits(struct target *target); +/** + * Return the number of data bits this target supports. + * + * This routine is a wrapper for target->type->data_bits. + */ +unsigned int target_data_bits(struct target *target); + /** Return the *name* of this targets current state */ const char *target_state_name(struct target *target); diff --git a/src/target/target_type.h b/src/target/target_type.h index cc51c04..cf30cf8 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -295,6 +295,11 @@ struct target_type { * typically be 32 for 32-bit targets, and 64 for 64-bit targets. If not * implemented, it's assumed to be 32. */ unsigned (*address_bits)(struct target *target); + + /* Return the number of system bus data bits this target supports. This + * will typically be 32 for 32-bit targets, and 64 for 64-bit targets. If + * not implemented, it's assumed to be 32. */ + unsigned int (*data_bits)(struct target *target); }; #endif /* OPENOCD_TARGET_TARGET_TYPE_H */ -- cgit v1.1 From 6a49b1ce2344c8707e322565ff0e5254762353fd Mon Sep 17 00:00:00 2001 From: "R. Diez" Date: Sun, 23 May 2021 12:01:48 +0200 Subject: Avoid non-standard conditionals with omitted operands. Fixes bug #257. Change-Id: I05fc6468306d46399e769098e031e7e588798afc Signed-off-by: R. Diez Reviewed-on: http://openocd.zylin.com/6271 Tested-by: jenkins Reviewed-by: Xiang W Reviewed-by: Antonio Borneo --- src/flash/nand/lpc3180.c | 6 +++--- src/flash/nand/lpc32xx.c | 6 +++--- src/flash/nand/nuc910.c | 2 +- src/helper/command.c | 4 ++-- src/jtag/adapter.c | 2 +- src/jtag/core.c | 2 +- src/jtag/drivers/stlink_usb.c | 4 ++-- src/target/target.c | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c index 97bd7a3..6ce0575 100644 --- a/src/flash/nand/lpc3180.c +++ b/src/flash/nand/lpc3180.c @@ -139,9 +139,9 @@ static int lpc3180_init(struct nand_device *nand) { struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv; struct target *target = nand->target; - int bus_width = nand->bus_width ? : 8; - int address_cycles = nand->address_cycles ? : 3; - int page_size = nand->page_size ? : 512; + int bus_width = nand->bus_width ? nand->bus_width : 8; + int address_cycles = nand->address_cycles ? nand->address_cycles : 3; + int page_size = nand->page_size ? nand->page_size : 512; if (target->state != TARGET_HALTED) { LOG_ERROR("target must be halted to use LPC3180 NAND flash controller"); diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c index 6443beb..f117ead 100644 --- a/src/flash/nand/lpc32xx.c +++ b/src/flash/nand/lpc32xx.c @@ -191,9 +191,9 @@ static int lpc32xx_init(struct nand_device *nand) { struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv; struct target *target = nand->target; - int bus_width = nand->bus_width ? : 8; - int address_cycles = nand->address_cycles ? : 3; - int page_size = nand->page_size ? : 512; + int bus_width = nand->bus_width ? nand->bus_width : 8; + int address_cycles = nand->address_cycles ? nand->address_cycles : 3; + int page_size = nand->page_size ? nand->page_size : 512; int retval; if (target->state != TARGET_HALTED) { diff --git a/src/flash/nand/nuc910.c b/src/flash/nand/nuc910.c index 1a2dd59..9546f2f 100644 --- a/src/flash/nand/nuc910.c +++ b/src/flash/nand/nuc910.c @@ -183,7 +183,7 @@ static int nuc910_nand_init(struct nand_device *nand) { struct nuc910_nand_controller *nuc910_nand = nand->controller_priv; struct target *target = nand->target; - int bus_width = nand->bus_width ? : 8; + int bus_width = nand->bus_width ? nand->bus_width : 8; int result; result = validate_target_state(nand); diff --git a/src/helper/command.c b/src/helper/command.c index 43c5a0f..4be3abd 100644 --- a/src/helper/command.c +++ b/src/helper/command.c @@ -866,9 +866,9 @@ static COMMAND_HELPER(command_help_show, struct help_entry *c, stage_msg = " (?mode error?)"; break; } - msg = alloc_printf("%s%s", c->help ? : "", stage_msg); + msg = alloc_printf("%s%s", c->help ? c->help : "", stage_msg); } else - msg = alloc_printf("%s", c->help ? : ""); + msg = alloc_printf("%s", c->help ? c->help : ""); if (NULL != msg) { command_help_show_wrap(msg, n + 3, n + 3); diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c index 03bb1a9..a867d2c 100644 --- a/src/jtag/adapter.c +++ b/src/jtag/adapter.c @@ -62,7 +62,7 @@ static int jim_adapter_name(Jim_Interp *interp, int argc, Jim_Obj * const *argv) return JIM_ERR; } const char *name = adapter_driver ? adapter_driver->name : NULL; - Jim_SetResultString(goi.interp, name ? : "undefined", -1); + Jim_SetResultString(goi.interp, name ? name : "undefined", -1); return JIM_OK; } diff --git a/src/jtag/core.c b/src/jtag/core.c index 2166374..456faf7 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -1455,7 +1455,7 @@ void jtag_tap_init(struct jtag_tap *tap) unsigned ir_len_bytes; /* if we're autoprobing, cope with potentially huge ir_length */ - ir_len_bits = tap->ir_length ? : JTAG_IRLEN_MAX; + ir_len_bits = tap->ir_length ? tap->ir_length : JTAG_IRLEN_MAX; ir_len_bytes = DIV_ROUND_UP(ir_len_bits, 8); tap->expected = calloc(1, ir_len_bytes); diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c index 7e3280b..c68bbb3 100644 --- a/src/jtag/drivers/stlink_usb.c +++ b/src/jtag/drivers/stlink_usb.c @@ -3904,7 +3904,7 @@ static int stlink_dap_op_queue_dp_read(struct adiv5_dap *dap, unsigned reg, if (retval != ERROR_OK) return retval; - data = data ? : &dummy; + data = data ? data : &dummy; if (stlink_dap_handle->version.flags & STLINK_F_QUIRK_JTAG_DP_READ && stlink_dap_handle->st_mode == STLINK_MODE_DEBUG_JTAG) { /* Quirk required in JTAG. Read RDBUFF to get the data */ @@ -3969,7 +3969,7 @@ static int stlink_dap_op_queue_ap_read(struct adiv5_ap *ap, unsigned reg, if (retval != ERROR_OK) return retval; } - data = data ? : &dummy; + data = data ? data : &dummy; retval = stlink_read_dap_register(stlink_dap_handle, ap->ap_num, reg, data); dap->stlink_flush_ap_write = false; diff --git a/src/target/target.c b/src/target/target.c index 63f68eb..450e231 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -5178,7 +5178,7 @@ no_params: if (goi->argc != 0) goto no_params; } - Jim_SetResultString(goi->interp, target->gdb_port_override ? : "undefined", -1); + Jim_SetResultString(goi->interp, target->gdb_port_override ? target->gdb_port_override : "undefined", -1); /* loop for more */ break; -- cgit v1.1 From bb81ec8bf00f2d8cc0719cef802a367b4dc286e6 Mon Sep 17 00:00:00 2001 From: Marc Schink Date: Sat, 29 May 2021 12:09:28 +0200 Subject: target/startup.tcl: Do not use 'Yoda conditions' Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce Signed-off-by: Marc Schink Reviewed-on: http://openocd.zylin.com/6284 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/target/startup.tcl | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/src/target/startup.tcl b/src/target/startup.tcl index 54a3942..cd98d68 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -30,18 +30,17 @@ proc ocd_process_reset_inner { MODE } { set targets [target names] # If this target must be halted... - set halt -1 - if { 0 == [string compare $MODE halt] } { - set halt 1 - } - if { 0 == [string compare $MODE init] } { - set halt 1; - } - if { 0 == [string compare $MODE run ] } { - set halt 0; - } - if { $halt < 0 } { - return -code error "Invalid mode: $MODE, must be one of: halt, init, or run"; + switch $MODE { + halt - + init { + set halt 1 + } + run { + set halt 0 + } + default { + return -code error "Invalid mode: $MODE, must be one of: halt, init, or run"; + } } # Target event handlers *might* change which TAPs are enabled @@ -130,14 +129,14 @@ proc ocd_process_reset_inner { MODE } { # Did we succeed? set s [$t curstate] - if { 0 != [string compare $s "halted" ] } { + if { $s != "halted" } { return -code error [format "TARGET: %s - Not halted" $t] } } } #Pass 2 - if needed "init" - if { 0 == [string compare init $MODE] } { + if { $MODE == "init" } { foreach t $targets { if {[using_jtag] && ![jtag tapisenabled [$t cget -chain-position]]} { continue -- cgit v1.1 From ee4aa33644df36607750d23d97f84d15b9e71db6 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 8 Jun 2021 12:41:07 -0700 Subject: Fix build. Change-Id: I4f2667db91f84f07af354691aac5d4c9e3aea3fa Signed-off-by: Tim Newsome --- src/rtos/zephyr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/rtos/zephyr.c b/src/rtos/zephyr.c index e5d6835..3ef9bcd 100644 --- a/src/rtos/zephyr.c +++ b/src/rtos/zephyr.c @@ -189,9 +189,9 @@ enum zephyr_symbol_values { ZEPHYR_VAL_COUNT }; -static int64_t zephyr_cortex_m_stack_align(struct target *target, +static target_addr_t zephyr_cortex_m_stack_align(struct target *target, const uint8_t *stack_data, - const struct rtos_register_stacking *stacking, int64_t stack_ptr) + const struct rtos_register_stacking *stacking, target_addr_t stack_ptr) { return rtos_Cortex_M_stack_align(target, stack_data, stacking, stack_ptr, ARM_XPSR_OFFSET); -- cgit v1.1