From c5a8e1cf4c9c685c8a5809f5dba90865e61d2de2 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Wed, 4 Apr 2018 13:50:17 -0700 Subject: Initial commit of tests for SBA feature --- src/target/riscv/riscv-013.c | 160 +++++++++++++++++++++++++++++++++++++++++++ src/target/riscv/riscv.c | 28 ++++++++ src/target/riscv/riscv.h | 3 + 3 files changed, 191 insertions(+) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 2a04d61..a701e2c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -57,6 +57,9 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); +static int riscv013_test_sba_config_reg(struct target *target, uint32_t address); +uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs); +void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, uint64_t value); @@ -1488,6 +1491,7 @@ static int init_target(struct command_context *cmd_ctx, generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64; generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64; generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits; + generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->authdata_read = &riscv013_authdata_read; generic_info->authdata_write = &riscv013_authdata_write; generic_info->dmi_read = &dmi_read; @@ -2811,6 +2815,162 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } +static int riscv013_test_sba_config_reg(struct target *target, uint32_t address) +{ + LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); + + if(!riscv_rtos_enabled(target)) { + LOG_ERROR("Please run with -rtos riscv to run SBA test."); + } + + uint32_t rd_val; + uint32_t sbcs_orig; + dmi_read(target, &sbcs_orig, DMI_SBCS); + + uint32_t sbcs = sbcs_orig; + + // Test 1: Simple write/read test, no address autoincrement + sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,0); + dmi_write(target,DMI_SBCS,sbcs); + + for(int sbaccess = 0; sbaccess < 0x5; sbaccess++) { + sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess); + dmi_write(target,DMI_SBCS,sbcs); + + for(int i = 0; i < 100; i++){ + uint32_t addr = 0x80000000 + (i << sbaccess); + write_memory_sba_simple(target,addr,i,sbcs_orig); + } + + for(uint32_t i = 0; i < 100; i++){ + uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t val = read_memory_sba_simple(target,addr,sbcs_orig); + if(i != val) { + LOG_ERROR("System Bus Access Test: Error reading non-autoincremented address %x, expected val = %d, read val = %d",addr,i,val); + } + } + } + LOG_INFO("System Bus Access Test: Read/write test, no addr autoincrement PASSED"); + + // Test 2: Simple write/read test, with address autoincrement + sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,1); + dmi_write(target,DMI_SBCS,sbcs); + + for(int sbaccess = 0; sbaccess < 0x5; sbaccess++){ + sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess); + dmi_write(target,DMI_SBCS,sbcs); + + dmi_write(target,DMI_SBADDRESS0,0x80000000); + for(int i = 0; i < 100; i++){ + read_sbcs_nonbusy(target,&sbcs); + dmi_write(target,DMI_SBDATA0,i); + } + + sbcs = set_field(sbcs_orig,DMI_SBCS_SBREADONDATA,1); + + dmi_write(target,DMI_SBADDRESS0,0x80000000); + for(uint32_t i = 0; i < 100; i++){ + read_sbcs_nonbusy(target,&sbcs); + uint32_t val; + dmi_read(target,&val,DMI_SBDATA0); + if(i != val) { + LOG_ERROR("System Bus Access Test: Error reading autoincremented address, expected val = %d, read val = %d",i,val); + } + } + } + LOG_INFO("System Bus Access Test: Read/write test, with addr autoincrement PASSED"); + + // Test 3: Read from illegal address + read_memory_sba_simple(target,address,sbcs_orig); + + dmi_read(target,&rd_val,DMI_SBCS); + if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) { + LOG_INFO("System Bus Access Test: Illegal address read test PASSED"); + sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1); + dmi_write(target,DMI_SBCS,sbcs); + } else { + LOG_ERROR("System Bus Access Test: Illegal address read test FAILED"); + } + + // Test 4: Write to illegal address + write_memory_sba_simple(target,address,0xdeadbeef,sbcs_orig); + + dmi_read(target,&rd_val,DMI_SBCS); + if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) { + LOG_INFO("System Bus Access Test: Illegal address write test PASSED"); + sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1); + dmi_write(target,DMI_SBCS,sbcs); + } else { + LOG_ERROR("System Bus Access Test: Illegal address write test FAILED"); + } + + // Test 5: Write to unsupported sbaccess size + uint32_t sbaccess128 = get_field(sbcs_orig,DMI_SBCS_SBACCESS128); + + if(sbaccess128) { + LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED, all alignments supported"); + } else { + sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,0x4); + dmi_write(target, DMI_SBCS, sbcs); + + write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig); + + dmi_read(target,&rd_val,DMI_SBCS); + + if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x3) { + LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED"); + sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,0x1); + dmi_write(target,DMI_SBCS,sbcs); + } else { + LOG_ERROR("System Bus Access Test: SBCS Alignment error test FAILED"); + } + } + + // Test 5: Set sbbusyerror + dmi_write(target,DMI_SBADDRESS0,0x80000000); + dmi_write(target,DMI_SBADDRESS0,0x80000000); + + dmi_read(target,&rd_val,DMI_SBCS); + if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { + LOG_INFO("System Bus Access Test: SBCS sbbusy test PASSED"); + sbcs = set_field(sbcs_orig,DMI_SBCS_SBBUSYERROR,0x1); + dmi_write(target,DMI_SBCS,sbcs); + } else { + LOG_ERROR("System Bus Access Test: SBCS sbbusy test FAILED"); + } + + return 0; + +} + +void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs) +{ + uint32_t rd_sbcs; + read_sbcs_nonbusy(target,&rd_sbcs); + + uint32_t sbcs_no_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,0); + dmi_write(target,DMI_SBCS,sbcs_no_readonaddr); + dmi_write(target,DMI_SBADDRESS0,addr); + dmi_write(target,DMI_SBDATA0,data); +} + +uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs) +{ + uint32_t rd_val; + uint32_t rd_sbcs; + read_sbcs_nonbusy(target,&rd_sbcs); + + uint32_t sbcs_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,1); + dmi_write(target,DMI_SBCS,sbcs_readonaddr); + dmi_write(target,DMI_SBADDRESS0,addr); + + read_sbcs_nonbusy(target,&rd_sbcs); + + dmi_read(target,&rd_val,DMI_SBDATA0); + + return rd_val; +} + int riscv013_dmi_write_u64_bits(struct target *target) { RISCV013_INFO(info); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9af9a5e..4577ef5 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1428,6 +1428,27 @@ COMMAND_HANDLER(riscv_dmi_write) } } +COMMAND_HANDLER(riscv_test_sba_config_reg) +{ + if (CMD_ARGC != 1) { + LOG_ERROR("Command takes exactly 1 argument"); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + struct target *target = get_current_target(CMD_CTX); + RISCV_INFO(r); + + uint32_t address; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); + + if (r->test_sba_config_reg) { + return r->test_sba_config_reg(target,address); + } else { + LOG_ERROR("test_sba_config_reg is not implemented for this target."); + return ERROR_FAIL; + } +} + static const struct command_registration riscv_exec_command_handlers[] = { { .name = "set_command_timeout_sec", @@ -1495,6 +1516,13 @@ static const struct command_registration riscv_exec_command_handlers[] = { .usage = "riscv dmi_write address value", .help = "Perform a 32-bit DMI write of value at address." }, + { + .name = "test_sba_config_reg", + .handler = riscv_test_sba_config_reg, + .mode = COMMAND_ANY, + .usage = "riscv test_sba_config_reg address", + .help = "Perform a series of tests on the SBCS register. Pass in a non-readable/writable address" + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index ad70f4c..a564fb1 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -116,6 +116,9 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); + + int (*test_sba_config_reg)(struct target *target, uint32_t address); + } riscv_info_t; /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/ -- cgit v1.1 From 3bdb8b29a85be3b5b717dfa576a9249c7ab3b47e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 16:31:09 -0700 Subject: Checkpoint: finish debug of tests, working on hitting sbbusyerror case --- src/target/riscv/riscv-013.c | 366 ++++++++++++++++++++++++++----------------- src/target/riscv/riscv.c | 10 +- src/target/riscv/riscv.h | 2 +- 3 files changed, 230 insertions(+), 148 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index a701e2c..57578bf 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -57,7 +57,7 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); -static int riscv013_test_sba_config_reg(struct target *target, uint32_t address); +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address); uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs); void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); @@ -1491,7 +1491,7 @@ static int init_target(struct command_context *cmd_ctx, generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64; generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64; generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits; - generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; + generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->authdata_read = &riscv013_authdata_read; generic_info->authdata_write = &riscv013_authdata_write; generic_info->dmi_read = &dmi_read; @@ -2815,160 +2815,242 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } -static int riscv013_test_sba_config_reg(struct target *target, uint32_t address) -{ - LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); - - if(!riscv_rtos_enabled(target)) { - LOG_ERROR("Please run with -rtos riscv to run SBA test."); - } - - uint32_t rd_val; - uint32_t sbcs_orig; - dmi_read(target, &sbcs_orig, DMI_SBCS); - - uint32_t sbcs = sbcs_orig; - - // Test 1: Simple write/read test, no address autoincrement - sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,0); - dmi_write(target,DMI_SBCS,sbcs); - - for(int sbaccess = 0; sbaccess < 0x5; sbaccess++) { - sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess); - dmi_write(target,DMI_SBCS,sbcs); - - for(int i = 0; i < 100; i++){ - uint32_t addr = 0x80000000 + (i << sbaccess); - write_memory_sba_simple(target,addr,i,sbcs_orig); - } - - for(uint32_t i = 0; i < 100; i++){ - uint32_t addr = 0x80000000 + (i << sbaccess); - uint32_t val = read_memory_sba_simple(target,addr,sbcs_orig); - if(i != val) { - LOG_ERROR("System Bus Access Test: Error reading non-autoincremented address %x, expected val = %d, read val = %d",addr,i,val); - } - } - } - LOG_INFO("System Bus Access Test: Read/write test, no addr autoincrement PASSED"); - - // Test 2: Simple write/read test, with address autoincrement - sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,1); - dmi_write(target,DMI_SBCS,sbcs); - - for(int sbaccess = 0; sbaccess < 0x5; sbaccess++){ - sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess); - dmi_write(target,DMI_SBCS,sbcs); - - dmi_write(target,DMI_SBADDRESS0,0x80000000); - for(int i = 0; i < 100; i++){ - read_sbcs_nonbusy(target,&sbcs); - dmi_write(target,DMI_SBDATA0,i); - } - - sbcs = set_field(sbcs_orig,DMI_SBCS_SBREADONDATA,1); - - dmi_write(target,DMI_SBADDRESS0,0x80000000); - for(uint32_t i = 0; i < 100; i++){ - read_sbcs_nonbusy(target,&sbcs); - uint32_t val; - dmi_read(target,&val,DMI_SBDATA0); - if(i != val) { - LOG_ERROR("System Bus Access Test: Error reading autoincremented address, expected val = %d, read val = %d",i,val); - } - } - } - LOG_INFO("System Bus Access Test: Read/write test, with addr autoincrement PASSED"); - - // Test 3: Read from illegal address - read_memory_sba_simple(target,address,sbcs_orig); - - dmi_read(target,&rd_val,DMI_SBCS); - if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) { - LOG_INFO("System Bus Access Test: Illegal address read test PASSED"); - sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1); - dmi_write(target,DMI_SBCS,sbcs); - } else { - LOG_ERROR("System Bus Access Test: Illegal address read test FAILED"); - } - - // Test 4: Write to illegal address - write_memory_sba_simple(target,address,0xdeadbeef,sbcs_orig); - - dmi_read(target,&rd_val,DMI_SBCS); - if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) { - LOG_INFO("System Bus Access Test: Illegal address write test PASSED"); - sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1); - dmi_write(target,DMI_SBCS,sbcs); - } else { - LOG_ERROR("System Bus Access Test: Illegal address write test FAILED"); - } - - // Test 5: Write to unsupported sbaccess size - uint32_t sbaccess128 = get_field(sbcs_orig,DMI_SBCS_SBACCESS128); - - if(sbaccess128) { - LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED, all alignments supported"); - } else { - sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,0x4); - dmi_write(target, DMI_SBCS, sbcs); - - write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig); - - dmi_read(target,&rd_val,DMI_SBCS); - - if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x3) { - LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED"); - sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,0x1); - dmi_write(target,DMI_SBCS,sbcs); - } else { - LOG_ERROR("System Bus Access Test: SBCS Alignment error test FAILED"); - } - } - - // Test 5: Set sbbusyerror - dmi_write(target,DMI_SBADDRESS0,0x80000000); - dmi_write(target,DMI_SBADDRESS0,0x80000000); - - dmi_read(target,&rd_val,DMI_SBCS); - if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { - LOG_INFO("System Bus Access Test: SBCS sbbusy test PASSED"); - sbcs = set_field(sbcs_orig,DMI_SBCS_SBBUSYERROR,0x1); - dmi_write(target,DMI_SBCS,sbcs); - } else { - LOG_ERROR("System Bus Access Test: SBCS sbbusy test FAILED"); - } - - return 0; +static int get_max_sbaccess(struct target *target) +{ + uint32_t sbcs; + dmi_read(target,&sbcs,DMI_SBCS); + + uint32_t sbaccess128 = get_field(sbcs, DMI_SBCS_SBACCESS128); + uint32_t sbaccess64 = get_field(sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(sbcs, DMI_SBCS_SBACCESS32); + uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16); + uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); + + if(sbaccess128){ + return 4; + }else if(sbaccess64){ + return 3; + }else if(sbaccess32){ + return 2; + }else if(sbaccess16){ + return 1; + }else if(sbaccess8){ + return 0; + } else { + return ERROR_FAIL; + } +} + +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) +{ + LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); + + uint32_t rd_val; + uint32_t sbcs_orig; + dmi_read(target, &sbcs_orig, DMI_SBCS) + + uint32_t sbcs = sbcs_orig; + bool test_passed; + + int max_sbaccess = get_max_sbaccess(target); + + if(max_sbaccess == ERROR_FAIL) { + LOG_ERROR("System Bus Access not supported in this config."); + return ERROR_FAIL; + } + + if(get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { + LOG_ERROR("System Bus Access unsupported SBVERSION"); + return ERROR_FAIL; + } + + // Test 1: Simple write/read test, no address autoincrement + test_passed = true; + sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); + dmi_write(target, DMI_SBCS, sbcs); + + for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){ + sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); + dmi_write(target, DMI_SBCS, sbcs); + + for(int i = 0; i < 100; i++){ + uint32_t addr = 0x80000000 + (i << sbaccess); + write_memory_sba_simple(target, addr, i, sbcs); + } + + for(uint32_t i = 0; i < 100; i++){ + uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t val = read_memory_sba_simple(target, addr, sbcs); + if(i != val) { + LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val); + test_passed = false; + } + } + } + if(test_passed) LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); + + // Test 2: Simple write/read test, with address autoincrement + test_passed = true; + sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); + dmi_write(target, DMI_SBCS, sbcs); + + for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){ + sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); + dmi_write(target, DMI_SBCS, sbcs); + + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + for(int i = 0; i < 100; i++){ + read_sbcs_nonbusy(target, &sbcs); + dmi_write(target, DMI_SBDATA0, i); + } + + read_sbcs_nonbusy(target, &sbcs); + + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + + uint32_t val; + sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); + dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read + for(uint32_t i = 0; i < 100; i++){ + read_sbcs_nonbusy(target, &sbcs); + dmi_read(target, &val, DMI_SBDATA0); + read_sbcs_nonbusy(target, &sbcs); + if(i != val) { + LOG_ERROR("System Bus Access Test 2: Error reading autoincremented address, expected val = %d, read val = %d",i,val); + test_passed = false; + } + } + } + if(test_passed) LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); + + // Test 3: Read from illegal address + read_memory_sba_simple(target, illegal_address, sbcs_orig); + + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) { + LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED"); + sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + } else { + LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED"); + } + + // Test 4: Write to illegal address + write_memory_sba_simple(target, illegal_address, 0xdeadbeef, sbcs_orig); + + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) { + LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED"); + sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); + dmi_write(target, DMI_SBCS,sbcs); + } else { + LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED"); + } + + // Test 5: Write to unsupported sbaccess size + uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128); + + if(sbaccess128) { + LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED, all alignments supported"); + } else { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); + dmi_write(target, DMI_SBCS, sbcs); + + write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig); + + dmi_read(target, &rd_val, DMI_SBCS); + + if(get_field(rd_val, DMI_SBCS_SBERROR) == 3) { + LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED"); + sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + } else { + LOG_ERROR("System Bus Access Test 5: SBCS Alignment error test FAILED"); + } + } + + // Test 6: Set sbbusyerror + sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); + dmi_write(target, DMI_SBCS, sbcs); + + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, 0x80000000); + + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + else LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + } else { + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + } + + return ERROR_OK; } void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs) { - uint32_t rd_sbcs; - read_sbcs_nonbusy(target,&rd_sbcs); + uint32_t rd_sbcs; - uint32_t sbcs_no_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,0); - dmi_write(target,DMI_SBCS,sbcs_no_readonaddr); - dmi_write(target,DMI_SBADDRESS0,addr); - dmi_write(target,DMI_SBDATA0,data); + read_sbcs_nonbusy(target, &rd_sbcs); + + uint32_t sbcs_no_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 0); + dmi_write(target, DMI_SBCS, sbcs_no_readonaddr); + dmi_write(target, DMI_SBADDRESS0, addr); + dmi_write(target, DMI_SBDATA0, data); } uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs) { - uint32_t rd_val; - uint32_t rd_sbcs; - read_sbcs_nonbusy(target,&rd_sbcs); + uint32_t rd_val; + uint32_t rd_sbcs; + + read_sbcs_nonbusy(target, &rd_sbcs); - uint32_t sbcs_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,1); - dmi_write(target,DMI_SBCS,sbcs_readonaddr); - dmi_write(target,DMI_SBADDRESS0,addr); + uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1); + dmi_write(target, DMI_SBCS,sbcs_readonaddr); + dmi_write(target, DMI_SBADDRESS0,addr); - read_sbcs_nonbusy(target,&rd_sbcs); + read_sbcs_nonbusy(target, &rd_sbcs); - dmi_read(target,&rd_val,DMI_SBDATA0); + dmi_read(target, &rd_val, DMI_SBDATA0); - return rd_val; + return rd_val; } int riscv013_dmi_write_u64_bits(struct target *target) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 4577ef5..a94640e 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1438,11 +1438,11 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); - uint32_t address; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); + uint32_t illegal_address; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], illegal_address); if (r->test_sba_config_reg) { - return r->test_sba_config_reg(target,address); + return r->test_sba_config_reg(target, illegal_address); } else { LOG_ERROR("test_sba_config_reg is not implemented for this target."); return ERROR_FAIL; @@ -1520,8 +1520,8 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg address", - .help = "Perform a series of tests on the SBCS register. Pass in a non-readable/writable address" + .usage = "riscv test_sba_config_reg illegal_address", + .help = "Perform a series of tests on the SBCS register. Input arg is a non-readable/writable address." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index a564fb1..18f47b7 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -117,7 +117,7 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); - int (*test_sba_config_reg)(struct target *target, uint32_t address); + int (*test_sba_config_reg)(struct target *target, target_addr_t illegal_address); } riscv_info_t; -- cgit v1.1 From 761aaeba989a56a8afdfb3c78663b823f914ad0d Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 16:39:33 -0700 Subject: Checkpoint: fix some code style issues --- src/target/riscv/riscv-013.c | 63 ++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 35 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 57578bf..9f14300 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2818,27 +2818,20 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) static int get_max_sbaccess(struct target *target) { uint32_t sbcs; - dmi_read(target,&sbcs,DMI_SBCS); + dmi_read(target, &sbcs, DMI_SBCS); uint32_t sbaccess128 = get_field(sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(sbcs, DMI_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(sbcs, DMI_SBCS_SBACCESS32); - uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16); + uint32_t sbaccess64 = get_field(sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(sbcs, DMI_SBCS_SBACCESS32); + uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16); uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); - if(sbaccess128){ - return 4; - }else if(sbaccess64){ - return 3; - }else if(sbaccess32){ - return 2; - }else if(sbaccess16){ - return 1; - }else if(sbaccess8){ - return 0; - } else { - return ERROR_FAIL; - } + if (sbaccess128) return 4; + else if (sbaccess64) return 3; + else if (sbaccess32) return 2; + else if (sbaccess16) return 1; + else if (sbaccess8) return 0; + else return ERROR_FAIL; } static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) @@ -2854,12 +2847,12 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill int max_sbaccess = get_max_sbaccess(target); - if(max_sbaccess == ERROR_FAIL) { + if (max_sbaccess == ERROR_FAIL) { LOG_ERROR("System Bus Access not supported in this config."); return ERROR_FAIL; } - if(get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { + if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { LOG_ERROR("System Bus Access unsupported SBVERSION"); return ERROR_FAIL; } @@ -2869,37 +2862,37 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); dmi_write(target, DMI_SBCS, sbcs); - for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){ + for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); - for(int i = 0; i < 100; i++){ + for (int i = 0; i < 100; i++) { uint32_t addr = 0x80000000 + (i << sbaccess); write_memory_sba_simple(target, addr, i, sbcs); } - for(uint32_t i = 0; i < 100; i++){ + for (uint32_t i = 0; i < 100; i++) { uint32_t addr = 0x80000000 + (i << sbaccess); uint32_t val = read_memory_sba_simple(target, addr, sbcs); - if(i != val) { + if (i != val) { LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val); test_passed = false; } } } - if(test_passed) LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); + if (test_passed) LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); // Test 2: Simple write/read test, with address autoincrement test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); dmi_write(target, DMI_SBCS, sbcs); - for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){ + for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); dmi_write(target, DMI_SBADDRESS0, 0x80000000); - for(int i = 0; i < 100; i++){ + for (int i = 0; i < 100; i++) { read_sbcs_nonbusy(target, &sbcs); dmi_write(target, DMI_SBDATA0, i); } @@ -2912,23 +2905,23 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read - for(uint32_t i = 0; i < 100; i++){ + for (uint32_t i = 0; i < 100; i++) { read_sbcs_nonbusy(target, &sbcs); dmi_read(target, &val, DMI_SBDATA0); read_sbcs_nonbusy(target, &sbcs); - if(i != val) { + if (i != val) { LOG_ERROR("System Bus Access Test 2: Error reading autoincremented address, expected val = %d, read val = %d",i,val); test_passed = false; } } } - if(test_passed) LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); + if (test_passed) LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); // Test 3: Read from illegal address read_memory_sba_simple(target, illegal_address, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) { + if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED"); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -2940,7 +2933,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill write_memory_sba_simple(target, illegal_address, 0xdeadbeef, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) { + if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED"); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS,sbcs); @@ -2951,7 +2944,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill // Test 5: Write to unsupported sbaccess size uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128); - if(sbaccess128) { + if (sbaccess128) { LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED, all alignments supported"); } else { sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); @@ -2961,7 +2954,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 3) { + if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED"); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -3009,11 +3002,11 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBADDRESS0, 0x80000000); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { + if (get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); else LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); } else { LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); -- cgit v1.1 From 8c8bed878c8a6783681fcf327cd4bf361975e410 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 16:42:28 -0700 Subject: Checkpoint: fix some more code style issues --- src/target/riscv/riscv-013.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 9f14300..4bd0450 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2826,12 +2826,18 @@ static int get_max_sbaccess(struct target *target) uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16); uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); - if (sbaccess128) return 4; - else if (sbaccess64) return 3; - else if (sbaccess32) return 2; - else if (sbaccess16) return 1; - else if (sbaccess8) return 0; - else return ERROR_FAIL; + if (sbaccess128) + return 4; + else if (sbaccess64) + return 3; + else if (sbaccess32) + return 2; + else if (sbaccess16) + return 1; + else if (sbaccess8) + return 0; + else + return ERROR_FAIL; } static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) @@ -2880,7 +2886,8 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill } } } - if (test_passed) LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); + if (test_passed) + LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); // Test 2: Simple write/read test, with address autoincrement test_passed = true; @@ -2915,7 +2922,8 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill } } } - if (test_passed) LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); + if (test_passed) + LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); // Test 3: Read from illegal address read_memory_sba_simple(target, illegal_address, sbcs_orig); @@ -3002,12 +3010,15 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBADDRESS0, 0x80000000); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val,DMI_SBCS_SBBUSYERROR)) { + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); - else LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) { + LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + } else { + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + } } else { LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); } -- cgit v1.1 From ada78cae11c18c8aa743d24b08983878f3c4976e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 16:49:00 -0700 Subject: Checkpoint: fix even more code style issues --- src/target/riscv/riscv-013.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 4bd0450..389d2d7 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2827,17 +2827,17 @@ static int get_max_sbaccess(struct target *target) uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); if (sbaccess128) - return 4; + return 4; else if (sbaccess64) - return 3; + return 3; else if (sbaccess32) - return 2; + return 2; else if (sbaccess16) - return 1; + return 1; else if (sbaccess8) - return 0; - else - return ERROR_FAIL; + return 0; + else + return ERROR_FAIL; } static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) @@ -2887,7 +2887,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill } } if (test_passed) - LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); + LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); // Test 2: Simple write/read test, with address autoincrement test_passed = true; @@ -2923,7 +2923,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill } } if (test_passed) - LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); + LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); // Test 3: Read from illegal address read_memory_sba_simple(target, illegal_address, sbcs_orig); @@ -3014,11 +3014,10 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) { - LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); - } else { - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); - } + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) + LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + else + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); } else { LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); } -- cgit v1.1 From d471fff3dbeeaf2db80d39fb754e6071b6b3e03e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 17:57:53 -0700 Subject: Fixed build issues --- src/target/riscv/riscv-013.c | 49 ++++++++++++++++++++++---------------------- src/target/riscv/riscv.c | 12 +++++++---- src/target/riscv/riscv.h | 3 ++- 3 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 389d2d7..988b691 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -57,7 +57,8 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address); +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, + target_addr_t illegal_address); uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs); void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); @@ -2840,13 +2841,13 @@ static int get_max_sbaccess(struct target *target) return ERROR_FAIL; } -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, target_addr_t illegal_address) { LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); uint32_t rd_val; uint32_t sbcs_orig; - dmi_read(target, &sbcs_orig, DMI_SBCS) + dmi_read(target, &sbcs_orig, DMI_SBCS); uint32_t sbcs = sbcs_orig; bool test_passed; @@ -2873,12 +2874,12 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBCS, sbcs); for (int i = 0; i < 100; i++) { - uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t addr = legal_address + (i << sbaccess); write_memory_sba_simple(target, addr, i, sbcs); } for (uint32_t i = 0; i < 100; i++) { - uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t addr = legal_address + (i << sbaccess); uint32_t val = read_memory_sba_simple(target, addr, sbcs); if (i != val) { LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val); @@ -2898,7 +2899,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); for (int i = 0; i < 100; i++) { read_sbcs_nonbusy(target, &sbcs); dmi_write(target, DMI_SBDATA0, i); @@ -2906,7 +2907,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill read_sbcs_nonbusy(target, &sbcs); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); uint32_t val; sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); @@ -2958,7 +2959,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); dmi_write(target, DMI_SBCS, sbcs); - write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig); + write_memory_sba_simple(target, legal_address, 0xdeadbeef, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); @@ -2992,22 +2993,22 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBDATA0, 0xdeadbeef); dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index a94640e..9aed49c 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1438,11 +1438,13 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); + uint32_t legal_address; uint32_t illegal_address; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], illegal_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], legal_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], illegal_address); if (r->test_sba_config_reg) { - return r->test_sba_config_reg(target, illegal_address); + return r->test_sba_config_reg(target, legal_address, illegal_address); } else { LOG_ERROR("test_sba_config_reg is not implemented for this target."); return ERROR_FAIL; @@ -1520,8 +1522,10 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg illegal_address", - .help = "Perform a series of tests on the SBCS register. Input arg is a non-readable/writable address." + .usage = "riscv test_sba_config_reg legal_address illegal_address", + .help = "Perform a series of tests on the SBCS register." + "Inputs are a legal address for read/write tests," + "and an illegal address to for error flag/handling cases." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 18f47b7..ec0a21c 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -117,7 +117,8 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); - int (*test_sba_config_reg)(struct target *target, target_addr_t illegal_address); + int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, + target_addr_t illegal_address); } riscv_info_t; -- cgit v1.1 From 7c6f6d79bc6a60a3e91da5056c15118a09252297 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 17:59:43 -0700 Subject: Fixed more style issues --- src/target/riscv/riscv-013.c | 3 ++- src/target/riscv/riscv.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 988b691..c926180 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2841,7 +2841,8 @@ static int get_max_sbaccess(struct target *target) return ERROR_FAIL; } -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, target_addr_t illegal_address) +static int riscv013_test_sba_config_reg(struct target *target, + target_addr_t legal_address, target_addr_t illegal_address) { LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index ec0a21c..8ac4f86 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -117,7 +117,7 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); - int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, + int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, target_addr_t illegal_address); } riscv_info_t; -- cgit v1.1 From a9b2277574c1f4e82ec9ab44e1a5e8fc2af1dbf1 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 10:51:53 -0700 Subject: Add #ifdef to only enable sbbusyerror test in simulation. --- src/target/riscv/riscv-013.c | 80 ++++++++++++++++++++++++++++++++++---------- src/target/riscv/riscv.c | 14 ++++---- 2 files changed, 70 insertions(+), 24 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index c926180..62dc671 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -59,8 +59,8 @@ static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, target_addr_t illegal_address); -uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs); -void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs); +uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs); +void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, uint64_t value); @@ -2818,14 +2818,13 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) static int get_max_sbaccess(struct target *target) { - uint32_t sbcs; - dmi_read(target, &sbcs, DMI_SBCS); + RISCV013_INFO(info); - uint32_t sbaccess128 = get_field(sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(sbcs, DMI_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(sbcs, DMI_SBCS_SBACCESS32); - uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16); - uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8); + uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); + uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); + uint32_t sbaccess16 = get_field(info->sbcs, DMI_SBCS_SBACCESS16); + uint32_t sbaccess8 = get_field(info->sbcs, DMI_SBCS_SBACCESS8); if (sbaccess128) return 4; @@ -2838,7 +2837,7 @@ static int get_max_sbaccess(struct target *target) else if (sbaccess8) return 0; else - return ERROR_FAIL; + return -1; } static int riscv013_test_sba_config_reg(struct target *target, @@ -2861,7 +2860,7 @@ static int riscv013_test_sba_config_reg(struct target *target, } if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { - LOG_ERROR("System Bus Access unsupported SBVERSION"); + LOG_ERROR("System Bus Access unsupported SBVERSION (0). Only version 1 is supported."); return ERROR_FAIL; } @@ -2892,6 +2891,8 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); // Test 2: Simple write/read test, with address autoincrement + uint32_t curr_addr; + uint32_t prev_addr; test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -2901,8 +2902,16 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_write(target, DMI_SBCS, sbcs); dmi_write(target, DMI_SBADDRESS0, legal_address); + read_sbcs_nonbusy(target, &sbcs); + curr_addr = legal_address; for (int i = 0; i < 100; i++) { + prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); + dmi_read(target,&curr_addr,DMI_SBADDRESS0); + if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { + LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x",sbaccess); + test_passed = false; + } dmi_write(target, DMI_SBDATA0, i); } @@ -2914,8 +2923,15 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read + curr_addr = legal_address; for (uint32_t i = 0; i < 100; i++) { + prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); + dmi_read(target,&curr_addr,DMI_SBADDRESS0); + if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { + LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x",sbaccess); + test_passed = false; + } dmi_read(target, &val, DMI_SBDATA0); read_sbcs_nonbusy(target, &sbcs); if (i != val) { @@ -2973,7 +2989,9 @@ static int riscv013_test_sba_config_reg(struct target *target, } } - // Test 6: Set sbbusyerror + // Test 6: Set sbbusyerror, only run this case in simulation as it is likely + // impossible to hit otherwise +#ifdef SIM_ON sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -3023,33 +3041,61 @@ static int riscv013_test_sba_config_reg(struct target *target, } else { LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); } +#endif return ERROR_OK; } -void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs) +void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs) { + RISCV013_INFO(info); + uint32_t rd_sbcs; + uint32_t masked_addr; + + uint32_t sba_size = get_field(info->sbcs,DMI_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); uint32_t sbcs_no_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 0); dmi_write(target, DMI_SBCS, sbcs_no_readonaddr); - dmi_write(target, DMI_SBADDRESS0, addr); + + for (uint32_t i = 0; i < sba_size/32; i++) { + masked_addr = (addr >> 32*i) & 0xffffffff; + + if (i != 3) + dmi_write(target, DMI_SBADDRESS0+i, masked_addr); + else + dmi_write(target, DMI_SBADDRESS3, masked_addr); + } + dmi_write(target, DMI_SBDATA0, data); } -uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs) +uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs) { + RISCV013_INFO(info); + uint32_t rd_val; uint32_t rd_sbcs; + uint32_t masked_addr; + + uint32_t sba_size = get_field(info->sbcs,DMI_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1); - dmi_write(target, DMI_SBCS,sbcs_readonaddr); - dmi_write(target, DMI_SBADDRESS0,addr); + dmi_write(target, DMI_SBCS, sbcs_readonaddr); + + for (uint32_t i = 0; i < sba_size/32; i++) { + masked_addr = (addr >> 32*i) & 0xffffffff; + + if (i != 3) + dmi_write(target, DMI_SBADDRESS0+i, masked_addr); + else + dmi_write(target, DMI_SBADDRESS3, masked_addr); + } read_sbcs_nonbusy(target, &rd_sbcs); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9aed49c..21fb5b4 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1430,18 +1430,18 @@ COMMAND_HANDLER(riscv_dmi_write) COMMAND_HANDLER(riscv_test_sba_config_reg) { - if (CMD_ARGC != 1) { - LOG_ERROR("Command takes exactly 1 argument"); + if (CMD_ARGC != 2) { + LOG_ERROR("Command takes exactly 2 arguments"); return ERROR_COMMAND_SYNTAX_ERROR; } struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); - uint32_t legal_address; - uint32_t illegal_address; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], legal_address); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], illegal_address); + target_addr_t legal_address; + target_addr_t illegal_address; + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address); if (r->test_sba_config_reg) { return r->test_sba_config_reg(target, legal_address, illegal_address); @@ -1525,7 +1525,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { .usage = "riscv test_sba_config_reg legal_address illegal_address", .help = "Perform a series of tests on the SBCS register." "Inputs are a legal address for read/write tests," - "and an illegal address to for error flag/handling cases." + "and an illegal address for error flag/handling cases." }, COMMAND_REGISTRATION_DONE }; -- cgit v1.1 From de329f40042b9c11d494aed573c46dcf9e48fbbd Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 10:54:21 -0700 Subject: Fixed style issues in previous commit. --- src/target/riscv/riscv-013.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 62dc671..664c31c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2907,9 +2907,9 @@ static int riscv013_test_sba_config_reg(struct target *target, for (int i = 0; i < 100; i++) { prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); - dmi_read(target,&curr_addr,DMI_SBADDRESS0); + dmi_read(target, &curr_addr, DMI_SBADDRESS0); if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { - LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x",sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } dmi_write(target, DMI_SBDATA0, i); @@ -2927,9 +2927,9 @@ static int riscv013_test_sba_config_reg(struct target *target, for (uint32_t i = 0; i < 100; i++) { prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); - dmi_read(target,&curr_addr,DMI_SBADDRESS0); + dmi_read(target, &curr_addr, DMI_SBADDRESS0); if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { - LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x",sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } dmi_read(target, &val, DMI_SBDATA0); @@ -2989,8 +2989,8 @@ static int riscv013_test_sba_config_reg(struct target *target, } } - // Test 6: Set sbbusyerror, only run this case in simulation as it is likely - // impossible to hit otherwise + /* Test 6: Set sbbusyerror, only run this case in simulation as it is likely + * impossible to hit otherwise */ #ifdef SIM_ON sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -3054,7 +3054,7 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t uint32_t rd_sbcs; uint32_t masked_addr; - uint32_t sba_size = get_field(info->sbcs,DMI_SBCS_SBASIZE); + uint32_t sba_size = get_field(info->sbcs, DMI_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); @@ -3081,7 +3081,7 @@ uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint3 uint32_t rd_sbcs; uint32_t masked_addr; - uint32_t sba_size = get_field(info->sbcs,DMI_SBCS_SBASIZE); + uint32_t sba_size = get_field(info->sbcs, DMI_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); -- cgit v1.1 From 99f2f5a27291312f11ee9851631cd3b0c183bc4e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 11:26:31 -0700 Subject: Change #ifdef SIM_ON to be a run-time arg --- src/target/riscv/riscv-013.c | 102 +++++++++++++++++++++---------------------- src/target/riscv/riscv.c | 13 ++++-- src/target/riscv/riscv.h | 2 + 3 files changed, 62 insertions(+), 55 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 664c31c..ba5a074 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2816,7 +2816,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } -static int get_max_sbaccess(struct target *target) +static uint32_t get_max_sbaccess(struct target *target) { RISCV013_INFO(info); @@ -2854,7 +2854,7 @@ static int riscv013_test_sba_config_reg(struct target *target, int max_sbaccess = get_max_sbaccess(target); - if (max_sbaccess == ERROR_FAIL) { + if (max_sbaccess == -1) { LOG_ERROR("System Bus Access not supported in this config."); return ERROR_FAIL; } @@ -2869,7 +2869,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); dmi_write(target, DMI_SBCS, sbcs); - for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { + for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); @@ -2897,7 +2897,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); dmi_write(target, DMI_SBCS, sbcs); - for (int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++) { + for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); @@ -2991,57 +2991,57 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 6: Set sbbusyerror, only run this case in simulation as it is likely * impossible to hit otherwise */ -#ifdef SIM_ON - sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); - dmi_write(target, DMI_SBCS, sbcs); + if (run_sim_only_tests) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); + dmi_write(target, DMI_SBCS, sbcs); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); - dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) - LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); - else - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); - } else { - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &rd_val, DMI_SBCS); + if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) + LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + else + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + } else { + LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + } } -#endif return ERROR_OK; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 21fb5b4..4ca474b 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -190,6 +190,8 @@ uint64_t riscv_scratch_ram_address; bool riscv_prefer_sba; +bool run_sim_only_tests; + /* In addition to the ones in the standard spec, we'll also expose additional * CSRs in this list. * The list is either NULL, or a series of ranges (inclusive), terminated with @@ -1430,8 +1432,8 @@ COMMAND_HANDLER(riscv_dmi_write) COMMAND_HANDLER(riscv_test_sba_config_reg) { - if (CMD_ARGC != 2) { - LOG_ERROR("Command takes exactly 2 arguments"); + if (CMD_ARGC != 3) { + LOG_ERROR("Command takes exactly 3 arguments"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1442,6 +1444,7 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) target_addr_t illegal_address; COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address); + COMMAND_PARSE_ON_OFF(CMD_ARGV[2], run_sim_only_tests); if (r->test_sba_config_reg) { return r->test_sba_config_reg(target, legal_address, illegal_address); @@ -1522,10 +1525,12 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg legal_address illegal_address", + .usage = "riscv test_sba_config_reg legal_address" + "illegal_address run_sim_only_tests[on/off]", .help = "Perform a series of tests on the SBCS register." "Inputs are a legal address for read/write tests," - "and an illegal address for error flag/handling cases." + "an illegal address for error flag/handling cases, and" + "whether sim_only tests should be run." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 8ac4f86..367b670 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -133,6 +133,8 @@ extern uint64_t riscv_scratch_ram_address; extern bool riscv_prefer_sba; +extern bool run_sim_only_tests; + /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused)); -- cgit v1.1 From c2c52c89b17c72b511b731c41bad75f04f1a4f10 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 11:38:41 -0700 Subject: Fix some build issues --- src/target/riscv/riscv-013.c | 6 +++--- src/target/riscv/riscv.c | 6 +++--- src/target/riscv/riscv.h | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index ba5a074..0ebfcc4 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2908,7 +2908,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); dmi_read(target, &curr_addr, DMI_SBADDRESS0); - if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) { LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } @@ -2928,7 +2928,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); dmi_read(target, &curr_addr, DMI_SBADDRESS0); - if ((curr_addr - prev_addr != (1 << sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) { LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } @@ -2991,7 +2991,7 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 6: Set sbbusyerror, only run this case in simulation as it is likely * impossible to hit otherwise */ - if (run_sim_only_tests) { + if (riscv_run_sim_only_tests) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 4ca474b..ffe7bc5 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -190,7 +190,7 @@ uint64_t riscv_scratch_ram_address; bool riscv_prefer_sba; -bool run_sim_only_tests; +bool riscv_run_sim_only_tests; /* In addition to the ones in the standard spec, we'll also expose additional * CSRs in this list. @@ -1444,7 +1444,7 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) target_addr_t illegal_address; COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address); - COMMAND_PARSE_ON_OFF(CMD_ARGV[2], run_sim_only_tests); + COMMAND_PARSE_ON_OFF(CMD_ARGV[2], riscv_run_sim_only_tests); if (r->test_sba_config_reg) { return r->test_sba_config_reg(target, legal_address, illegal_address); @@ -1526,7 +1526,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, .usage = "riscv test_sba_config_reg legal_address" - "illegal_address run_sim_only_tests[on/off]", + "illegal_address riscv_run_sim_only_tests[on/off]", .help = "Perform a series of tests on the SBCS register." "Inputs are a legal address for read/write tests," "an illegal address for error flag/handling cases, and" diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 367b670..2ce908d 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -133,7 +133,7 @@ extern uint64_t riscv_scratch_ram_address; extern bool riscv_prefer_sba; -extern bool run_sim_only_tests; +extern bool riscv_run_sim_only_tests; /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ -- cgit v1.1 From 836bd7cb693fc4d6d8eb09c578fdcfccd71eee03 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 9 Apr 2018 11:55:46 -0700 Subject: Fix sign compare compiler error --- src/target/riscv/riscv-013.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 0ebfcc4..f225092 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2908,7 +2908,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); dmi_read(target, &curr_addr, DMI_SBADDRESS0); - if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } @@ -2928,7 +2928,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); dmi_read(target, &curr_addr, DMI_SBADDRESS0); - if ((curr_addr - prev_addr != (1 << (uint32_t)sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); test_passed = false; } -- cgit v1.1 From cc98a14839ab11a71fbc24e708fe91d17c04fa1b Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Wed, 11 Apr 2018 14:26:16 -0700 Subject: Added address alignment test, code fixups from review --- src/target/riscv/riscv-013.c | 196 ++++++++++++++++++++++++++----------------- src/target/riscv/riscv.c | 28 ++++--- src/target/riscv/riscv.h | 4 +- 3 files changed, 135 insertions(+), 93 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index f225092..5dd8232 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -58,9 +58,11 @@ static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, - target_addr_t illegal_address); -uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs); -void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs); + uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); +void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data, + uint32_t write_size, uint32_t sbcs); +uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t read_size, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, uint64_t value); @@ -2816,7 +2818,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } -static uint32_t get_max_sbaccess(struct target *target) +static int get_max_sbaccess(struct target *target) { RISCV013_INFO(info); @@ -2840,8 +2842,24 @@ static uint32_t get_max_sbaccess(struct target *target) return -1; } +static uint32_t get_num_sbdata_regs(struct target *target) +{ + RISCV013_INFO(info); + + uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); + uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); + + if(sbaccess128) + return 4; + else if(sbaccess64) + return 2; + else + return 1; +} + static int riscv013_test_sba_config_reg(struct target *target, - target_addr_t legal_address, target_addr_t illegal_address) + target_addr_t legal_address, uint32_t num_words, + target_addr_t illegal_address, bool run_sbbusyerror_test) { LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); @@ -2864,35 +2882,47 @@ static int riscv013_test_sba_config_reg(struct target *target, return ERROR_FAIL; } - // Test 1: Simple write/read test, no address autoincrement + uint32_t num_sbdata_regs = get_num_sbdata_regs(target); + + // Test 1: Simple write/read test test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); dmi_write(target, DMI_SBCS, sbcs); + uint32_t test_patterns[4] = {0xdeadbeef, 0xfeedbabe, 0x12345678, 0x08675309}; for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); - for (int i = 0; i < 100; i++) { + uint32_t compare_mask = (sbaccess == 0) ? 0xff : + (sbaccess == 1) ? 0xffff : 0xffffffff; + + for (uint32_t i = 0; i < num_words; i++) { uint32_t addr = legal_address + (i << sbaccess); - write_memory_sba_simple(target, addr, i, sbcs); + uint32_t wr_data[num_sbdata_regs]; + for (uint32_t j = 0; j < num_sbdata_regs; j++) + wr_data[j] = test_patterns[j] + i; + write_memory_sba_simple(target, addr, wr_data, num_sbdata_regs, sbcs); } - for (uint32_t i = 0; i < 100; i++) { + for (uint32_t i = 0; i < num_words; i++) { uint32_t addr = legal_address + (i << sbaccess); - uint32_t val = read_memory_sba_simple(target, addr, sbcs); - if (i != val) { - LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val); - test_passed = false; + uint32_t* val = read_memory_sba_simple(target, addr, num_sbdata_regs, sbcs); + for (uint32_t j = 0; j < num_sbdata_regs; j++) { + if (((test_patterns[j]+i)&compare_mask) != (val[j]&compare_mask)) { + LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %x, read val = %x", addr, test_patterns[j]+i, val[j]); + test_passed = false; + } } + free(val); } } if (test_passed) - LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED"); + LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED."); - // Test 2: Simple write/read test, with address autoincrement - uint32_t curr_addr; - uint32_t prev_addr; + // Test 2: Address autoincrement test + target_addr_t curr_addr; + target_addr_t prev_addr; test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -2904,12 +2934,12 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_write(target, DMI_SBADDRESS0, legal_address); read_sbcs_nonbusy(target, &sbcs); curr_addr = legal_address; - for (int i = 0; i < 100; i++) { + for (uint32_t i = 0; i < num_words; i++) { prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); - dmi_read(target, &curr_addr, DMI_SBADDRESS0); + curr_addr = sb_read_address(target); if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { - LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); test_passed = false; } dmi_write(target, DMI_SBDATA0, i); @@ -2924,110 +2954,109 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read curr_addr = legal_address; - for (uint32_t i = 0; i < 100; i++) { + for (uint32_t i = 0; i < num_words; i++) { prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); - dmi_read(target, &curr_addr, DMI_SBADDRESS0); + curr_addr = sb_read_address(target); if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { - LOG_ERROR("System Bus Access Test 2: Error with address autoincrement, sbaccess = %x", sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); test_passed = false; } dmi_read(target, &val, DMI_SBDATA0); read_sbcs_nonbusy(target, &sbcs); if (i != val) { - LOG_ERROR("System Bus Access Test 2: Error reading autoincremented address, expected val = %d, read val = %d",i,val); + LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address, expected val = %x, read val = %x",i,val); test_passed = false; } } } if (test_passed) - LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED"); + LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED."); // Test 3: Read from illegal address - read_memory_sba_simple(target, illegal_address, sbcs_orig); + uint32_t* illegal_addr_read = read_memory_sba_simple(target, illegal_address, 1, sbcs_orig); + free(illegal_addr_read); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { - LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED"); + LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED."); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); } else { - LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED"); + LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED."); } // Test 4: Write to illegal address - write_memory_sba_simple(target, illegal_address, 0xdeadbeef, sbcs_orig); + write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { - LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED"); + LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS,sbcs); } else { - LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED"); + LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED."); } - // Test 5: Write to unsupported sbaccess size + // Test 5: Write with unsupported sbaccess size uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128); if (sbaccess128) { - LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED, all alignments supported"); + LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported."); } else { sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); dmi_write(target, DMI_SBCS, sbcs); - write_memory_sba_simple(target, legal_address, 0xdeadbeef, sbcs_orig); + write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); + LOG_INFO("SBCS.SBACCESS128 = %x",sbaccess128); + LOG_INFO("SBCS.SBERROR = %x",get_field(rd_val,DMI_SBCS_SBERROR)); + if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { - LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED"); sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED."); + else + LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0."); } else { - LOG_ERROR("System Bus Access Test 5: SBCS Alignment error test FAILED"); + LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code."); } } - /* Test 6: Set sbbusyerror, only run this case in simulation as it is likely + // Test 6: Write to misaligned address + sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); + dmi_write(target, DMI_SBCS, sbcs); + + dmi_write(target, DMI_SBADDRESS0, legal_address+1); + if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { + sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); + dmi_write(target, DMI_SBCS, sbcs); + dmi_read(target, &rd_val, DMI_SBCS); + if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED"); + else + LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0."); + } else { + LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code."); + } + + /* Test 7: Set sbbusyerror, only run this case in simulation as it is likely * impossible to hit otherwise */ - if (riscv_run_sim_only_tests) { + if (run_sbbusyerror_test) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + for (int i = 0; i < 16; i++) { + dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + } - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); - dmi_write(target, DMI_SBADDRESS0, legal_address); + for (int i = 0; i < 16; i++) { + dmi_write(target, DMI_SBADDRESS0, legal_address); + } dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { @@ -3035,11 +3064,11 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) - LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED"); + LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED."); else - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0"); + LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0."); } else { - LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set"); + LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code."); } } @@ -3047,7 +3076,8 @@ static int riscv013_test_sba_config_reg(struct target *target, } -void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t data, uint32_t sbcs) +void write_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t* write_data, uint32_t write_size, uint32_t sbcs) { RISCV013_INFO(info); @@ -3070,14 +3100,19 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t dmi_write(target, DMI_SBADDRESS3, masked_addr); } - dmi_write(target, DMI_SBDATA0, data); + /* Write SBDATA registers starting with highest address, since write to + * SBDATA0 triggers write */ + for (int i = write_size-1; i >= 0; i--) { + dmi_write(target,DMI_SBDATA0+i,write_data[i]); + } } -uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs) +uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t read_size, uint32_t sbcs) { RISCV013_INFO(info); - uint32_t rd_val; + uint32_t* rd_val = malloc(read_size*sizeof(uint32_t)); uint32_t rd_sbcs; uint32_t masked_addr; @@ -3088,7 +3123,8 @@ uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint3 uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs_readonaddr); - for (uint32_t i = 0; i < sba_size/32; i++) { + // Write addresses starting with highest address register + for (int i = sba_size/32-1; i >= 0; i--) { masked_addr = (addr >> 32*i) & 0xffffffff; if (i != 3) @@ -3099,7 +3135,9 @@ uint32_t read_memory_sba_simple(struct target *target, target_addr_t addr, uint3 read_sbcs_nonbusy(target, &rd_sbcs); - dmi_read(target, &rd_val, DMI_SBDATA0); + for (uint32_t i = 0; i < read_size; i++) { + dmi_read(target, &(rd_val[i]), DMI_SBDATA0+i); + } return rd_val; } diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index ffe7bc5..d1bd5e6 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -190,8 +190,6 @@ uint64_t riscv_scratch_ram_address; bool riscv_prefer_sba; -bool riscv_run_sim_only_tests; - /* In addition to the ones in the standard spec, we'll also expose additional * CSRs in this list. * The list is either NULL, or a series of ranges (inclusive), terminated with @@ -1432,8 +1430,8 @@ COMMAND_HANDLER(riscv_dmi_write) COMMAND_HANDLER(riscv_test_sba_config_reg) { - if (CMD_ARGC != 3) { - LOG_ERROR("Command takes exactly 3 arguments"); + if (CMD_ARGC != 4) { + LOG_ERROR("Command takes exactly 4 arguments"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1441,13 +1439,17 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) RISCV_INFO(r); target_addr_t legal_address; + uint32_t num_words; target_addr_t illegal_address; + bool run_sbbusyerror_test; COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); - COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], illegal_address); - COMMAND_PARSE_ON_OFF(CMD_ARGV[2], riscv_run_sim_only_tests); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words); + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[2], illegal_address); + COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test); if (r->test_sba_config_reg) { - return r->test_sba_config_reg(target, legal_address, illegal_address); + return r->test_sba_config_reg(target, legal_address, num_words, + illegal_address, run_sbbusyerror_test); } else { LOG_ERROR("test_sba_config_reg is not implemented for this target."); return ERROR_FAIL; @@ -1525,12 +1527,14 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg legal_address" - "illegal_address riscv_run_sim_only_tests[on/off]", + .usage = "riscv test_sba_config_reg legal_address num_words" + "illegal_address run_sbbusyerror_test[on/off]", .help = "Perform a series of tests on the SBCS register." - "Inputs are a legal address for read/write tests," - "an illegal address for error flag/handling cases, and" - "whether sim_only tests should be run." + "Inputs are a legal, 128-byte aligned address and a number of words to" + "read/write starting at that address (i.e., address range [legal address," + "legal_address+word_size*num_words) must be legally readaable/writable)" + ", an illegal, 128-byte aligned address for error flag/handling cases," + "and whether sbbusyerror test should be run." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 2ce908d..3230285 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -118,7 +118,7 @@ typedef struct { int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, - target_addr_t illegal_address); + uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); } riscv_info_t; @@ -133,7 +133,7 @@ extern uint64_t riscv_scratch_ram_address; extern bool riscv_prefer_sba; -extern bool riscv_run_sim_only_tests; +extern bool riscv_run_sbbusyerror_test; /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ -- cgit v1.1 From 4191505b763bc9b82993d5bc2e7b1802c9552166 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Wed, 11 Apr 2018 14:38:51 -0700 Subject: Fix style issues with previous commit --- src/target/riscv/riscv-013.c | 59 ++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 5dd8232..7d89801 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -61,7 +61,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t leg uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data, uint32_t write_size, uint32_t sbcs); -uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, +uint32_t *read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t read_size, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, @@ -2849,9 +2849,9 @@ static uint32_t get_num_sbdata_regs(struct target *target) uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); - if(sbaccess128) + if (sbaccess128) return 4; - else if(sbaccess64) + else if (sbaccess64) return 2; else return 1; @@ -2884,7 +2884,7 @@ static int riscv013_test_sba_config_reg(struct target *target, uint32_t num_sbdata_regs = get_num_sbdata_regs(target); - // Test 1: Simple write/read test + /* Test 1: Simple write/read test */ test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); dmi_write(target, DMI_SBCS, sbcs); @@ -2907,10 +2907,11 @@ static int riscv013_test_sba_config_reg(struct target *target, for (uint32_t i = 0; i < num_words; i++) { uint32_t addr = legal_address + (i << sbaccess); - uint32_t* val = read_memory_sba_simple(target, addr, num_sbdata_regs, sbcs); + uint32_t *val = read_memory_sba_simple(target, addr, num_sbdata_regs, sbcs); for (uint32_t j = 0; j < num_sbdata_regs; j++) { if (((test_patterns[j]+i)&compare_mask) != (val[j]&compare_mask)) { - LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %x, read val = %x", addr, test_patterns[j]+i, val[j]); + LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x," + "expected val = %x, read val = %x", addr, test_patterns[j]+i, val[j]); test_passed = false; } } @@ -2920,7 +2921,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if (test_passed) LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED."); - // Test 2: Address autoincrement test + /* Test 2: Address autoincrement test */ target_addr_t curr_addr; target_addr_t prev_addr; test_passed = true; @@ -2965,7 +2966,8 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &val, DMI_SBDATA0); read_sbcs_nonbusy(target, &sbcs); if (i != val) { - LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address, expected val = %x, read val = %x",i,val); + LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," + "expected val = %x, read val = %x", i, val); test_passed = false; } } @@ -2973,8 +2975,8 @@ static int riscv013_test_sba_config_reg(struct target *target, if (test_passed) LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED."); - // Test 3: Read from illegal address - uint32_t* illegal_addr_read = read_memory_sba_simple(target, illegal_address, 1, sbcs_orig); + /* Test 3: Read from illegal address */ + uint32_t *illegal_addr_read = read_memory_sba_simple(target, illegal_address, 1, sbcs_orig); free(illegal_addr_read); dmi_read(target, &rd_val, DMI_SBCS); @@ -2986,7 +2988,7 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED."); } - // Test 4: Write to illegal address + /* Test 4: Write to illegal address */ write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); @@ -2998,7 +3000,7 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED."); } - // Test 5: Write with unsupported sbaccess size + /* Test 5: Write with unsupported sbaccess size */ uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128); if (sbaccess128) { @@ -3011,14 +3013,11 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); - LOG_INFO("SBCS.SBACCESS128 = %x",sbaccess128); - LOG_INFO("SBCS.SBERROR = %x",get_field(rd_val,DMI_SBCS_SBERROR)); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED."); else LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0."); @@ -3027,8 +3026,8 @@ static int riscv013_test_sba_config_reg(struct target *target, } } - // Test 6: Write to misaligned address - sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); + /* Test 6: Write to misaligned address */ + sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_write(target, DMI_SBADDRESS0, legal_address+1); @@ -3036,7 +3035,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED"); else LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0."); @@ -3050,13 +3049,11 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs); - for (int i = 0; i < 16; i++) { + for (int i = 0; i < 16; i++) dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - } - for (int i = 0; i < 16; i++) { + for (int i = 0; i < 16; i++) dmi_write(target, DMI_SBADDRESS0, legal_address); - } dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { @@ -3077,7 +3074,7 @@ static int riscv013_test_sba_config_reg(struct target *target, } void write_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t* write_data, uint32_t write_size, uint32_t sbcs) + uint32_t *write_data, uint32_t write_size, uint32_t sbcs) { RISCV013_INFO(info); @@ -3102,17 +3099,16 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, /* Write SBDATA registers starting with highest address, since write to * SBDATA0 triggers write */ - for (int i = write_size-1; i >= 0; i--) { - dmi_write(target,DMI_SBDATA0+i,write_data[i]); - } + for (int i = write_size-1; i >= 0; i--) + dmi_write(target, DMI_SBDATA0+i, write_data[i]); } -uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, +uint32_t *read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t read_size, uint32_t sbcs) { RISCV013_INFO(info); - uint32_t* rd_val = malloc(read_size*sizeof(uint32_t)); + uint32_t *rd_val = malloc(read_size*sizeof(uint32_t)); uint32_t rd_sbcs; uint32_t masked_addr; @@ -3123,7 +3119,7 @@ uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1); dmi_write(target, DMI_SBCS, sbcs_readonaddr); - // Write addresses starting with highest address register + /* Write addresses starting with highest address register */ for (int i = sba_size/32-1; i >= 0; i--) { masked_addr = (addr >> 32*i) & 0xffffffff; @@ -3135,9 +3131,8 @@ uint32_t* read_memory_sba_simple(struct target *target, target_addr_t addr, read_sbcs_nonbusy(target, &rd_sbcs); - for (uint32_t i = 0; i < read_size; i++) { + for (uint32_t i = 0; i < read_size; i++) dmi_read(target, &(rd_val[i]), DMI_SBDATA0+i); - } return rd_val; } -- cgit v1.1 From 50cd4203a5edb7a2b6d2c6c6ccdf734a722c2e77 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Wed, 11 Apr 2018 14:41:00 -0700 Subject: Fix more style issues with previous commit --- src/target/riscv/riscv-013.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 7d89801..0f622f3 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2921,7 +2921,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if (test_passed) LOG_INFO("System Bus Access Test 1: Simple write/read test PASSED."); - /* Test 2: Address autoincrement test */ + /* Test 2: Address autoincrement test */ target_addr_t curr_addr; target_addr_t prev_addr; test_passed = true; @@ -3099,7 +3099,7 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, /* Write SBDATA registers starting with highest address, since write to * SBDATA0 triggers write */ - for (int i = write_size-1; i >= 0; i--) + for (int i = write_size-1; i >= 0; i--) dmi_write(target, DMI_SBDATA0+i, write_data[i]); } -- cgit v1.1 From a9b8820916c8f7f82fa1879efcbdad4c4d2ac186 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Wed, 11 Apr 2018 18:10:48 -0700 Subject: Checkpoint: debugging tests --- src/target/riscv/riscv-013.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 0f622f3..d9df6d1 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -3007,12 +3007,10 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported."); } else { sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); - dmi_write(target, DMI_SBCS, sbcs); - write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs_orig); + write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); @@ -3028,9 +3026,10 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 6: Write to misaligned address */ sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); - dmi_write(target, DMI_SBCS, sbcs); - dmi_write(target, DMI_SBADDRESS0, legal_address+1); + write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs); + + dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); -- cgit v1.1 From 1ba3986eb78cdd02e12c99f2f3a8ba0766ddeac8 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 12 Apr 2018 12:26:54 -0700 Subject: More test/SBA RTL debug --- src/target/riscv/riscv-013.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d9df6d1..0508145 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -3027,9 +3027,9 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 6: Write to misaligned address */ sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); - write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs); + write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); + dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); -- cgit v1.1 From 065671b3116d1cf87cf1bb89f980d08a74ccfa3f Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Fri, 13 Apr 2018 11:20:12 -0700 Subject: Code style cleanup --- src/target/riscv/riscv-013.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 0508145..a542c09 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -61,8 +61,8 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t leg uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data, uint32_t write_size, uint32_t sbcs); -uint32_t *read_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t read_size, uint32_t sbcs); +void read_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, uint64_t value); @@ -2884,6 +2884,8 @@ static int riscv013_test_sba_config_reg(struct target *target, uint32_t num_sbdata_regs = get_num_sbdata_regs(target); + uint32_t rd_buf[num_sbdata_regs]; + /* Test 1: Simple write/read test */ test_passed = true; sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); @@ -2894,8 +2896,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); - uint32_t compare_mask = (sbaccess == 0) ? 0xff : - (sbaccess == 1) ? 0xffff : 0xffffffff; + uint32_t compare_mask = (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff; for (uint32_t i = 0; i < num_words; i++) { uint32_t addr = legal_address + (i << sbaccess); @@ -2907,15 +2908,14 @@ static int riscv013_test_sba_config_reg(struct target *target, for (uint32_t i = 0; i < num_words; i++) { uint32_t addr = legal_address + (i << sbaccess); - uint32_t *val = read_memory_sba_simple(target, addr, num_sbdata_regs, sbcs); + read_memory_sba_simple(target, addr, rd_buf, num_sbdata_regs, sbcs); for (uint32_t j = 0; j < num_sbdata_regs; j++) { - if (((test_patterns[j]+i)&compare_mask) != (val[j]&compare_mask)) { + if (((test_patterns[j]+i)&compare_mask) != (rd_buf[j]&compare_mask)) { LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x," - "expected val = %x, read val = %x", addr, test_patterns[j]+i, val[j]); + "expected val = %x, read val = %x", addr, test_patterns[j]+i, rd_buf[j]); test_passed = false; } } - free(val); } } if (test_passed) @@ -2976,8 +2976,7 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_INFO("System Bus Access Test 2: Address auto-increment test PASSED."); /* Test 3: Read from illegal address */ - uint32_t *illegal_addr_read = read_memory_sba_simple(target, illegal_address, 1, sbcs_orig); - free(illegal_addr_read); + read_memory_sba_simple(target, illegal_address, rd_buf, 1, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { @@ -3102,12 +3101,11 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, dmi_write(target, DMI_SBDATA0+i, write_data[i]); } -uint32_t *read_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t read_size, uint32_t sbcs) +void read_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs) { RISCV013_INFO(info); - uint32_t *rd_val = malloc(read_size*sizeof(uint32_t)); uint32_t rd_sbcs; uint32_t masked_addr; @@ -3131,9 +3129,7 @@ uint32_t *read_memory_sba_simple(struct target *target, target_addr_t addr, read_sbcs_nonbusy(target, &rd_sbcs); for (uint32_t i = 0; i < read_size; i++) - dmi_read(target, &(rd_val[i]), DMI_SBDATA0+i); - - return rd_val; + dmi_read(target, &(rd_buf[i]), DMI_SBDATA0+i); } int riscv013_dmi_write_u64_bits(struct target *target) -- cgit v1.1 From bf0ffff1db194b11d2b3e512b624e5309fa112db Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Fri, 13 Apr 2018 16:09:57 -0700 Subject: Fix issue with COMMAND_PARSE_NUMBER --- src/target/riscv/riscv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index d1bd5e6..0f8443f 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1442,9 +1442,10 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) uint32_t num_words; target_addr_t illegal_address; bool run_sbbusyerror_test; - COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], legal_address); + + COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words); - COMMAND_PARSE_NUMBER(u64, CMD_ARGV[2], illegal_address); + COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address); COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test); if (r->test_sba_config_reg) { -- cgit v1.1 From 0b027a2854acd18677febb038b822f70f62c3987 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Mon, 16 Apr 2018 17:20:31 -0700 Subject: Code cleanup. Bump debug_defines.h version --- src/target/riscv/riscv-013.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index a542c09..2e44e03 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -57,12 +57,6 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, - uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); -void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data, - uint32_t write_size, uint32_t sbcs); -void read_memory_sba_simple(struct target *target, target_addr_t addr, - uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); static int register_write_direct(struct target *target, unsigned number, uint64_t value); @@ -70,6 +64,12 @@ static int read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); static int write_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer); +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, + uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); +void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t* write_data, + uint32_t write_size, uint32_t sbcs); +void read_memory_sba_simple(struct target *target, target_addr_t addr, + uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs); /** * Since almost everything can be accomplish by scanning the dbus register, all @@ -269,7 +269,7 @@ static dm013_info_t *get_dm(struct target *target) static uint32_t hartsel_mask(const struct target *target) { RISCV013_INFO(info); - return ((1L<hartsellen)-1) << DMI_DMCONTROL_HARTSEL_OFFSET; + return ((1L<hartsellen)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET; } static void decode_dmi(char *text, unsigned address, unsigned data) @@ -283,7 +283,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) { DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" }, { DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" }, - { DMI_DMCONTROL, ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET, "hartsel" }, + { DMI_DMCONTROL, ((1L<<10)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET, "hartsel" }, { DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" }, @@ -1288,7 +1288,7 @@ static int examine(struct target *target) dm->was_reset = true; } - uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET; + uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSELLO_OFFSET; dmi_write(target, DMI_DMCONTROL, max_hartsel_mask | DMI_DMCONTROL_DMACTIVE); uint32_t dmcontrol; if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) @@ -1494,11 +1494,11 @@ static int init_target(struct command_context *cmd_ctx, generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64; generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64; generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits; - generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->authdata_read = &riscv013_authdata_read; generic_info->authdata_write = &riscv013_authdata_write; generic_info->dmi_read = &dmi_read; generic_info->dmi_write = &dmi_write; + generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->version_specific = calloc(1, sizeof(riscv013_info_t)); if (!generic_info->version_specific) return ERROR_FAIL; @@ -2818,6 +2818,7 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf) buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0); } +/* Helper function for riscv013_test_sba_config_reg */ static int get_max_sbaccess(struct target *target) { RISCV013_INFO(info); @@ -2847,7 +2848,7 @@ static uint32_t get_num_sbdata_regs(struct target *target) RISCV013_INFO(info); uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); if (sbaccess128) return 4; @@ -2939,7 +2940,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); curr_addr = sb_read_address(target); - if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); test_passed = false; } @@ -2959,7 +2960,7 @@ static int riscv013_test_sba_config_reg(struct target *target, prev_addr = curr_addr; read_sbcs_nonbusy(target, &sbcs); curr_addr = sb_read_address(target); - if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && i != 0) { + if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); test_passed = false; } @@ -3010,7 +3011,7 @@ static int riscv013_test_sba_config_reg(struct target *target, write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { + if (get_field(rd_val, DMI_SBCS_SBERROR) == 4) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1); dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); -- cgit v1.1 From 4f4d5f46f1413ac0acad43e59955a620c743fc71 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Tue, 17 Apr 2018 10:35:32 -0700 Subject: Fix build issues --- src/target/riscv/debug_defines.h | 211 +++++++++++++++++---------------------- src/target/riscv/riscv-013.c | 26 +++-- 2 files changed, 109 insertions(+), 128 deletions(-) diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 04500e5..7308bb9 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -245,6 +245,16 @@ #define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) /* +* When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. +* +* Since an NMI can indicate a hardware error condition, +* reliable debugging may no longer be possible once this bit becomes set. +* This is implementation-dependent. + */ +#define CSR_DCSR_NMIP_OFFSET 3 +#define CSR_DCSR_NMIP_LENGTH 1 +#define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET) +/* * When set and not in Debug Mode, the hart will only execute a single * instruction and then enter Debug Mode. * If the instruction does not complete due to an exception, @@ -343,6 +353,16 @@ #define CSR_MCONTROL_MASKMAX_LENGTH 6 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) /* +* If this optional bit is implemented, the hardware sets it when this +* trigger matches. The trigger's user can set or clear it at any +* time. The trigger's user can use this bit to determine which +* trigger(s) matched. If the bit is not implemented, it is always 0 +* and writing it has no effect. + */ +#define CSR_MCONTROL_HIT_OFFSET 20 +#define CSR_MCONTROL_HIT_LENGTH 1 +#define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET) +/* * 0: Perform a match on the virtual address. * * 1: Perform a match on the data value loaded/stored, or the @@ -368,7 +388,7 @@ * which case the debugger has a little more control. * * Data load triggers with \Ftiming of 0 will result in the same load -* happening again when the debugger lets the core run. For data load +* happening again when the debugger lets the hart run. For data load * triggers, debuggers must first attempt to set the breakpoint with * \Ftiming of 1. * @@ -479,6 +499,16 @@ #define CSR_ICOUNT_DMODE_LENGTH 1 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) /* +* If this optional bit is implemented, the hardware sets it when this +* trigger matches. The trigger's user can set or clear it at any +* time. The trigger's user can use this bit to determine which +* trigger(s) matched. If the bit is not implemented, it is always 0 +* and writing it has no effect. + */ +#define CSR_ICOUNT_HIT_OFFSET 24 +#define CSR_ICOUNT_HIT_LENGTH 1 +#define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET) +/* * When count is decremented to 0, the trigger fires. Instead of * changing \Fcount from 1 to 0, it is also acceptable for hardware to * clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired @@ -674,7 +704,7 @@ */ #define DMI_DMCONTROL_HALTREQ_OFFSET 31 #define DMI_DMCONTROL_HALTREQ_LENGTH 1 -#define DMI_DMCONTROL_HALTREQ (0x1ULL << DMI_DMCONTROL_HALTREQ_OFFSET) +#define DMI_DMCONTROL_HALTREQ (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET) /* * Writes the resume request bit for all currently selected harts. * When set to 1, each selected hart will resume if it is currently @@ -687,7 +717,7 @@ */ #define DMI_DMCONTROL_RESUMEREQ_OFFSET 30 #define DMI_DMCONTROL_RESUMEREQ_LENGTH 1 -#define DMI_DMCONTROL_RESUMEREQ (0x1ULL << DMI_DMCONTROL_RESUMEREQ_OFFSET) +#define DMI_DMCONTROL_RESUMEREQ (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET) /* * This optional field writes the reset bit for all the currently * selected harts. To perform a reset the debugger writes 1, and then @@ -701,7 +731,7 @@ */ #define DMI_DMCONTROL_HARTRESET_OFFSET 29 #define DMI_DMCONTROL_HARTRESET_LENGTH 1 -#define DMI_DMCONTROL_HARTRESET (0x1ULL << DMI_DMCONTROL_HARTRESET_OFFSET) +#define DMI_DMCONTROL_HARTRESET (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET) /* * Writing 1 to this bit clears the {\tt havereset} bits for * any selected harts. @@ -710,7 +740,7 @@ */ #define DMI_DMCONTROL_ACKHAVERESET_OFFSET 28 #define DMI_DMCONTROL_ACKHAVERESET_LENGTH 1 -#define DMI_DMCONTROL_ACKHAVERESET (0x1ULL << DMI_DMCONTROL_ACKHAVERESET_OFFSET) +#define DMI_DMCONTROL_ACKHAVERESET (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET) /* * Selects the definition of currently selected harts. * @@ -720,20 +750,27 @@ * plus those selected by the hart array mask register. * * An implementation which does not implement the hart array mask register -* should tie this field to 0. A debugger which wishes to use the hart array +* must tie this field to 0. A debugger which wishes to use the hart array * mask register feature should set this bit and read back to see if the functionality * is supported. */ #define DMI_DMCONTROL_HASEL_OFFSET 26 #define DMI_DMCONTROL_HASEL_LENGTH 1 -#define DMI_DMCONTROL_HASEL (0x1ULL << DMI_DMCONTROL_HASEL_OFFSET) +#define DMI_DMCONTROL_HASEL (0x1U << DMI_DMCONTROL_HASEL_OFFSET) /* -* The DM-specific index of the hart to select. This hart is always part of the -* currently selected harts. +* The low 10 bits of \Fhartsel: the DM-specific index of the hart to +* select. This hart is always part of the currently selected harts. */ -#define DMI_DMCONTROL_HARTSEL_OFFSET 16 -#define DMI_DMCONTROL_HARTSEL_LENGTH HARTSELLEN -#define DMI_DMCONTROL_HARTSEL (((1L< Date: Tue, 17 Apr 2018 10:47:44 -0700 Subject: Fix style issues. Code cleanup. --- src/target/riscv/riscv-013.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 45b7ca9..1f1575c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -283,7 +283,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) { DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" }, { DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO, "hartsel" }, + { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO, "hartsello" }, { DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" }, @@ -2941,7 +2941,7 @@ static int riscv013_test_sba_config_reg(struct target *target, read_sbcs_nonbusy(target, &sbcs); curr_addr = sb_read_address(target); if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { - LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess); test_passed = false; } dmi_write(target, DMI_SBDATA0, i); @@ -2968,7 +2968,7 @@ static int riscv013_test_sba_config_reg(struct target *target, read_sbcs_nonbusy(target, &sbcs); if (i != val) { LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," - "expected val = %x, read val = %x", i, val); + "expected val = %x, read val = %x.", i, val); test_passed = false; } } @@ -3000,7 +3000,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 2); dmi_write(target, DMI_SBCS,sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); else LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0."); -- cgit v1.1 From 9089854b84166c4ad8b4075b652fbde52e6ba91e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Tue, 24 Apr 2018 13:58:09 -0700 Subject: Code cleanup from feedback. --- src/target/riscv/riscv-013.c | 11 +++++++---- src/target/riscv/riscv.h | 2 -- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1f1575c..21000bc 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2824,9 +2824,9 @@ static int get_max_sbaccess(struct target *target) RISCV013_INFO(info); uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); - uint32_t sbaccess16 = get_field(info->sbcs, DMI_SBCS_SBACCESS16); + uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); + uint32_t sbaccess16 = get_field(info->sbcs, DMI_SBCS_SBACCESS16); uint32_t sbaccess8 = get_field(info->sbcs, DMI_SBCS_SBACCESS8); if (sbaccess128) @@ -2849,13 +2849,16 @@ static uint32_t get_num_sbdata_regs(struct target *target) uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); if (sbaccess128) return 4; else if (sbaccess64) return 2; - else + else if (sbaccess32) return 1; + else + return 0; } static int riscv013_test_sba_config_reg(struct target *target, diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 3230285..d724538 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -133,8 +133,6 @@ extern uint64_t riscv_scratch_ram_address; extern bool riscv_prefer_sba; -extern bool riscv_run_sbbusyerror_test; - /* Everything needs the RISC-V specific info structure, so here's a nice macro * that provides that. */ static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused)); -- cgit v1.1 From 0ed96e80d3f9b8828e6c3ca33ae91b0da6543c33 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Tue, 24 Apr 2018 14:15:30 -0700 Subject: Fix more style issues Signed-off-by: Ryan Macdonald --- src/target/riscv/riscv-013.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 21000bc..1cfda35 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -2957,7 +2957,7 @@ static int riscv013_test_sba_config_reg(struct target *target, uint32_t val; sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read + dmi_read(target, &val, DMI_SBDATA0); /* Dummy read to trigger first system bus read */ curr_addr = legal_address; for (uint32_t i = 0; i < num_words; i++) { prev_addr = curr_addr; @@ -3001,7 +3001,7 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 2); - dmi_write(target, DMI_SBCS,sbcs); + dmi_write(target, DMI_SBCS, sbcs); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); -- cgit v1.1 From 2608b8e25dc6a8d29658b66055ce1d942052cdb3 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 29 Aug 2018 16:00:51 -0700 Subject: Fix strange merge. --- src/target/riscv/debug_defines.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 0cabf15..d6ddd4f 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -1219,8 +1219,6 @@ * * An implementation may report "Other" (7) for any error condition. * -* An implementation may report "Other" (7) for any error condition. -* * 0: There was no bus error. * * 1: There was a timeout. -- cgit v1.1 From a0afcba66dda9b3213fc061dd744c79eaa134dc4 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 29 Aug 2018 16:05:54 -0700 Subject: Fix typo. --- src/target/riscv/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index dbfaf59..7b965f2 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1645,7 +1645,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { .help = "Perform a series of tests on the SBCS register." "Inputs are a legal, 128-byte aligned address and a number of words to" "read/write starting at that address (i.e., address range [legal address," - "legal_address+word_size*num_words) must be legally readaable/writable)" + "legal_address+word_size*num_words) must be legally readable/writable)" ", an illegal, 128-byte aligned address for error flag/handling cases," "and whether sbbusyerror test should be run." }, -- cgit v1.1 From 583c90e87ccc30719d215ae8f7ed96c9374d69fc Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Fri, 31 Aug 2018 14:26:32 -0700 Subject: Add pass message for SBA and compliance tests Signed-off-by: Ryan Macdonald --- src/target/riscv/riscv-013.c | 56 +++++++++++++++++++++++++++++++++----------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d3afc8a..ed1127e 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -71,7 +71,7 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t uint32_t write_size, uint32_t sbcs); void read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t *rd_buf, uint32_t read_size, uint32_t sbcs); -static int riscv013_test_compliance(struct target *target); +static int riscv013_test_compliance(struct target *target); /** * Since almost everything can be accomplish by scanning the dbus register, all @@ -2991,6 +2991,8 @@ static int riscv013_test_sba_config_reg(struct target *target, { LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); + uint32_t tests_failed = 0; + uint32_t rd_val; uint32_t sbcs_orig; dmi_read(target, &sbcs_orig, DMI_SBCS); @@ -3006,7 +3008,7 @@ static int riscv013_test_sba_config_reg(struct target *target, } if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { - LOG_ERROR("System Bus Access unsupported SBVERSION (0). Only version 1 is supported."); + LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", get_field(sbcs, DMI_SBCS_SBVERSION)); return ERROR_FAIL; } @@ -3042,6 +3044,7 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x," "expected val = %x, read val = %x", addr, test_patterns[j]+i, rd_buf[j]); test_passed = false; + tests_failed++; } } } @@ -3070,6 +3073,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess); test_passed = false; + tests_failed++; } dmi_write(target, DMI_SBDATA0, i); } @@ -3090,6 +3094,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); test_passed = false; + tests_failed++; } dmi_read(target, &val, DMI_SBDATA0); read_sbcs_nonbusy(target, &sbcs); @@ -3097,6 +3102,7 @@ static int riscv013_test_sba_config_reg(struct target *target, LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," "expected val = %x, read val = %x.", i, val); test_passed = false; + tests_failed++; } } } @@ -3129,10 +3135,13 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); - else + else { LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0."); + tests_failed++; + } } else { LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to set error code."); + tests_failed++; } /* Test 5: Write with unsupported sbaccess size */ @@ -3152,10 +3161,13 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED."); - else + else { LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0."); + tests_failed++; + } } else { LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to set error code."); + tests_failed++; } } @@ -3171,10 +3183,13 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED"); - else + else { LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0."); + tests_failed++; + } } else { LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to set error code."); + tests_failed++; } /* Test 7: Set sbbusyerror, only run this case in simulation as it is likely @@ -3196,14 +3211,24 @@ static int riscv013_test_sba_config_reg(struct target *target, dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED."); - else + else { LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0."); + tests_failed++; + } } else { LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to set error code."); + tests_failed++; } } - return ERROR_OK; + if (tests_failed == 0) { + LOG_INFO("ALL TESTS PASSED"); + return ERROR_OK; + } + else { + LOG_ERROR("%d TESTS FAILED", tests_failed); + return ERROR_FAIL; + } } @@ -3476,8 +3501,8 @@ int riscv013_test_compliance(struct target *target) this all into one PB execution. Which may not be possible on all implementations.*/ if (info->progbufsize >= 5) { for (testval = 0x0011223300112233; - testval != 0xDEAD; - testval = testval == 0x0011223300112233 ? ~testval : 0xDEAD) { + testval != 0xDEAD; + testval = testval == 0x0011223300112233 ? ~testval : 0xDEAD) { COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, testval) == ERROR_OK, "Need to be able to write S0 in order to test DSCRATCH."); struct riscv_program program32; @@ -3611,7 +3636,7 @@ int riscv013_test_compliance(struct target *target) /* Basic Abstract Commands */ for (unsigned int i = 1; i < 32; i = i << 1) { - riscv_reg_t testval = i | ((i + 1ULL) << 32); + riscv_reg_t testval = i | ((i + 1ULL) << 32); riscv_reg_t testval_read; COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_ZERO + i, testval), "GPR Writes should be supported."); @@ -3825,10 +3850,13 @@ int riscv013_test_compliance(struct target *target) /* Halt every hart for any follow-up tests*/ COMPLIANCE_MUST_PASS(riscv_halt_all_harts(target)); - LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests); - - if (total_tests == passed_tests) + uint32_t failed_tests = total_tests - passed_tests; + if (total_tests == passed_tests) { + LOG_INFO("ALL TESTS PASSED\n"); return ERROR_OK; - else + } + else { + LOG_INFO("%d TESTS FAILED\n", failed_tests); return ERROR_FAIL; + } } -- cgit v1.1 From 3516fd50197acaeff8e933d0e67028b6582c1cb5 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Fri, 31 Aug 2018 14:29:09 -0700 Subject: Style fixes Signed-off-by: Ryan Macdonald --- src/target/riscv/riscv-013.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index ed1127e..c1cae62 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -3008,7 +3008,8 @@ static int riscv013_test_sba_config_reg(struct target *target, } if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { - LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", get_field(sbcs, DMI_SBCS_SBVERSION)); + LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", + get_field(sbcs, DMI_SBCS_SBVERSION)); return ERROR_FAIL; } @@ -3224,8 +3225,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if (tests_failed == 0) { LOG_INFO("ALL TESTS PASSED"); return ERROR_OK; - } - else { + } else { LOG_ERROR("%d TESTS FAILED", tests_failed); return ERROR_FAIL; } @@ -3854,8 +3854,7 @@ int riscv013_test_compliance(struct target *target) if (total_tests == passed_tests) { LOG_INFO("ALL TESTS PASSED\n"); return ERROR_OK; - } - else { + } else { LOG_INFO("%d TESTS FAILED\n", failed_tests); return ERROR_FAIL; } -- cgit v1.1 From 631f6cd55b6b7a34b194c8d51c573ec60926ff56 Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Fri, 31 Aug 2018 14:30:17 -0700 Subject: More style fixes Signed-off-by: Ryan Macdonald --- src/target/riscv/riscv-013.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index c1cae62..34ec3c6 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -3009,7 +3009,7 @@ static int riscv013_test_sba_config_reg(struct target *target, if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", - get_field(sbcs, DMI_SBCS_SBVERSION)); + get_field(sbcs, DMI_SBCS_SBVERSION)); return ERROR_FAIL; } -- cgit v1.1