From 19f7b5c43c24977f24059e88477410658b7da466 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 20 May 2021 11:50:34 -0700 Subject: Add keepalive for vector register access. (#611) (And whatever else does a lot of register writes.) Change-Id: I86a1a784fb7b9430aa470dbb39a495b89f56d8c9 Signed-off-by: Tim Newsome --- src/target/riscv/riscv-013.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index cfc040c..cb963d8 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1307,6 +1307,8 @@ static int register_write_direct(struct target *target, unsigned number, LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target), gdb_regno_name(number), value); + keep_alive(); + int result = register_write_abstract(target, number, value, register_size(target, number)); if (result == ERROR_OK || !has_sufficient_progbuf(target, 2) || -- cgit v1.1