riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2014-06-22	openrisc: add support for JTAG Serial Port	Franck Jullien	1	-2/+4
	Change-Id: I623a8c74bcca2edb5f996b69c02d73a6f67b7d34 Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-on: http://openocd.zylin.com/2162 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-12-14	topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc	Sergio Chico	1	-0/+17
	This add support to the Xilinx BSCAN_* virtual JTAG interface. This is the Xilinx equivalent of the Altera sld_virtual_jtag interface, it allows a user to connect to the debug unit through the main FPGA JTAG connection. Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188 Signed-off-by: Sergio Chico <sergio.chico@gmail.com> Reviewed-on: http://openocd.zylin.com/1806 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-26	Add new target type: OpenRISC	Franck Jullien	1	-0/+53
	Add support for OpenRISC target. This implementation supports the adv_debug_sys debug unit core. The mohor dbg_if is not supported. Support for mohor TAP core and Altera Virtual JTAG core are also provided. Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72 Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-on: http://openocd.zylin.com/1547 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>