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This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.
Conflicts:
.travis.yml
contrib/loaders/flash/stm32/stm32f1x.S
contrib/loaders/flash/stm32/stm32f2x.S
doc/openocd.texi
src/rtos/FreeRTOS.c
src/server/gdb_server.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/riscv/riscv_semihosting.c
tcl/target/esp_common.cfg
tcl/target/gd32vf103.cfg
tools/scripts/checkpatch.pl
Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
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For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl/ target| while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7027
Tested-by: jenkins
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Conflicts:
tcl/target/gd32vf103.cfg
I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.
Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
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The flash is compatible with stm32f1x, reuse the driver.
Extend the size of work area to RAM size of the smallest device.
Stop watchdogs before flash programming.
Change-Id: I67a7654a6e196f9d4b2409edaa7990c53334437e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6711
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
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After compiling OpenOCD from source (commit: 6edf98db7), OpenOCD could not connect with the target board which is a GD32VF103T_START development board,
when I used the command: openocd -f "interface/cmsis-dap.cfg" -f "target/gd32vf103.cfg"
Issue 1: The clock speed hasn't been set, the error message given is:
Error: CMSIS-DAP command CMD_DAP_SWJ_CLOCK failed.
Which can be solved by adding a clock speed setting to the gd32vf103.cfg file:
adapter speed 1000
Issue 2: The default transport is not set to jtag, which it requires, the error shown is:
Open On-Chip Debugger 0.11.0+dev-01861-g6edf98db7-dirty (2021-08-25-10:18)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "swd". To override use 'transport select <transport>'.
embedded:startup.tcl:128: Error: session transport is "swd" but your config requires JTAG
in procedure 'script'
at file "embedded:startup.tcl", line 26
in procedure 'jtag' called at file "/home/user/riscv-openocd-tool/usr/local/bin/../share/openocd/scripts/target/gd32vf103.cfg", line 9
in procedure 'default_to_jtag' called at file "embedded:startup.tcl", line 133
at file "embedded:startup.tcl", line 128
This issue can be solved by adding the line:
transport select jtag
After adding these two lines, OpenOCD could connect to the development board successfully. Programming the flash also works.
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* riscv: work around buggy hart states during reset in some DMs
As described in the comment this change adds, the GD32VF103 DM reports
that the hart is in more than one state while it is resetting. Because
of this, the current code acknowledges resets before they actually
complete. This sometimes prevents havereset from getting cleared as
intended, leading to a spurious "Hart 0 unexpectedly reset!" message the
next time riscv_is_halted() gets called.
To work around this, check for the absence of the unavailable state
rather than the presence of the running or halted states. This behavior
is also arguably more true to the spec than what exists now: Section 3.2
states that "The system may take an arbitrarily long time to come out of
reset, as reported by allunavail, anyunavail."
Change-Id: I34e90a16233125608bce8e4c2414dbead637600e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* riscv: support custom reset-assert scripts
The reset-assert event is used, if present, to override the default
reset logic for ARM and MIPS cores. Do the same for RISC-V so that
devices with buggy ndmreset functionality (like GD32VF103) or
nonstandard reset sequences can specify the appropriate logic in Tcl.
Change-Id: I5e12077d67509853edb8ef3ad3f037f293a5fbb6
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target: support GD32VF103 RISC-V MCU
The GD32VF103 is a low-cost 32-bit RISC-V microcontroller with
peripherals that are more-or-less compatible with the STM32F103 ARM
microcontroller. It is available on several low-cost dev boards, such as
the Sipeed Longan Nano, which is what I am testing on.
Add initial support for this chip, including a workaround for a buggy
ndmreset line (i.e. one that doesn't actually trigger a reset) in its
integrated debug module. Use the existing GD32VF103 flash driver that
was ported from the vendor's code in commit 48e40f351325 ("Add support
for GD32VF103 flash").
Change-Id: Iadac47ceb5437b8e18f3d35901388f10fef9f876
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
* tcl/target/gd32vf103: add main flash alias
The GD32VF103 creates an alias to either main flash or the bootloader at
0x0, depending on how it was booted. As such, we want to indicate to
debuggers that the memory at 0x0 is flash and so cannot support software
breakpoints. To do this, add an alias to the main flash in the config.
This isn't strictly accurate in the case where we're running the
bootloader, but it still suits our purpose of fixing breakpoint
behavior.
Change-Id: I9eb8462d354f096eee231c0e5e2bffa538a5903e
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
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There is no flash bank support at the moment.
Change-Id: I52a2bde39425d94d9333cda002e5df0a1ef63c08
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/5755
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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