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2023-09-23jtagspi/pld: add interface to get support from pld driversDaniel Anselmi1-2/+10
Jtagspi is using a proxy bitstream to "connect" JTAG to the SPI pins. This is not possible with all FPGA vendors/families. In this cases a dedicated procedure is needed to establish such a connection. This patch adds a jtagspi-mode for these cases. It also adds the needed interfaces to jtagspi and the pld-driver so the driver can select the mode and provide the necessary procedures. For the cases where a proxy bitstream is needed, the pld driver will select the mode and provide instruction code needed in this case. Change-Id: I9563f26739589157b39a3664a73d91152cd13f77 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7822 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14tcl/ultrascale: add more ultrascale devicesDaniel Anselmi1-26/+73
Add more ultrascale devices. Set instruction codes for SSI devices such that refresh/program read_stat and user registers will work. Change-Id: Id0a0706f4016eb8a4732725a5b72ae61efd73421 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7716 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-14tcl/cpld: add config files for virtex-7 devices with ir-length > 6Daniel Anselmi4-9/+90
Adding a single file for each different ir-length. Change-Id: Iba3dd55b91c28fdb4d0cafa1ededd939fe61a267 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7715 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08pld/virtex2: add program/refresh commandDaniel Anselmi3-0/+4
Change-Id: If6d237a6f27c4232849f73d08e7ca74276e6d464 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7714 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08tcl/cpld: add config files for more xilinx fpga familiesDaniel Anselmi8-1/+193
Use configurable virtex pld driver to add support for more xilinx fpga families. Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7352 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08pld: give devices a name for referencing in scriptsDaniel Anselmi3-3/+3
Change-Id: I05e8596ffacdb6cd8da4dd8a40bb460183f4930a Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7728 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27flash/jtagspi: sending command and setting parameters without probing.Daniel Anselmi1-1/+11
Change-Id: I6b9d90265ca5112b9ab2aae97bb4c6cf3ebc4112 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7432 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-04-30pld: add support for altera/intel devicesDaniel Anselmi5-24/+83
Change-Id: I7977d39c9037ae71139f78c8d381f5f925dc3489 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7355 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-14tcl: cpld/xilinx-xc7: remove virtex-7 devices with ir-length > 6Daniel Anselmi1-8/+10
They have an ir length of 22, 24 or 38 bit and different command codes. Change-Id: I488e8613f1c4d017e1590111f60b2725ec62964b Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7387 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-11tcl/cpld/xilinx-xcu: fix typoGeorge Voicu1-1/+1
Fix typo in comments Signed-off-by: George Voicu <razvanvg@hotmail.com> Change-Id: Icc2d770e73f896e20dd347de324328030544bdb9 Reviewed-on: https://review.openocd.org/c/openocd/+/7333 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-06-24tcl: add SPDX tagAntonio Borneo10-0/+20
For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl | while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7030 Tested-by: jenkins
2022-02-26cpld: altera-epm240: Increase adapter speedSean Anderson1-0/+4
According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26cpld: altera-epm240: Add additional IDCODEsSean Anderson1-1/+14
This adds some additional IDCODEs from the datasheet. It also adds support for customizing the tap name. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-10-27xilinx-xc7: Add additional IDCODEs.William D. Jones1-0/+8
Add/detect missing IDCODEs for the Spartan 7 family and Artix 25T and Artix 12T. Change-Id: Ib6c83c5592e90df1eb8e715e79b279da9a95f9c6 Signed-off-by: William D. Jones <wjones@wdj-consulting.com> Reviewed-on: http://openocd.zylin.com/4428 Reviewed-by: Robert Jördens Tested-by: jenkins Reviewed-by: Rohit Singh <rohit91.2008@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30xilinx-xcu: add Xilinx Ultrascale tap dataRobert Jordens1-0/+72
The Ultrascale series is a bit more complicated to handle since with the stacked and interconnected dies the IR gets longer. This adds support for all currently known chips from the Ultrascale family. Change-Id: Ibac325dd6fadc76f73cc682b1c62c1a5f39f0786 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4188 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-13jtagspi: new protocol that includes transfer lengthRobert Jordens1-7/+1
This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13XCF (Xilinx platfrom flash) support.barthess2-0/+36
Change-Id: I4ee6db5f0abdb9fd279cc0edd13f71952a9d295d Signed-off-by: Uladzimir Pylinski <barthess@yandex.ru> Reviewed-on: http://openocd.zylin.com/3914 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-09tcl/cpld: add config file for Altera 5M570Z CPLD (MAXV family)Moritz Fischer1-0/+6
Change-Id: I229c746be27b7c4fa01f48a6ed54ab2679b50ab1 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/4109 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-08-14tcl/cpld: add config file for Altera EPM240 CPLD (MAXII family)Antony Pavlov1-0/+6
Change-Id: I5e589cf9d1d762321b7baa2509a4e78688fe6512 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/3607 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-08-10xilinx-xc7: correct Artix7 15T IDCODEFelix Held1-1/+1
The IDCODE of Artix7 15T in the UG470 is wrong; Artix7 35T and 15T don't have the same IDCODE. I've tested this on real hardware. Change-Id: Iac267dc449c23454dd119126749dbeb8267c18ac Signed-off-by: Felix Held <felix-openocd@felixheld.de> Reviewed-on: http://openocd.zylin.com/3633 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2015-10-21tcl: Support for reading "Device DNA" from Spartan 6 devices.Tim 'mithro' Ansell1-0/+36
Most Xilinx FPGA devices contain an embedded, unique device identifier called the "Device DNA". The identifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable providing a great serial / tracking number. Debugging was done in https://github.com/timvideos/HDMI2USB/issues/36 Change-Id: Iad03eafb40887f0321a4dc22858a7c3bf37a12b3 Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Reviewed-on: http://openocd.zylin.com/2960 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-08-06kc705: digilent-jtag/kintex7/jtagspi boardRobert Jordens1-0/+57
Xilinx Kintex7 Development board with integrated Digilent JTAG-SMT1 (a.k.a. HS1) interface and a 128 MBit SPI flash. Change-Id: I9daba0a2fb2c17e04bcb37bd41872ebde25e0d2f Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2861 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06pipistrello: ftdi-jtag/spartan6/jtagspi boardRobert Jordens1-0/+54
The Pipistrello is a low cost FPGA board with a Xilinx Spartan6 LX45, a SPI flash and onboard FTDI JTAG. This board is a good example use case for the jtagspi flash driver talking through a proxy bitstream. Change-Id: I04a80610ff825c36ebcb67b879507028eed141ad Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2846 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06flash/nor/jtagspi: add JTAGSPI driverRobert Jordens1-0/+43
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-07-17Add config file for Lattice LC4032ZE CPLD (ispMACH 4000ZE family)Freddie Chopin1-0/+3
Change-Id: Iefec12b30ff737317c454b472200fd7e7edde619 Signed-off-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-on: http://openocd.zylin.com/748 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
2009-10-12Xilinx xcr3256.cfg basic config scriptWookey1-0/+3
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