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2019-09-27Fix the build.Tim Newsome2-18/+5
Change-Id: I3a314488136ec47611d660140fb5dd70c00be59c
2019-09-27Update libjaylink.Tim Newsome3-2/+97
Change-Id: I9b8d7a5b9356c962d625e541f917c5dd74f47a98
2019-09-27Merge branch 'master' into from_upstreamTim Newsome166-4407/+2714
Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8
2019-09-24Perform SBA writes with batch transactions for improved performance. (#405)darius-bluespec3-18/+60
* Add riscv_batch_available_scans(). This function will query the number of available scans in a batch. * Perform SBA writes with batch transactions for improved performance. Using batch transactions avoids an unnecessary dmi read after every dmi write, resulting in a significant performance improvement.
2019-09-24src/jtag/aice: Fix obviously incorrect bit op.Seth LaForge1-1/+1
Fix expression "(pin_status | 0x4)" which was always true rather than testing a bit. Untested - was clearly not expressing the intent of the author by inspection. Found by automated tooling and rtrieu@google.com. Signed-off-by: Seth LaForge <sethml@google.com> Change-Id: I4bb91e60e8ce9757bf21976cc48de6f85a39c68d Reviewed-on: http://openocd.zylin.com/5301 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24helper/command: clear errno before calling parserChristopher Head1-0/+1
The C standard says that errno is set to ERANGE if an out-of-range value is returned by strtol, strtoul, et. al., but it does not say that errno is cleared if the function is successful (and, indeed, it is not on glibc). This means that, if errno is ERANGE before strtol is called, and if the value to be converted is exactly the maximum (or, for a signed conversion, the minimum) legal value, COMMAND_PARSE_NUMBER will erroneously indicate that the value is out of range. Change-Id: I8a8b50a815b408a38235968f1c1d70297ea1a6aa Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5298 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-24flash/nor/tcl: Fix usage of 'flash erase_sector' commandMarc Schink1-1/+1
Change-Id: I2141e377a0531cab8d1140049a2ee7721d30cfdc Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5299 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-18esirisc_flash: Rename PAGE_SIZE to FLASH_PAGE_SIZEKhem Raj1-4/+4
PAGE_SIZE is defined in system includes on some systems, this would avoid the unintended conflict Fixes | src/flash/nor/esirisc_flash.c:95:9: error: 'PAGE_SIZE' macro redefined [-Werror,-Wmacro-redefined] | #define PAGE_SIZE 4096 | ^ | /mnt/a/yoe/build/tmp/work/core2-64-yoe-linux-musl/openocd/0.10+gitrAUTOINC+7ee618692f-r0/recipe-sysroot/usr/inclu de/limits.h:89:9: note: previous definition is here | #define PAGE_SIZE PAGESIZE Change-Id: I195b303fc88a7c848ca4e55fd6ba893796df55cc Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-on: http://openocd.zylin.com/5180 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-13Add TCK padding in the OSCAN1 reset/online/activate sequence. (#406)Greg Savin1-0/+14
2019-09-11Display IDCODE in message about it not existing. (#404)Tim Newsome1-1/+1
Change-Id: I1d1ca10ec62502c4757b64122e190ff964616684
2019-09-09Fix flashing HiFive Unleashed (#402)Tim Newsome6-31/+61
* Align algorithm stack to XLEN. This fixes algorithm timeout on RV64 targets. Also improve debug information in various places. Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d * Compile 32-bit RISC-V algorithms for RV32E. Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa * Remove debug code. Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b * Dump start of gdb packets escaping non-printable. Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915 * Propagate flash programming errors. Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7 * Improve debug messaging. Change-Id: I47ac3518f3b241986c677824864102936100adf6 * Add debug output to flash image. This is helpful when you're debugging the flash algorithm itself, and a nop when running it through OpenOCD. Change-Id: Id44c6498c288872cc2cec79044116ac38198c572 * Make timeout depend on how much data is written. Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e * Fix issi erase commands. This is required to flash HiFive Unleashed. Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10 * Fix running algorithm on multicore `-rtos riscv`. The bug was that poll() might change the currently selected hart, and in that case we'd access registers on that other hart after the algorithm is finished. Change-Id: I140431898285cf471b372139cef2378ab4879377 * Make fespi flash algorithm debugging optional. Also add a scheme that allows you to see the stack trace of where a failure occurred if debugging is enabled. Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-09-08flash/nor/stm32h7x: remove unused 'pages_per_sector' from stm32h7x_part_infoTarek BOCHKATI1-1/+0
Change-Id: I1b79c25cada574e3a9849f506443c836bd707604 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5289 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-09-08flash/nor/stm32h7x: remove flash size information from device nameTarek BOCHKATI1-1/+1
There is no sense in displaying the max size (2M) as there is variants of this device with reduced flash size Change-Id: I40574064d75fdf2a038044c81038a6d7abc6c4dd Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5288 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-09-08flash/nor: flash driver for Synwit SWM050 MCUsCaleb Szalacinski3-0/+214
SWM050 is a series of MCU product by Foshan Synwit Tech, which is available in TSSOP-8 or SSOP-16 packages. Adds flash driver for the internal 8KiB flash of the MCU. The registers are based on reverse engineering the J-Flash blob provided by the vendor. Also adds a pre-made cfg file. Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Caleb Szalacinski <contact@skiboy.net> Reviewed-on: http://openocd.zylin.com/4927 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08target/dsp563xx: dsp563xx restore reg supportHan Hartgers1-0/+1
Added "exist=true" field to the reg_list struct to make access to the dsp563xx registers again possible. Without it defaults to exist=false and all the reg related functions will return nothing. Fixes regression from b5964191f0d2fc3ace607af001df3d57cbfbaf2b Change-Id: I9c256346735b8d66919c4ba83f528a8afca46ff9 Signed-off-by: Han Hartgers <han.hartgers@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5239 Tested-by: jenkins
2019-09-08src/flash/nand: Fix some operator precedence bugs.Seth LaForge2-2/+2
Fix two expressions where precedence of operator | vs ?: was clearly confused. Untested - was clearly not expressing the intent of the author by inspection. Found by automated tooling and rtrieu@google.com. Change-Id: I46f190154797f8affc761caf3a15a1a9db53d702 Signed-off-by: Seth LaForge <sethml@google.com> Reviewed-on: http://openocd.zylin.com/5281 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-07Update jep106.inc by running the script. (#400)Tim Newsome1-240/+491
Script was actually run by Ken Pettit, so he can get IQ-Analog in there. Change-Id: If0db2f624f2081a92749e39832f9000b74ef8844
2019-08-28Revert part of da12994 to fix ^C being eaten. (#397)Tim Newsome1-0/+4
I had thought this was purely debug code but it apparently has a real effect. Change-Id: Id3fcb014b57575d46ab8e0b3262a9a7ab1bdb7f3
2019-08-28gdb_server, rtos: Fine-grained RTOS register accessTim Newsome8-47/+155
1. Add get_thread_reg() to rtos. It's used in rtos_get_gdb_reg() to read the value of a single register, instead of reading all register values by calling get_thread_reg_list(). 2. Add set_reg() to rtos. gdb_server uses this to change a single register value for a specific thread. 3. Add target_get_gdb_reg_list_noread() so it's possible for gdb to get a list of registers without attempting to read their contents. The clang static checker doesn't find any new problems with this change. Change-Id: I77f792d1238cb015b91527ca8cb99593ccc8870e Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/5114 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-08-26Use only one hart to run algorithm. (#396)Tim Newsome2-11/+19
* Clear cmderr by writing all ones. This should have been part of #389. Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0 * Don't update reg cache in register_write_direct(). This function explicitly bypasses any caches. Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9 * Use only one hart to run algorithm. Fixes a bug with `-rtos hwthread` where all harts would run when running a flash/CRC algorithm, which would probably ruin flashing, and was unexpectedly changing registers on other harts for the CRC algorithm. Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
2019-08-19Adds support for RISCV Access Memory Abstract Commands (#394)dave-estes-syzexion1-6/+192
* Adds support for RISCV Access Memory Abstract Commands The Access Memory Abstract Command is one of the three optional methods for reading and writing memory on a complient RISCV debug module. The previous two options were already implemented in OpenOCD. Implementation Notes: - aamvirtual is hard-coded to false until the design for accessing virtual addresses is finalized. - aamsizes corresponding to 8b, 16b, 32b, and 64b are supported. 128b support is postponed until it is required, as it will mean changes to the read/write_abstract_arg() interface to pass 128b values. - aampostincrement is not used and hard-coded to false. * Changes from review. * Additional lint fixes and a typo from last commit. * Fixing a clang error. * Fixes a last-minute change that broke writes with width > 8b. * Removing memcpy after adding read_from_buf().
2019-08-14Don't fake step for hwthread rtos. (#393)Tim Newsome4-11/+26
Fake step is a hack introduced to make things work with real RTOSs that have a concept of a current thread. The hwthread rtos always has access to all threads, so doesn't need it. This fixes a bug when running my MulticoreRegTest against HiFive Unleashed where OpenOCD would return the registers of the wrong thread after gdb stepped a hart. Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
2019-08-04flash/nor/core: fix some minor typoTarek BOCHKATI1-5/+5
Change-Id: I03832b3e4a6eaadfd87729a3a898e0a2cd30931a Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5264 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-07-28mflash: Remove this broken flash driverAndreas Fritiofson4-1746/+1
This is causing repeated build failures. Its design is so fundamentally broken that if someone actually wants to use it, a full rewrite is the only option. So it's not even worth deprecating in the hope that someone will notice and fix it, just get rid of it. Change-Id: I513069919a3873bd69253110f7fb6f622ee7d061 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/5243 Tested-by: jenkins Reviewed-by: Jeffrey Booher-Kaeding <Jeff.Booher-Kaeding@arm.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-07-26Properly detect errors in SBA reads. (#392)Tim Newsome1-19/+26
Also don't set/clear sbreadondata when only reading one word. Change-Id: Ia81834014895f1f4b552312ad0b60b3d3967a2c7
2019-07-18Access memory through the scope of current privilege level (#386)Nils Wistoff6-0/+137
* add opcode for csrrsi and csrrci * enable MMU while reading/writing memory using progbuf * fix style issues * keep old behavior for progbufsize<4, perform r/w/csr only when necessary * do not pass progbufsize, only write mstatus if changed * add config option to enable virtualization feature * throw error if virt enabled but unavaliable, outsource modify_privilege * support virtualization for read_memory_progbuf_one
2019-07-15Optimize reading a single byte/short/word. (#390)Tim Newsome1-4/+61
gdb has developed a nasty habit of very often reading 30-some half-words. This change speeds that up significantly. Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
2019-07-15Write all ones to clear cmderr. (#389)Tim Newsome1-1/+1
Change-Id: Ia76e749ed9f5a5f3509f253eeb69d1208bcfc929
2019-07-15Make resume order configurable. (#388)Tim Newsome1-7/+58
* Make resume order configurable. This is a customer requirement. Using this option is discouraged. Change-Id: I520ec19cc23d7837cb8576f69dadf2b922fa2628 * Fix style. Change-Id: If8e515984c92ce8df52aa69e87abde023897409f * Make mingw32-gcc happy. Change-Id: I39852aedec293294b2b2638ab2cc45494fe77beb
2019-07-09Redo fespi flash algorithm (#384)Tim Newsome2-308/+184
* WIP, rewrite of flash algorithm. Just put all the flashing logic into the algorithm, instead of using an intermediate format. This should reduce total data written while flashing by about 9%, and also makes the code much simpler. Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79 * New algorithm works. Speeds up Arty flashing another 9%. wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s) verified 2192012 bytes in 6.693336s (319.816 KiB/s) 8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4 * Fix whitespace. Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b * Don't reserve so much stack space. Also properly check XLEN in riscv_wrapper.S. Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6
2019-07-08RV32E support (#387)Tim Newsome2-12/+31
* In theory support RV32E. Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee * In theory support RV32E. At least very basic tests pass. Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355 * Fix cut and paste bug. Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6 * Add hacks to make RV32E work with gdb. gdb currently requires all 32 GPRs to be present, even on RV32E targets. Once gdb is fixed these hacks can be removed. Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
2019-06-21Reduce abstract command execution by one scan. (#383)Tim Newsome1-37/+40
Speeds up Arty flashing another 7%. ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 96.997032s (22.434 KiB/s) verified 2192012 bytes in 6.642059s (322.285 KiB/s) 11.86user 12.75system 1:44.13elapsed 23%CPU (0avgtext+0avgdata 18684maxresident)k ``` Change-Id: If609ce3de1726332f420d131e9fa6e04a5d974a1
2019-06-20cortex_m: set C_DEBUGEN in soft_reset_haltAntonio Borneo1-0/+5
The command "soft_reset_halt" is deprecated since mid 2013 with the commit 146dfe32956d ("cortex_m: deprecate soft_reset_halt"). Nevertheless it is still extremely useful with multicore chips where it allows to reset only one of the cores, option not available through asserting the chip-wide srst. Without a better replacement of the command, it's worth fixing it. Accordingly to ARM DDI 0403E.d, chapter C1.4.1 "Entering Debug state on leaving reset state", to halt the core at reset both bits DHCSR.C_DEBUGEN and DEMCR.VC_CORERESET must be set. Current code only sets the latter bit, relying on having C_DEBUGEN already set through other commands, e.g. "halt". This prevents the command "soft_reset_halt" to work if issued as very first command. Set the bit C_DEBUGEN in command "soft_reset_halt". Change-Id: I66bfd6a0da1fca5049dea037b4d258cf6f842966 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4987 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20helper/options: simplify the code using command_run_linef()Antonio Borneo1-8/+3
Thanks to command_run_linef() there is no need to pre-build the command using alloc_printf(). Change-Id: Iccfebd6063d1ac162f090fe2309b1f51bebf0214 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5226 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20helper/command: make command_run_line reentrantChristopher Head1-0/+6
The `command_run_line` function contains a comment saying it should be reentrant. However, it isn’t: it NULLs out `current_target_override` and doesn’t restore it before returning, and it changes the `context` associated data of the `interp` object and then deletes that associated data before returning rather than restoring it to its previous value. Change-Id: I84fd46ef7173f08cf7c57b9a5b76e4986a60816f Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5223 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20fix memory leak (#382)jhjung811-0/+1
2019-06-19Improve block read and checksum speed (#381)Tim Newsome6-17/+117
* Cache program buffer writes. Speeds up flash program by 3%, flash verify by 2%. Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a * Remove nop from batch reads. program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287 KiB/s, verify @ 23.148 KiB/s originally). Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935 * Use "algorithm" to compute CRC on RISC-V targets. Use the C compiler to generate the algorithm code. It's better at assembly than I am. We need separate RV32 and RV64 binaries to handle shift instructions. I used the code from gdb (libiberty really) because it returns the correct result. I'm not sure if the table is worth it since we do have to save/download/restore more bytes now. riscv_run_algorithm() now properly saves and reads back all registers used for parameters. It also doesn't check final_pc if exit_point is 0. Using gdb means I don't know the exact address where the code will end. Small target.[ch] change to be able to run algorithms at 64-bit addresses. Flashing an arty board now: ``` wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s) verified 2192012 bytes in 7.037476s (304.177 KiB/s) 9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k ``` Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190 * Clean up formatting. Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
2019-06-19target/cortex_m: Add support for AHB5-APMarc Schink1-1/+10
The AHB5-AP is implemented in Cortex-M23/33 based devices. Change-Id: I505954a2e2c6462ce0aa96eba1d55b016c5028b9 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5232 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2019-06-19target/arm_adiv5: Add type for AHB5-APMarc Schink3-6/+12
This access port type comes with the AMBA 5 protocol specification, see 'C1.3 AP' in ARM IHI 0031D. Change-Id: I3c4f0a69230daaf4f5f979de6213fe3c025a089a Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5231 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2019-06-19Support for debugging on ARMv8-M CPUsOmair Javaid2-15/+62
This patch adds ARMv8-M CPUs detection logic in ARMv7m target specific code. Also adds a slightly different watchpoint manipulation logic for ARMv8-M. This is based on ARMv8-M architecture reference manual. Tested on ARM Musca A board. Change-Id: I0652560954ef02c378a7067fab586edf39d3e9cc Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4997 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-14Set mstatus.FS to access FPU CSRs. (#380)Tim Newsome1-3/+12
This improves behavior when executing function calls from mainline gdb. Change-Id: Ia37507a16cd76fc03d26457e84fd68402969c534
2019-06-14target/cortex_a: remove dependency from jtag queueAntonio Borneo1-2/+3
Replace jtag specific API jtag_add_reset() with transport independent API adapter_{de}assert_reset(). Change-Id: I1b917a4c1205115c4e0315373d81a9305e931258 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4944 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-14target/aarch64: remove dependency from jtag queueAntonio Borneo1-2/+3
Replace jtag specific API jtag_add_reset() with transport independent API adapter_{de}assert_reset(). Change-Id: I32c43e2e47366363521fa3f387de9e2fb1c20852 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4943 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-13jtag: fix error on TCL command "return" in jtag event handlerAntonio Borneo1-1/+6
The TCL command "return" always returns error code JIM_RETURN, to indicate that the effective error code and message are elsewhere. In the current implementation, the caller of jtag's event only checks for return code JIM_OK and considers any other value, including JIM_RETURN, as an error condition. It can be tested running openocd on a jtag target and adding a jtag event "setup" with a single line "return", e.g. openocd -f board/ti_cc3200_launchxl.cfg \ -c 'jtag configure cc32xx.cpu -event setup return' to get the message: ../src/jtag/core.c:1599: Error: in procedure 'jtag_init' called at file "../src/jtag/core.c", line 1599 Modify jtag_tap_handle_event() to detect the specific return value of the "return" command and to test the real error code that is, eventually, specified to the TCL "return" command. Change-Id: I6d6febc15ef169638afffbffc1810e0b84fcf5c8 Reported-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5199 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13target: fix error on TCL command "return" in target event handlerAntonio Borneo1-1/+6
The TCL command "return" always returns error code JIM_RETURN, to indicate that the effective error code and message are elsewhere. In the current implementation, the caller of target's event only checks for return code JIM_OK and considers any other value, including JIM_RETURN, as an error condition, thus dumping the call-trace. The execution is not stopped because the error is not further propagated, but the error message is annoying and misleading. It can be tested running openocd -f ./test.cfg using the following script "test.cfg". You can replace the board file in line 1, to use a board available in your lab: 1 source [find board/st_nucleo_f4.cfg] 2 [target current] configure -event reset-start {} 3 [target current] configure -event reset-end {return} 4 init 5 proc a {} {[target current] invoke-event reset-start} 6 proc b {} {[target current] invoke-event reset-end} 7 proc c {} {a;b;echo "arrived at the end"} 8 c 9 shutdown The execution produces: ./test.cfg:7: Error: in procedure 'c' called at file "./test.cfg", line 8 in procedure 'b' called at file "./test.cfg", line 7 arrived at the end that shows the call-trace but does not halt the execution. The developer can avoid using the "return" command in the event body by defining a TCL procedure that implements the handler and that contains the "return" command, reducing the handler body to a simple call to the procedure above. But this approach is either not documented nor always intuitive while writing the handler, causing waste of time to look for the false error. Modify target_handle_event() to detect the specific return value of the "return" command and to test the real error code that is, eventually, specified to the TCL "return" command. Change-Id: I2b860bab7233c6ed13ee4098e348d7533e1c4626 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4974 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13flash/stm32h7x: fix register names to comply with RM0399 Rev2 and RM0433 Rev6Tarek BOCHKATI1-13/+13
Change-Id: I085d86a2a47f4aeef93a99238e3b80ee294d46df Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5192 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13jtag: drivers: buspirate: chunk SWD switch sequence transfer.Tilman Sauerbeck1-8/+17
Commit c2e18bfaeafd changed the size of the JTAG-to-SWD sequence from 15 bytes to 17 bytes. This broke SWD switch sequence transfer for buspirate, since buspirate packets can only hold a payload of up to 16 bytes and we tried to fit the whole sequence in a single packet. Splitting up the sequence transfer in appropriately sized packets makes buspirate SWD work again (successfully tested with buspirate firmwares v6.1 and v7.0). Change-Id: Ib5b412b9e77287d705d2762e31c16d30318b50e3 Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de> Reviewed-on: http://openocd.zylin.com/5200 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-13jtag/drivers/jtag_usb_common: fix typoChristopher Head1-6/+6
Change-Id: If1f56fd5d610b993a4ecbc900fac9f90638037c9 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5202 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-12target: make target re-configuration possible againTomas Vanek1-1/+7
Before commit 877cec20dca6e78f9f029f0f173879cda101a6c2 ("command: check command mode for native jim commands") all the jim commands were erroneously treated as they had mode COMMAND_ANY. The command '$_TARGET configure -xxx' was therefore applicable on running OpenOCD to change the target configuration. It is handy e.g. for changing an event handler or changes of the work area. Change 'configure' command .mode to COMMAND_ANY to make it possible again. The only parameter which cannot be re-configured after init is -gdb-port. Test the command mode and refuse setting of gdb port after init. Change-Id: I88493ac10a46647dc52a88fbc9f8ce6b5ba3bcd0 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5214 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-12fix XScale register accessMichael Schwingen1-0/+1
since b5964191f0, all XScale-specific registers were missing, breaking config scripts. Change-Id: Ia56f3ca17500ba54bd08f417e9a5aaaa8a1be8c4 Signed-off-by: Michael Schwingen <spam-openocd@discworld.dascon.de> Reviewed-on: http://openocd.zylin.com/5136 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
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