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2017-02-10aarch64: remove unused struct componentsMatthias Welwarsky1-5/+0
remove unused register index array from armv8_mode_data[] Change-Id: I686c20eeb3da413f5e9ef6058e31ce939741afb4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: improve debug outputMatthias Welwarsky2-9/+9
Make debug and error messages more informative, fix spelling and formatting errors Change-Id: I7245f42c5153bcc95676270814d30e91c113aaed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: enlarge value buffer of arm_reg to store 64 bitMatthias Welwarsky2-2/+2
struct arm_reg::value[] must be 8 byte to hold a 64bit register value. Change-Id: If253e90731d0ee855eafd9d7b63b91f84630cc7c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: consolidate sticky error handlingMatthias Welwarsky2-31/+7
Move clearing of DSCR "Sticky Error" condition to the exception handling function. Clear once on entering debug state. Change-Id: Iec1d09d6f2d9cdd7e92953da5ea19f3e399ca12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: discard async aborts on entering debug stateMatthias Welwarsky4-2/+17
recommended for Corte-A8 cores, not sure if necessary for ARMv8 based cores as well. Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: cleanup context restoreMatthias Welwarsky1-12/+3
Remove register cache invalidation and target state changes that are handled appropriately in other functions. Change-Id: Ic903f41ddc267f4b8765ea022bd4d6da1017e21f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: enable aarch32 debugging with arm gdbMatthias Welwarsky2-27/+164
When a PE is in Aarch32 state and gdb asks for a target description, provide a register view compatible with the "org.gnu.gdb.arm.core" feature. Only current-mode registers are exported, banked registers are not visible. Change-Id: I99a85d94831cf597fe8cff6a0a1818ce0a33613b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: allow reading TTBR register when halted in EL0Matthias Welwarsky1-0/+3
There's no access to TTBR in EL0. Circumvent by moving the PE to EL1 before reading, and switch back to original mode afterwards. Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: make sure to enable HDE for all SMP PEs to be haltedMatthias Welwarsky1-28/+27
When halting a group of PEs through CTI, HDE must be set in EDSCR for all of them. Change-Id: Iaa4bc0b0fe31e46a463c709d8274023225affd85 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: handle exceptions taken in debug stateMatthias Welwarsky3-0/+60
When an armv8-a PE causes an exception while halted, e.g. by performing a prohibited memory or register access, its state is affected in the same way as if it was running. That means, a number of registers is overwritten (notably DLR and DSPSR, but also others) and also potentially the exception level and therefore also the PE state can change. This state must be restored before resuming normal operation. This is done by marking the relevant cached registers "dirty" so that they are written back before resume. Change-Id: I9b6967a62d7cb23a477a9f7839f8d2b7087eed09 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: cache identification for aarch32 stateMatthias Welwarsky3-6/+14
Use proper T32 opcodes for cache identification when the PE is in Aarch32 state Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix mode switchingMatthias Welwarsky6-51/+119
DCPS only allows to enter higher ELs, for lower ELs you need to use DRPS. Also, of course the encoding differs between A64 and T32. Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be restored on resume. Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: register access rewriteMatthias Welwarsky8-366/+580
All register access is now performed through common read/write functions, which delegate the actual register access to the armv8_common object. armv8_common contains function pointers to direct read and write requests to the respective low-level functions for each PE state. The respective read/write functions are selected on debug state entry. At the same time, T32 opcodes are now formatted for ITR in dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global visibility. Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: simplify armv8_read_ttbcrMatthias Welwarsky1-50/+47
Read registers based on current EL instead of PE mode. Change-Id: I05d3219ac1bf8585e9f4f024a7e8599fea0913b6 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: allow reading system control register when halted in EL0Matthias Welwarsky1-1/+10
There's no access to system control register in EL0. Circumvent by moving the PE to EL1 before reading, and switch back to original mode afterwards. Change-Id: I309f4eea5597ffc88fc892e9bbb826982e8a44ec Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: simplify armv8_set_cpsr()Matthias Welwarsky1-29/+3
Translate from cpsr value to "enum arm_mode" by shifting up 4 bits and filling the lowest nibble with 0xF. Change-Id: Ic32186104b0c29578c4f6f99e04840ab88a0017b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: provide virt2phys commandMatthias Welwarsky4-2/+89
Use AT commands to translate virtual to physical addresses based on current MMU configuration. Change-Id: I1bbd7d674c435541b617b17022fa9f7f0f01bdab Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: slightly simplify breakpoint set functionMatthias Welwarsky1-6/+1
Set HDE bit through helper function instead of manual mem_ap access. Change-Id: I68c157870f3f3c47a875d425ade6e975d8075424 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove bogus os_border calculationMatthias Welwarsky2-36/+5
The artificial "os_border" doesn't exist in aarch64 state and is wrong for aarch32 state as well. Remove it. Change-Id: I7c673a1404b03aa78dbd505e115fa3a93f7ca05f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: armv8 cache functions updateMatthias Welwarsky5-271/+353
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: refactor armv8 dpmMatthias Welwarsky2-510/+440
Move all DPM related functions from aarch64.c to armv8_dpm.c. Change-Id: I43404ff5db414ae898787a523d3219e5bee44889 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky7-83/+406
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: update smp halt and resume to better facilitate CTIMatthias Welwarsky2-73/+82
Set up CTI so that halt and resume requests get routed to all PEs in the SMP group. Change-Id: Ie92cfd3fe54632e5fdc049a6bf5b24b99451a8c9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling when setting/deleting soft breakpointsMatthias Welwarsky1-0/+29
Flush D-Cache before, flush D-Cache and invalidate I-Cache after modifying the breakpoint location. Change-Id: Id2e2f4f2545c062de7e27275f66857357496d4ae Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling functionsMatthias Welwarsky4-1/+153
For now only D-Cache flush (Clean&Invalidate) and I-Cache invalidate are implemented. That's enough for software breakpoints. Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: disable interrupts when stepping [WIP]Matthias Welwarsky1-0/+32
On live hardware, interrupts will happen while the core is held for stepping. The next step will most of the time execute an interrupt service instead of the next line of code, which is not what you expect. Disable interrupts through DSCR before resuming for a step, and re-enable them again after the step happened. This should be made configurable, like on cortex_a target. Change-Id: I94d8ffb58cf7579dedb66bc756b7eb6828b6e8e4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct instruction for software breakpointsMatthias Welwarsky3-3/+6
External debuggers need to use HLT, not BRK. HLT generates a halting debug event while BRK generates a debug exception for self-hosted debugging. Change-Id: I24024b83668107f73a14cc75d951134917269e5c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: report the correct reason for halting after singlestepMatthias Welwarsky2-13/+14
Don't report breakpoint as debug reason when halt is due to a single-step event. Change-Id: Ie6c3ca1e5427c73eb726a038301b6a29a47d1217 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix register listMatthias Welwarsky1-33/+33
According to gdb documentation, a register "cpsr" is expected if aarch64 features are announced. Also, the value buffer must be capable of holding a 64bit value (8 byte, not 4) Change-Id: I7aec4e84fa87eadb26797acd0d16c988b9852616 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix duplication of register cacheMatthias Welwarsky1-3/+5
Change-Id: Ib4422e39171f19eea3f0b5a86f9dccdbb7044265 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove code for AHB-AP supportMatthias Welwarsky3-181/+31
Reduce complexity of memory access functions, anyway there are no ARMv8 platforms that actually contain an AHB-AP at all. while at it, fix virt-to-phys function signatures to expect target_addr_t. Change-Id: I55a369686f42993988b6323e5a77f38de12530a9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix stepping from addressMatthias Welwarsky1-1/+1
The step command optionally carries a resume address. In this case, stepping should start not at the current PC, but at the given address. Change-Id: Id5792a3745f470cf29efa90c63d65f33d36f6b25 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove references to armv7-rMatthias Welwarsky2-19/+9
aarch64 target doesn't support the -r profile anyway. Change-Id: Iaa470ed9f95ea495ab1bafdf401f55a1ebcefddf Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix armv8_set_core_reg when destination is cpsrMatthias Welwarsky1-2/+8
When armv8_set_core_reg is used to set the value of the CPSR, also update the internal architecture state. Change-Id: I5f6a2be6fde8d91ec3352d8ba23c4aa90eb02977 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: unify armv7-a and armv8 debug entry decodingMatthias Welwarsky4-33/+21
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct A64 instructions for cache handlingMatthias Welwarsky2-11/+10
Replace A32 MCR with proper A64 MSR opcodes Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix first examinationMatthias Welwarsky1-51/+42
properly decode debug capabilities, remove superfluous register accesses. Change-Id: I2cca699b515262dd2a508d7be97826eb17b9c607 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: correct display for aarch64 stateMatthias Welwarsky1-11/+29
Aarch64 state has different PSTATE and exception level model. Correct the printout e.g. in poll command. Change-Id: I1820fd1836c7076ae0aa405fa335fd1a14a2e5b3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic constant for register countMatthias Welwarsky1-4/+3
Aarch64 has 34 registers, but use ARMV8_LAST_REG instead of raw integer constant. Change-Id: I86481899ade74f27fc90eff9f367d444c03e535e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove armv7-a virt-to-phys codeMatthias Welwarsky3-93/+27
Page table layout in aarch64 is very different from armv7-a layout. Remove the incorrect handling, to be replaced correct armv8 code in a later patch Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: clear breakpoint value register on removalMatthias Welwarsky1-0/+27
Not only null control but also value of the breakpoint when it is removed. Change-Id: Id99c7e3644729c64e563f1fa8b0577f350be6a98 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: correct breakpoint register offsetMatthias Welwarsky1-7/+4
armv8 breakpoint register spacing is 16, not 4 as in armv7-a Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix cache identificationMatthias Welwarsky2-28/+18
Use correct instructions to access CLIDR, CSSELR and CCSIDR. Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of translation table registersMatthias Welwarsky2-11/+100
Correctly access and parse aarch64 ttbcr. Change-Id: I1b1652791a6b5200f58033925286292d838e8410 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix entry into debug stateMatthias Welwarsky2-20/+16
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this bit are ignored but we should not do them anyway - use dpmv8 function to report the reason for debug entry - WFAR is a 64bit register Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic opcodes instead of hex valuesMatthias Welwarsky1-7/+6
Use opcode definitions from armv8_opcodes.h where appropriate Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix accesses to SCTLR_ELn registerMatthias Welwarsky1-27/+142
The system control register has several instances, depending on the exception level. Make sure to access always access the correct one. Change-Id: I9e867f4dbd9625762042f20ed905064ea4e3270f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix error recovery in aarch64_dpm_prepareMatthias Welwarsky1-4/+8
Flush DTRRX with a dummy read if it's full, clear sticky errors by writing CSE bit to EDRCR register. Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: formalize use of CTI in halt and resumeMatthias Welwarsky2-57/+68
Use configured CTI base address instead of hardcoded value, if available. Use symbolic constants instead of raw hex offsets. Trim halt and resume code to what is actually necessary. Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix context and hybrid hardware breakpointsMatthias Welwarsky1-10/+17
Fix 64bit address setting Fix register spacing (16 instead of 4) Set HMC bit for all but linked context match breakpoints, where the bit is ignored anyway Change-Id: I48428f39154a6fe5fadc075ca918d1500a0bb241 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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