riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-04-04	riscv: Correct the autoexec in read_mem	Megan Wachs	1	-4/+13
2017-03-30	riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.	Megan Wachs	1	-9/+5
2017-03-23	Revert "(WIP) Force algorithms to 64 bit"	Palmer Dabbelt	1	-2/+2
2017-03-23	(WIP) Force algorithms to 64 bit	Palmer Dabbelt	1	-2/+2
2017-03-23	some device	Palmer Dabbelt	1	-0/+1
2017-03-23	Don't set abstractauto at the start	Palmer Dabbelt	1	-1/+2
2017-03-22	riscv: Retry failed memory reads	Megan Wachs	1	-65/+75
2017-03-21	riscv: add missing variable declaration.	Megan Wachs	1	-0/+1
2017-03-21	Clear autoexec correctly	Palmer Dabbelt	1	-1/+1
2017-03-21	Wrong autoexec	Palmer Dabbelt	1	-2/+2
2017-03-21	Builds	Palmer Dabbelt	2	-425/+533
2017-03-15	riscv-v13: wait for idle in read_memory	Megan Wachs	1	-3/+10
2017-02-27	Remove more cruft.	Tim Newsome	1	-35/+1
2017-02-27	riscv: Ensure that hart is halted before attempting to examine it.	Megan Wachs	1	-2/+4
2017-02-25	Remove cruft.	Tim Newsome	1	-47/+11
2017-02-25	Use DCSR constants from the debug spec.	Tim Newsome	1	-170/+21
2017-02-25	Update bits to latest spec.	Tim Newsome	2	-587/+591
2017-02-22	Speed things up by ignoring return values.	Tim Newsome	1	-13/+45
2017-02-21	Optimize memory write code, used in download.	Tim Newsome	1	-92/+216
2017-02-20	Better error checking in memory access.	Tim Newsome	1	-4/+8
2017-02-20	Properly restore s0 and s1 on resume.	Tim Newsome	1	-8/+8
2017-02-17	Fix access FPU registers again.	Tim Newsome	1	-46/+80
2017-02-17	Fix use of REG vs CSR constants.	Tim Newsome	1	-26/+30
2017-02-17	Bunch of register access refactoring.	Tim Newsome	2	-546/+161
2017-02-16	Check busy before triggering another command.	Tim Newsome	1	-46/+50
2017-02-15	Check for errors after read/write.	Tim Newsome	1	-4/+12
2017-02-15	Fix double read, which might have side effects.	Tim Newsome	1	-4/+6
2017-02-15	Make MemTest32 pass.	Tim Newsome	1	-2/+2
2017-02-15	Some memory access works.	Tim Newsome	2	-351/+161
2017-02-14	Merge pull request #15 from sifive/get_set_reg_error	Tim Newsome	2	-9/+45
2017-02-14	Make general CSR reads work.	Tim Newsome	1	-36/+22
2017-02-14	Make it all the way through examine().	Tim Newsome	1	-220/+85
2017-02-14	More dbus->dmi.	Tim Newsome	1	-21/+65
2017-02-13	Read misa during examine(), using program buffer.	Tim Newsome	2	-100/+939
2017-02-13	dbus -> dmi	Tim Newsome	2	-160/+160
2017-02-13	Discover XLEN using abstract reg reads.	Tim Newsome	2	-42/+64
2017-02-10	Attempt to discover XLEN with abstract reg reads	Tim Newsome	4	-108/+118
2017-02-10	riscv: Add register name to message when they do not exist.	Megan Wachs	2	-7/+7
2017-02-10	Halt target in riscv_examine().	Tim Newsome	2	-30/+45
2017-02-09	Add debug_defines.h.	Tim Newsome	1	-0/+630
2017-02-08	Detect and smoketest data and ibuf registers.	Tim Newsome	1	-28/+69
2017-02-08	Correctly parse dmcontrol.	Tim Newsome	1	-51/+29
2017-02-07	Update DMI bus width for 0.13.	Tim Newsome	2	-10/+2
2017-02-07	Merge remote-tracking branch 'origin/riscv' into HEAD	Megan Wachs	7	-2297/+6016
2017-02-05	Add missing header file.	Tim Newsome	1	-0/+62
2017-02-05	Use the set/reg register error return code when registers don't exist.	Megan Wachs	2	-9/+45
2017-02-05	Add the first difference for 0.13 targets.	Tim Newsome	1	-1/+1
2017-02-05	Use the csrNNN name instead of "mstatus".	Tim Newsome	1	-2/+6
2017-02-05	Most gdbserver tests pass now.	Tim Newsome	5	-2296/+5308
2017-01-25	riscv: disable interrupts for all priviledge levels	Megan Wachs	1	-3/+2