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2018-01-22Fix 2 more bitbang drivers.rbb_cleanupTim Newsome2-10/+17
Change-Id: Ib7257d1d113871a9f57ba3b899cb029bb595035a
2018-01-22Update parport to return errors.Tim Newsome1-10/+20
Change-Id: I6c6bf75809cd3222c7680e10ac6ee6073050ed07
2018-01-22Propagate errors from remote_bitbang; don't exit()Tim Newsome3-92/+146
Change requested by Paul Fertser at http://openocd.zylin.com/#/c/4312/4/src/jtag/drivers/remote_bitbang.c Change-Id: I44d97bd1198821d2e8afdc7a237ed3c3825cd319 Signed-off-by: Tim Newsome <tim@sifive.com>
2018-01-22Format comments to be doxygen style.Tim Newsome1-13/+12
Change-Id: I7a757b92926b9cd65846551893f78ffb5e462370
2018-01-22fdopen() for writing and reading.Tim Newsome1-1/+1
Since that's what we're doing. Doesn't seem like this affected anything, though. Change-Id: I0fa915fe2a311d4b3e6e72a9a9a19f52018258c3
2018-01-19Incorporate review feedback from OpenOCD teamTim Newsome1-17/+9
Remove unused file handle, and rename the only remaining one to make more sense. Close file descriptor if initialization fails. Change-Id: I383567aaadb1aa59d86f814eba8bc65f24e91928
2018-01-15Remove dead code.Tim Newsome1-9/+0
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-10Merge pull request #172 from riscv/dbus_read_commentMegan Wachs1-1/+6
Add a comment in dbus_read
2018-01-10Merge pull request #178 from riscv/cleanupTim Newsome1-2/+2
Rename dummy variable to be correct.
2018-01-09Muck with mstatus to always be able to read FPRsTim Newsome1-1/+13
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-08Propagate register read errors.Tim Newsome6-62/+115
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-05Merge pull request #179 from riscv/multicore_hart_selectionTim Newsome1-4/+12
Select current hart before reading memory.
2018-01-05Merge pull request #173 from riscv/warn_namesTim Newsome2-6/+5
Use register names instead of numbers in warnings
2018-01-05Rename dummy variable to be correct.Tim Newsome1-2/+2
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-04Select current hart before reading memory.Tim Newsome1-4/+12
This avoids trying to read memory from the wrong hart, if the current hart was changed by an earlier call (eg. to poll()). Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04Make delay update messages debug instead of info.Tim Newsome2-4/+4
They confuse users otherwise. Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04Add a comment in dbus_readMegan Wachs1-1/+6
This just comments the current behavior
2018-01-04Use register names instead of numbers in warningsTim Newsome2-6/+5
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-02Parse 64-bit CRC addrs even on 32-bit hostsTim Newsome1-1/+1
Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
2017-12-28Fix typo.Tim Newsome1-1/+1
Issue #164 Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
2017-12-27Get rid of abort() calls.Tim Newsome5-54/+77
Also changed a few asserts that could trigger due to broken hardware. Fixes Issue #142. Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-26Propagate error instead of calling abort().Tim Newsome3-34/+62
As part of this I improved the memory read/write fatal error handling a bit. Now at least we try to leave autoexec turned off, and will even restore the temp registers if the situation isn't too hosed for that. Partly addresses Issue #142 Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26Remove unused code.Tim Newsome2-18/+0
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26Conform to OpenOCD style guide.Tim Newsome15-733/+846
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-22Merge branch 'master' into updateTim Newsome54-791/+4228
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-21Fix flash/run algorithm with new register namesTim Newsome2-5/+8
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21Make functions static. Free memory.Tim Newsome1-10/+12
Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
2017-12-21Merge pull request #155 from riscv/debug_definesMegan Wachs1-22/+48
Update debug_defines to the one used with spike.
2017-12-21Merge pull request #148 from riscv/macbuildMegan Wachs1-1/+1
Use %ll instead of %L in scanf.
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21Merge pull request #145 from riscv/rbb_winTim Newsome2-2/+13
Fix Windows build
2017-12-21Use parens after if.Tim Newsome1-1/+1
I'm surprised this built with gcc before. Fixes Issue #150. Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-19Add `riscv expose_csrs` command.Tim Newsome1-0/+110
This lets users tell OpenOCD which non-standard CSRs exist on their target, that will also be accessible and whose existence will be communicated to gdb. Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19Hide supervisor registers if there is no S mode.Tim Newsome2-28/+32
Also update encoding.h. Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19Give FPRs ABI names.Tim Newsome2-2/+67
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19Remove some debug printfs.Tim Newsome1-2/+0
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19Avoid another assertion failure.Tim Newsome1-1/+5
Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19Read misa before using it to check for extensions.Tim Newsome1-1/+2
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19Don't rely on hart count until it's correct.Tim Newsome1-1/+1
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19Remove no-longer-true comment.Tim Newsome1-1/+0
Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19Simplify examine()Tim Newsome1-43/+13
Now we don't have to play tricks fooling other parts of our code that might assert. Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19Make priv register 8 bits.Tim Newsome1-0/+1
(It's really only 2 bits, but something wonky happens between gdb and OpenOCD if I make it that size.) Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19WIP xml register for 0.11.Tim Newsome4-392/+290
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of 0x40001105. Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19Hide unknown registers, which probably don't existTim Newsome2-13/+21
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19Fix register names.Tim Newsome5-46/+108
Use the ABI ones for every register that we have one for. Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19WIP better CSR names, and include only existingTim Newsome1-1/+32
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19WIP. Hide FPRs if the hart doesn't support F/D.Tim Newsome2-23/+31
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19`make all` debug tests now pass.Tim Newsome3-73/+106
Also properly support (I think) D extension on RV32. Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19Checkpoint that seems to work.Tim Newsome1-0/+30
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-15Use %ll instead of %L instead of scanf.macbuildTim Newsome1-1/+1
Mac build barfs on L, and the manpage says they're equivalent. Hopefully fixes #147 Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
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