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2017-12-21Merge pull request #155 from riscv/debug_definesMegan Wachs1-22/+48
2017-12-21Merge pull request #148 from riscv/macbuildMegan Wachs1-1/+1
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
2017-12-21Merge pull request #145 from riscv/rbb_winTim Newsome2-2/+13
2017-12-21Use parens after if.Tim Newsome1-1/+1
2017-12-19Add `riscv expose_csrs` command.Tim Newsome1-0/+110
2017-12-19Hide supervisor registers if there is no S mode.Tim Newsome2-28/+32
2017-12-19Give FPRs ABI names.Tim Newsome2-2/+67
2017-12-19Remove some debug printfs.Tim Newsome1-2/+0
2017-12-19Avoid another assertion failure.Tim Newsome1-1/+5
2017-12-19Read misa before using it to check for extensions.Tim Newsome1-1/+2
2017-12-19Don't rely on hart count until it's correct.Tim Newsome1-1/+1
2017-12-19Remove no-longer-true comment.Tim Newsome1-1/+0
2017-12-19Simplify examine()Tim Newsome1-43/+13
2017-12-19Make priv register 8 bits.Tim Newsome1-0/+1
2017-12-19WIP xml register for 0.11.Tim Newsome4-392/+290
2017-12-19Hide unknown registers, which probably don't existTim Newsome2-13/+21
2017-12-19Fix register names.Tim Newsome5-46/+108
2017-12-19WIP better CSR names, and include only existingTim Newsome1-1/+32
2017-12-19WIP. Hide FPRs if the hart doesn't support F/D.Tim Newsome2-23/+31
2017-12-19`make all` debug tests now pass.Tim Newsome3-73/+106
2017-12-19Checkpoint that seems to work.Tim Newsome1-0/+30
2017-12-15Use %ll instead of %L instead of scanf.macbuildTim Newsome1-1/+1
2017-12-14Fix cut and paste bug.Tim Newsome1-1/+1
2017-12-14Use abstraction because Windows is not POSIXTim Newsome2-2/+13
2017-12-11Fix build.Tim Newsome1-2/+2
2017-12-11Merge pull request #131 from riscv/small_progbufTim Newsome7-1018/+780
2017-11-27Update encoding.h.Tim Newsome2-58/+216
2017-11-16Add missing return.Tim Newsome1-0/+1
2017-11-14Merge pull request #127 from riscv/jtag_debugTim Newsome1-62/+10
2017-11-01Merge branch 'riscv' into small_progbufTim Newsome2-5/+1
2017-10-27Fix compile warning with new gcc.Tim Newsome1-1/+1
2017-10-27Support 64-bit FPRs on RV32.Tim Newsome3-34/+328
2017-10-25Remove unused variables.Tim Newsome1-4/+0
2017-10-24Remove more unused functionality.Tim Newsome1-6/+0
2017-10-24Add a fence after memory writes.Tim Newsome1-7/+16
2017-10-24Remove more unused code.Tim Newsome1-6/+0
2017-10-24Remove more unused code.Tim Newsome1-48/+6
2017-10-23Remove unused functionality.Tim Newsome2-268/+0
2017-10-23Properly fix memory read when encountering busy.Tim Newsome1-36/+101
2017-10-18Pay attention to impebreak.Tim Newsome4-64/+95
2017-10-18Remove unused functionality.Tim Newsome2-73/+3
2017-10-18Still restore registers if an access failed.Tim Newsome1-8/+11
2017-10-18Fix FPR access.Tim Newsome1-5/+8
2017-10-17Don't crash when encountering RV64.Tim Newsome1-7/+3
2017-10-17Memory read/write works if the core can keep up.Tim Newsome1-11/+8
2017-10-17MemTest64 passes.Tim Newsome2-4/+18
2017-10-16Memtest{16,32} pass.Tim Newsome4-217/+126
2017-10-13At least some memory writes work.Tim Newsome3-130/+94
2017-10-12Register read/write might be working.Tim Newsome2-72/+67
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