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2015-11-03target: tell which target state is meantOleksij Rempel1-1/+2
If we work on smp system, the output of step command will depend on Id of default target. This patch adds additional information to help find what on which core is happening. Example of LOG after this patch. imx6.cpu.1: target state: halted ^^^^^^^^^^ target halted in ARM state due to breakpoint, current mode: Supervisor cpsr: 0x60000093 pc: 0x80076c0c MMU: enabled, D-Cache: enabled, I-Cache: enabled imx6.cpu.0: target state: halted ^^^^^^^^^^ target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x20000193 pc: 0x802ccb6c MMU: enabled, D-Cache: enabled, I-Cache: enabled Change-Id: I536a2cce33b5ab10af9de2a43b9960320c17729f Signed-off-by: Oleksij Rempel <external.Oleksij.Rempel@de.bosch.com> Reviewed-on: http://openocd.zylin.com/2691 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-11-03cortex_m: dwt_num_comp should be set to zero in cortex_m_dwt_free()Tomas Vanek1-0/+1
A segmentation fault in cortex_m_endreset_event() is sometimes raised with very broken target like Kinetis Kx with erased flash and active WDOG. Debugging revealed that cortex_m->dwt_num_comp is 4 and dwt_list is NULL at cortex_m:290 Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2989 Reviewed-by: Thomas Schmid <thomas@rfranging.com> Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-03rtos/mqx: Fix uninitialized parts of symbol tabledaniel-k1-1/+1
Memory for the symbol table was allocated by malloc but not initialized other than with the symbol name. Therefore `address` and `optional` members were having arbitrary values leading to every symbol being optional most of the time which messes up RTOS auto-detection. Memory will now be zero-initialized as in other RTOS implementations. Change-Id: I6c6e31ec1ef7e043061adf8c695b2139620e005d Signed-off-by: Daniel Krebs <github@daniel-krebs.net> Reviewed-on: http://openocd.zylin.com/3017 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-03Change from sys/poll.h to standard poll.h locationPaul Fertser1-2/+2
According to "man 2 poll" the correct header to include is poll.h, not sys/poll.h. Reported by a build against musl. Change-Id: I5298b49dc947d1a368e423104c0c0c7b9bdd1a10 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2947 Tested-by: jenkins
2015-11-03flash/nor/stm32f2x: Add STM32F469 partMaxime Coquelin1-0/+2
Change-Id: I4e13ceb0ba954dc2fea059ddeef10109be938c9c Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Reviewed-on: http://openocd.zylin.com/3042 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-10-30rtos: handle STKALIGN adjustments on cortex mAndrew Ruder2-1/+53
In the case that the STKALIGN bit is set on Cortex M processors, on entry to an exception - the processor can store an additional 4 bytes of padding before regular stacking to achieve 8-byte alignment on exception entry. In the case that this padding is present, the processor will set bit (1 << 9) in the stacked xPSR register. Use the new calculate_process_stack callback to take into account the xPSR register and use it on the standard Cortex_M3 stacking. Note: Change #2301 had some misinformation regarding the padding. On Cortex-M the padding is stored BEFORE stacking so xPSR is always available at a fixed offset. Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed to a '1' such that this alignment always occurs on non-aligned stacks. Behavior of xPSR verified via the (bad-sorry) assembly program below by setting a breakpoint on the SVC_Handler symbol. The first time SVC_Handler is triggered the stack was 0x20000ff8, the second time SVC_Handler is triggered the stack was 0x20000ffc. Note that in both cases the interrupt handler gets 0x20000fd8 for a stack pointer. GDB exerpt: Breakpoint 1, 0x000040b6 in Reset_Handler () (gdb) hbreak SVC_Handler Hardware assisted breakpoint 2 at 0x40f8 (gdb) cont Continuing. Breakpoint 2, 0x000040f8 in SVC_Handler () (gdb) print $msp $3 = (void *) 0x20000fd8 (gdb) x/9w $msp 0x20000fd8: 0x1 0x2 0x3 0x4 0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000 0x20000ff8: 0x0 (gdb) cont Continuing. Breakpoint 2, 0x000040f8 in SVC_Handler () (gdb) print $msp $4 = (void *) 0x20000fd8 (gdb) x/9w $msp 0x20000fd8: 0x1 0x2 0x3 0x4 0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200 0x20000ff8: 0x0 Assembly program: .cpu cortex-m0plus .fpu softvfp .thumb .syntax unified .section .vectors @ pvStack: .word 0x20001000 @ pfnReset_Handler: .word Reset_Handler + 1 @ pfnNMI_Handler: .word 0 @ pfnHardFault_Handler: .word 0 @ pfnReservedM12: .word 0 @ pfnReservedM11: .word 0 @ pfnReservedM10: .word 0 @ pfnReservedM9: .word 0 @ pfnReservedM8: .word 0 @ pfnReservedM7: .word 0 @ pfnReservedM6: .word 0 @ pfnSVC_Handler: .word SVC_Handler + 1 .section .text .global Reset_Handler Reset_Handler: cpsie i ldr r0, .stack_start ldr r2, .stack_last eors r1, r1 .loop_clear: str r1, [r0] adds r0, r0, #4 cmp r0, r2 bne .loop_clear subs r2, r2, #4 mov sp, r2 movs r0, #1 movs r1, #2 movs r2, #3 movs r3, #4 svc #0 ldr r0, .stack_start ldr r2, .stack_last eors r1, r1 .loop_clear2: str r1, [r0] adds r0, r0, #4 cmp r0, r2 bne .loop_clear2 mov sp, r2 movs r0, #1 movs r1, #2 movs r2, #3 movs r3, #4 svc #0 .loop: b .loop .align 4 .stack_start: .word 0x20000f00 .stack_last: .word 0x20000ffc @ first call - 0x2000fff8 -- should already be aligned @ second call - 0x2000fffc -- should hit the alignment code .global SVC_Handler SVC_Handler: bx lr Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com> Reviewed-on: http://openocd.zylin.com/3003 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-10-30rtos: turn stack alignment into a function pointerAndrew Ruder9-18/+58
Some targets (Cortex M) require more complicated calculations for turning the stored stack pointer back into a process stack pointer. For example, the Cortex M stores a bit in the auto-stacked xPSR indicating that alignment had to be performed and an additional 4 byte padding is present before the exception stacking. This change only sets up the framework for Cortex-M unstacking and does not add Cortex-M support. Note: this also fixes the alignment calculation nearly addressed by change #2301 entitled rtos/rtos.c: fix stack alignment calculation. Updated calculation is in rtos_generic_stack_align. Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com> Reviewed-on: http://openocd.zylin.com/3002 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2015-10-30Add handling for STM32L4.Uwe Bonnes3-0/+921
Option handling not yet implemented. Change-Id: I5a11ef3221896cb02babe4e6e71073c43aa8740b Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2941 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-10-30stm32f2x: Add memory barrier needed for STM32F7 flashing.Uwe Bonnes1-2/+3
Change-Id: I44fca55c46fc8f960ba46a0604692ce98909face Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2939 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-10-30stm32f2x.c: Add STM32F74x handling.Uwe Bonnes1-6/+36
Change-Id: I2e7a8e9f855fc99a3f2535e2af6c0921329a5013 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2940 Tested-by: jenkins Reviewed-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com> Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-10-30stm32f2x.c: Handle STM32F42x/43x 1 MiByte devices with DB1M option set.Uwe Bonnes1-21/+42
Change-Id: Ic51d34a9abe9693fd21e9b3247523821b6fb1fe3 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2938 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-10-30quark: updating license to GPLv2+Ivan De Cesaris5-10/+15
Intel is relicensing our contributions to OpenOCD under GPL version 2 or any later version. We previously contributed code under GPL version 2 only. It was not our intention to differ from the standard OpenOCD license. We're correcting that here. This also applies retroactively to previous versions of our contributions to OpenOCD. Change-Id: I5e831ed95d03d2044d8e5a8375b21c6e52c933d7 Signed-off-by: Ivan De Cesaris <ivan.de.cesaris@intel.com> Reviewed-on: http://openocd.zylin.com/3044 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-10-30Cortex-M: Detect Flash Patch Revision and implement Rev. 2 handling.Uwe Bonnes2-3/+15
E.g. STM32F7 implements Rev.2. Supercedes abandoned patch 2755 that doesn't evaluate Flash patch revision. Change-Id: I48756b0451c7359475066969c900978a536bc328 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2868 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-10-09nrf51: recognize hwid 0084Peter A. Bigot1-0/+6
Chip markings: N51822 / QFACA1 / 1513AN Change-Id: Idb7fc723850ea08b60b9f5c97a53f1ae8dfc8eb2 Signed-off-by: Peter A. Bigot <pab@pabigot.com> Reviewed-on: http://openocd.zylin.com/2936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-10-09Kinetis: new devices K02, K26, K63, K64, K66, correct K21 and K22 variantsTomas Vanek1-14/+69
K22FN1M0 and K22FX512 has FTFE flash and old style SDID. K22FN128, 256 and 512 has FTFA flash and new style SDID K63 and K64 detects as K61 and K62, see Errata 1N83J e7534 Change-Id: I2aca6f1f18819bb2b2ec4982036510de444ad2ac Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2867 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Patrick Stewart <patstew@gmail.com>
2015-10-09Kinetis: give a reasonable default for max_flash_prog_sizeTomas Vanek1-5/+11
max_flash_prog_size euals to pflash_sector_size_bytes for most of devices. There is no point setting max_flash_prog_size for devices without FS_PROGRAM_SECTOR capability. Check for zero sector_size to avoid div by zero exception in case of device has FlexNVM but the driver does not define nvm_sector_size_bytes Change-Id: Iaf4e007fb1ec3d24c373350410e4bebe504a4c3e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2958 Tested-by: jenkins Reviewed-by: Thomas Schmid <thomas@rfranging.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Patrick Stewart <patstew@gmail.com>
2015-10-09Kinetis: Add K24 support and tidy upPatrick Stewart1-86/+135
The K24 uses the KL-style SDID register and has some flashing quirks, so the kinetis driver does not support it properly. Extend the chip detection routine to support the new SDID format. Add a parameter for the maximum flash size, as the K24 only supports 1k flashing blocks but has 4k sector size. Remove global 'granularity' array, as it's only really needed in one function. Replace 'klxx' with an enum showing which flash commands are actually supported on a given chip. Signed-off-by: Patrick Stewart <patstew@gmail.com> Change-Id: Ie244fab564d58c5cfe4fa36a025f0b2674ffad69 Reviewed-on: http://openocd.zylin.com/2864 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-09-30flash/nor/spi: Add Winbond w25q128fvAlex Forencich1-1/+2
Change-Id: I2e13c02361982468f41f218421ece9046bcc9a5f Signed-off-by: Alex Forencich <alex@alexforencich.com> Reviewed-on: http://openocd.zylin.com/2951 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30ADIv5: Fix typo in log messageEvan Hunter1-1/+1
Change-Id: I9c5e648566b1dd43cb55fd5e30edf8d5f0d189a6 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2892 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30stlink_usb: fix typoJim Paris1-1/+1
Change-Id: I3cf5ced568319878b8bf40743e4c07718f630c68 Signed-off-by: Jim Paris <jim@jtan.com> Reviewed-on: http://openocd.zylin.com/2953 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30armv7m: Fix memory leak in register caching.Marc Schink3-1/+38
Change-Id: I184042d277a52f3940d6d6c13f3d94afc557933d Signed-off-by: Marc Schink <openocd-dev@marcschink.de> [andreas.fritiofson@gmail.com: don't check pointers before free()] Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2881 Tested-by: jenkins
2015-09-30numicro: Integrate Nuvoton NuMicro flash driver.Nemui Trinomius5-1230/+1883
Flash driver "mini51.c" and "nuc1x.c" are same target MCU. This patch integrates each driver and functions, and makes into new "NuMicro" flash driver. Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Reviewed-on: http://openocd.zylin.com/2794 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-09-30flash: Analog Devices ADuCM360 supportIvan Buliev3-0/+583
A target config and a simple flash driver for the ADuCM360 microcontroller. The EEPROM of the chip may be erased and programmed. Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8 Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com> Reviewed-on: http://openocd.zylin.com/2787 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2015-09-30svf: fix segfaults exposed by some SVFPaul Fertser1-1/+14
The problem was reported by jstefanop on IRC, the SVF was generated with Xilinx ISE 14.7. Found and investigated with Valgrind's vgdb service. Change-Id: I32b0e77e0380ce4a391661f97449f9c2a5f83625 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2933 Tested-by: jenkins
2015-09-30tcl_server: Support line buffers up to 4M (v3)Philipp Wagner1-8/+43
Currently, the maximum size of a command sent to the TCL server is 4k. This patch increases this limit up to 4M. Reasoning: To get high-speed JTAG data transfers, I'm using a very long shift register. This reduces the overhead of the state changes, as well as the latency due to the common USB adapter transfers considerably. In order to submit those long DRSCAN commands to OpenOCD over the TCL/TCL interface, long TCL command lines are required. This is enabled by this patch. v3: Address review comments. Drop line instead of connection when realloc() fails. Changes in v2 of this patch: The line buffer is allocated dynamically to avoid an OpenOCD memory overhead if the large buffers are not used. The buffer starts at 4K and increases exponentially up to 1M, and then linearly in 1M increments up to 4M. Change-Id: Iecaef6a56ed5e18e9de4d912a514031ea78fa3bd Signed-off-by: Philipp Wagner <philipp.wagner@tum.de> Reviewed-on: http://openocd.zylin.com/2837 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-09-28server: remove connection limit from tcl and telnet serversAustin Morton4-5/+10
Add constant CONNECTION_LIMIT_UNLIMITED which indicates a service has no connection limit Change-Id: I008d31264010c25fa44ca74eb6d5740eca38bee1 Signed-off-by: Austin Morton <austinpmorton@gmail.com> Reviewed-on: http://openocd.zylin.com/2937 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-09-05server: tcl_trace commandAustin Morton4-11/+140
Implements async target trace output to the tcl server Change-Id: I0178f6404447337d523782a1d2c317457030da40 Signed-off-by: Austin Morton <austinpmorton@gmail.com> Reviewed-on: http://openocd.zylin.com/2588 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-08-19flash/nor/jtagspi: 'retval' may be used uninitializedAlamy Liu1-1/+1
Problem As my compiler has "warnings being treated as errors" on, it shows the error message: error: 'retval' may be used uninitialized in this function Investigation Nothing wrong with the logic, 'retval' would have a value before returning. Just wanna get rid of the compiling "warning as error" message. Solution Provide a reasonable default value Change-Id: I712c15f82819c6c48bee9dceca8de4b18aeb29b0 Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2905 Tested-by: jenkins Reviewed-by: Robert Jordens <jordens@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-08-06svf: flush the queue before reallocing memoryPaul Fertser1-0/+4
During reallocation a new memory region might be allocated and the old one freed. If jtag queue is holding a pointer to the old memory, it will segfault during the execution. Avoid this by flushing the queue before a reallocation attempt is made. This should fix ticket #102. Change-Id: I737fc3f1ebf6d76413a475beb8bf20184fe0233f Reported-by: Alex Forencich <aforencich@users.sf.net> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2899 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-08-06flash : Add support for Atmel at91sam4sa16bEvan Hunter1-0/+33
Change-Id: Ief6833b4bf587fbf53c8fbeee2fc276a95ca0a8a Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2878 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06gdb_server: Add check for malloc failEvan Hunter1-0/+3
Change-Id: I623b30883042eae3253ed29de5c426da760dffa0 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2871 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06bcm2835gpio: Add SWD support, Raspberry Pi 2 support.Christoph Pittracher1-9/+158
Added support for SWD transport similar to sysfsgpio driver. Added configurable peripheral base address to support Raspberry Pi 2. Change-Id: If76d45fbe74ce49f1f22af72e5f246e973237e04 Signed-off-by: Christoph Pittracher <pitt@segfault.info> Reviewed-on: http://openocd.zylin.com/2802 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06at91samd: add chip IDs for SAMC20 and SAMC21 familiesAndrey Yurovsky1-0/+37
Add the chip IDs corresponding to the new 5V "SAMC" parts which are otherwise identical to the SAMD and should work with this driver. Also add the configurations for their Xplained Pro boards. Change-Id: Ic268d4ac384a3a77d4211a94da9f9faf4d8c0f7b Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-on: http://openocd.zylin.com/2809 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06sim3x: fix build failure with clang 3.6Paul Fertser1-7/+5
This fixes a warning as reported by the current clang version: ../../../../src/flash/nor/sim3x.c:867:20: error: address of array 'sim3x_info->device_package' will always evaluate to 'true' . Change-Id: Ie160cbe6df8f491e9beff38d47e2f13575529bf9 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2838 Tested-by: jenkins Reviewed-by: Oleksij Rempel Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06flash/nor/jtagspi: add JTAGSPI driverRobert Jordens3-0/+414
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06flash/nor/tcl: add read_bank and verify_bankRobert Jordens1-0/+177
The only read access to flash chips so is through the target's memory. Flashes like jtagspi do not expose a memory mapped interface to the flash. These commands use the flash_driver_read() driver API directly. Change-Id: I40b910de650114a3f676507f9f059a234377d862 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2842 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06cpld/virtex2: allow JSTART to be disabledRobert Jordens2-5/+12
This adds an option to disable the use of the JSTART instruction when loading bitstreams to xilinx fpgas. JSTART apparently prevents configuration if the startup clock is not set to the jtag clock in the bitstream. xc3sprog is omitting JSTART for all devices. Problems with loading a bitstream that does not have StartupClk:JTAGClk are described here: http://www.xilinx.com/support/answers/56151.html Change-Id: I8137c0bae05a8c3c6f8e2611869f70a770d1651d Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2860 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06flash/nor/spi: add micron/numonyx n25q128Robert Jordens1-0/+1
http://www.micron.com/products/nor-flash/serial-nor-flash https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf Signed-off-by: Robert Jordens <jordens@gmail.com> Change-Id: Icfb830387fabfb1a67e4d00bdf21a10420f6fc1c Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2841 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06target/testee: manage target->stateRobert Jordens1-0/+5
The testee target is usefull for certain non-cpu pass-through situations, for example in the case of a spi flash mapped to the DR of a JTAG tap, as is the case for most FPGAs with SPI flashs behind them. We just manage the RUNNING/RESET/HALTED state in the testee driver to support it being halted which is a requirement for flash banks. Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2840 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06jlink: Add on-board nRF51-DK USB VID and PIDKyle Manna1-2/+2
* Add USB VID and PID for the J-Link interface running on the Nordic Semiconductor nRF51-DK. Also tested with debug out port to debug external boards. * Elimiantes need for `-c "jlink pid 0x1015"` on the openocd cmd line. Change-Id: Ib23acb72b9f5183b76fc7dc22b556982869ae830 Signed-off-by: Kyle Manna <kyle@kylemanna.com> Reviewed-on: http://openocd.zylin.com/2775 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06RTOS: ThreadX support on ARM926E-JSAlexander Drozdov1-2/+160
ThreadX uses two stacking schemas on ARM926E-JS, extend API to use more then one stecking at time. Change-Id: I92d445ad0981b6409ea4c4e7e438d3a7ae39cbe7 Signed-off-by: Alexander Drozdov <adrozdoff@gmail.com> Reviewed-on: http://openocd.zylin.com/2848 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-08-06target: check memory handlers before use for all typesKarl Palsson1-24/+16
MMU types were checking and installing fakes at init, but this wasn't catching all devices. Fixes segfaults when attempting mdw and friends on avr. Change-Id: I5b11f9913157a21f1aeb11ec852f593b529d9be8 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/2791 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Andreas Färber <afaerber@suse.de>
2015-05-17jtag/drivers/stlink: fix SRST issue with stlink-v1Paul Fertser1-1/+1
Even though the latest firmware version for stlink-v1 supports "v2" JTAG API, the hardware SRST handling is still broken; amend the check accordingly. Change-Id: I62c662cd7aa209d2d6e9fe260f5c0be81d0ce672 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2761 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-05-17psoc4: add support for Cypress CCG1 familyVincent Palatin1-0/+9
Add the identifiers to support the flash on the Cypress Type-C Port Controller chips of the CCG1 family : http://www.cypress.com/ccg1/. Tested successfully on CYPD1132-16SXI. Change-Id: I3fe6283379e5bcab964afac31b547ef95535aa2c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://openocd.zylin.com/2757 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-05-17nrf51: refine and extend known devices tablePeter A. Bigot1-16/+34
The notation Gx0 in the nRF51 Series Compatibility Matrix indicates that the specified HWID is valid only for build code 0 of each chip, and for subsequent builds the HWID will be different. Replace the Gx0 notation with G0 throughout, and add the missing HWID for nRF51422 QFAC A1 (present on the newer nRF51 developer boards). See: https://www.nordicsemi.com/eng/nordic/download_resource/41917/5/55913589 See: https://devzone.nordicsemi.com/question/30774/mapping-hwid-to-revision-information/ Change-Id: I79d842137d41342db35904867c48b06fbc6fbc70 Signed-off-by: Peter A. Bigot <pab@pabigot.com> Signed-off-by: Angus Gratton <gus@projectgus.com> Reviewed-on: http://openocd.zylin.com/2593 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-05-17server: avoid the tcl server crashing when there is no targetAustin Morton3-2/+3
Since commit 1d0cf0df37a4e831ca3121ba8987d5848cad3e42 ("server: tcl_notifications command") connecting to the tcl server would terminate openocd. Fix this. Change-Id: I36e2a7482f7db3a30ff7e9f969c3b6cda9599382 Signed-off-by: Austin Morton <austinpmorton@gmail.com> Reviewed-on: http://openocd.zylin.com/2759 Tested-by: jenkins Reviewed-by: Forest Crossman <cyrozap@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-04-24jtag/drivers/ti_icdi: do not segfault when adapter can't be openedPaul Fertser1-0/+3
Change-Id: Id3af8dfd18b13947bca4f3c89c2516ccbcef60b6 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2742 Tested-by: jenkins
2015-04-24rtos/mqx: prevent crash with -rtos autoPaul Fertser1-0/+6
Since mqx comes last in the list, with the auto option its update_threads is called even though it wasn't detected. This check should be removed from all the rtos helpers and moved to the generic code, but better do it later all in one go. Change-Id: If24ab42a58a468d90e9f12028d4c2fb76a9bc2e8 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2741 Tested-by: jenkins
2015-04-24target/cortex_a: examination should be done every time it's asked forPaul Fertser1-3/+3
It was observed on AM437x that after every reset the target's debug regions are unpowered. To be able to properly communicate with the target and perform cortex_a init debug access after a reset event the examination need to be performed every time, not just on OpenOCD start. Change-Id: Idf272e127ee88341e806ee00df154eade573451d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2723 Tested-by: jenkins Reviewed-by: Felipe Balbi <balbi@ti.com>
2015-04-24target: try to reexamine even when polling failsPaul Fertser1-6/+4
After intermittent connection failures or target power failures it might be necessary to try reexamination even when polling fails. This should make communication with Cortex-A targets more reliable. This was runtime tested with stlink attached to an stm32l1 and an FTDI JTAG adapter attached to an stm32f1 target. Change-Id: I38c4db8124b7f4bbf53ddda53c13273449f49c15 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2721 Tested-by: jenkins Reviewed-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Färber <afaerber@suse.de>
generated by cgit v1.1 at 2024-11-16 17:36:05 +0000