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2020-11-04target: handle command 'target current' when no target is presentAntonio Borneo1-1/+3
Is it possible to run OpenOCD without any target, for example to only dump the rom-tables of an arm dap, or to perform low level jtag operations. But without any target created, the command 'target current' causes OpenOCD to abruptly exit. Handle in command 'target current' the case of no targets. Change-Id: Ide15cb13bec84b88ccc3e7126523c04a6d70e636 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5881 Tested-by: jenkins
2020-11-04gdb_server: allow multiple GDB connections to selected targetsAntonio Borneo2-3/+27
The default way of working is to have a single GDB attached to one target, so OpenOCD accepts only one connection to the GDB port of each targets and rejects any further connection. There are some barely safe use cases in which it could get useful having a second GDB connection to the same target. One such use case is while using GDB as a 'non-intrusive memory inspector', as explained in the OpenOCD documentation. One GDB can be left running an infinite loop to dump some memory area, or even analysing the content, while keeping a second GDB ready for user interaction or spot memory check. Add a target configure option to specify the maximum number of GDB connections allowed for that target, keeping the default to 1. Change-Id: I4985a602e61588df0b527d2f2aa5b955c93e125e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5865 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-11-04target/arm_cti: use adiv5_jim_mem_ap_spot_configure()Antonio Borneo2-101/+47
To avoid code duplication, reorganize the code to replace cti_configure() with adiv5_jim_mem_ap_spot_configure(). Reorganize 'struct arm_cti_object' and its sub-'struct arm_cti' moving DAP and mem-AP info in a 'struct adiv5_mem_ap_spot'. Replace cti_configure() with adiv5_jim_mem_ap_spot_configure(). Deprecate the use of '-ctibase' in favor of '-baseaddr'. Change-Id: I43740a37c80de67c0f5e4dc79c3400b91a12e9e8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5869 Tested-by: jenkins
2020-11-04target/arm_adi_v5: add helper to get mem_ap spot in configure/cgetAntonio Borneo2-85/+135
This is somehow an extension of existing adiv5_jim_configure(), but includes the 'address' in the mem_ap. Rewrite adiv5_jim_configure() using the new helper. Change-Id: Ia7effeeece044004d459b45126ed4961a98b8568 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5857 Tested-by: jenkins
2020-10-30target: restore last run state after profilingChristopher Head1-1/+13
Now that it’s possible to start profiling from either a running or a halted state, rather than unconditionally halting after profiling finishes, it makes more sense to restore the processor to whatever state (running or halted) it was in before profiling started. Change-Id: If6f6e70a1a365c1ce3b348a306c435c220b8bf12 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5237 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-30target/cortex_m: reduce duplication in profilingChristopher Head3-47/+24
The Cortex-M implementation of profiling contains a bunch of conditionals and checks to handle both chips which have PCSR and chips which do not. However, the net effect of the non-PCSR branches is actually exactly the same as what target_profiling_default does. Rather than duplicating this code, just detect the situation where PCSR isn’t available and delegate to target_profiling_default. Change-Id: I1be57ac77f983816ab6bf644a3cfca77b67d6f70 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5236 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-30target: allow profiling from runningChristopher Head2-4/+6
There are a handful of implementations of profiling. There is the default implementation, which repeatedly halts and resumes the target, sampling PC each time. There is the Cortex-M implementation, which uses PCSR if available, otherwise falling back to halting and resuming and sampling PC. There is the OR1K implementation, which reads NPC repeatedly. Finally, there is the NDS32 implementation which uses some kind of AICE commands with which I am unfamiliar. None of these (with the possible exception of the NDS32 implementation) actually require the target to be halted when starting profiling. The Cortex-M and OR1K actually resume the target as pretty much their first action. The default implementation doesn’t do this, but is written in such a way that the target just flips back and forth between halted and running, and the code will do the right thing from either initial state. The NDS32 implementation I don’t know about. As such, for everything except NDS32, it is not really necessary that the target be halted to start profiling. For the non-PCSR Cortex-M and default implementations, there is no real harm in such a requirement, because profiling is intrusive anyway, but there is no benefit. For the PCSR-based Cortex-M and the OR1K, requiring that the target is halted is annoying because it makes profiling more intrusive. Remove the must-be-halted check from the target_profiling function. Add it to the NDS32 implementation because I am not sure if that will break when invoked with a running target. Do not add it to any of the other implementations because they don’t need it. Change-Id: I479dce999a80eccccfd3be4fa192c904f0a45709 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5235 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-24target/arc: introduce watchpoints supportEvgeniy Didin1-3/+165
With help of actionpoint mechanism now it is possible to introduce watchpoints support for ARC. Change-Id: I5887335d0ba38c15c377bc1d24a1ef36e138cf65 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5867 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-22cortex_m: support control.FPCASylvain Chouleur3-7/+7
Bit 2 of control register is used if the processor includes the FP extension Change-Id: Ie21bc9de8cae5bad9d841e1908eff3aa0bb29d4b Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai> Reviewed-on: http://openocd.zylin.com/5853 Reviewed-by: Sylvain Chouleur <sylvain.chouleur@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-10-14riscv: fix compile errorAntonio Borneo1-2/+2
The commit b68674a1da72 ("Upstream tons of RISC-V changes.") was proposed well before commit 3ac010bb9f10 ("Fix debug prints when loading to flash"), but the merge got in different order. After latest merge, the master branch fails to compile. Fix the compile error. Change-Id: Ia3bd21d970d589343a3b9b2d58c89e0c49f30015 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5856 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com>
2020-10-14Upstream tons of RISC-V changes.Tim Newsome14-2659/+7226
These are all the changes from https://github.com/riscv/riscv-openocd (approximately 91dc0c0c) made just to src/target/riscv/*. Some of the new code is disabled because it requires some other target-independent changes which I didn't want to include here. Built like this, OpenOCD passes: * All single-RV32 tests against spike. * All single-RV64 tests against spike. * Enough HiFive1 tests. (I suspect the failures are due to the test suite rotting.) * Many dual-RV32 (-rtos hwthread) against spike. * Many dual-RV64 (-rtos hwthread) against spike. I suspect this is an overall improvement compared to what's in mainline right now, and it gets me a lot closer to getting all the riscv-openocd work upstreamed. Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/5821 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2020-10-11target/aarch64: fix use of 'target->private_config'Antonio Borneo1-0/+5
The function adiv5_jim_configure() casts the void pointer 'target->private_config' to a struct adiv5_private_config pointer. This is tricky in case of aarch64, where the private data are in a struct aarch64_private_config that has as first element the struct adiv5_private_config. While the current solution is working fine, it's not clean and requires special attention for any further code development. Override 'target->private_config' to the correct pointer while calling adiv5_jim_configure(). Change-Id: Ic2fc047dd1e57013943d96e6d5879a919d1eb7b3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5847 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-10-11target/aarch64: Use apnum settingKevin Yang1-10/+14
Change aarch64 to use ap-num setting if provided. Fall back to original behavior of using first AP when ap-num is invalid. Change-Id: I0d3624f75c86ba5fd5a322ac60856dbbb6e71eaf Signed-off-by: Kevin Yang <kangyang@google.com> Reviewed-on: http://openocd.zylin.com/5831 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-03target/cortex_m.c: vector_catch command checks if a target is examinedDaniel Trnka1-0/+5
If a target is not examined, command vector_catch crashes while accessing the debug_ap NULL pointer. maskisr and reset_config commands don't require this check. Change-Id: I949b6f6e8b983327dd98fbe403735141f8f0b5d6 Signed-off-by: Daniel Trnka <daniel.trnka@gmail.com> Reviewed-on: http://openocd.zylin.com/5813 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-10-03target/aarch64: a64 disassemblerMete Balci4-1/+218
Add A64 (AArch64) Disassembler using Capstone framework. Change-Id: Ia92b57001843b11a818af940a468b131e42a03fd Signed-off-by: Mete Balci <metebalci@gmail.com> [Antonio Borneo: Rebased on current HEAD] Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5004 Tested-by: jenkins
2020-09-27Use capstone for ARM disassemblerMarc Schink4-1615/+112
Change-Id: I1c9bf3f8178d4a06babe23a918e4411833ebc418 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4812 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20cortex_m: add detection of Cortex M35P and M55Tarek BOCHKATI2-3/+9
Change-Id: I52599b2b09c2dc50c95d64059213c832d380ea31 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5799 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20cortex_m: read and display core security stateTarek BOCHKATI3-1/+25
Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7 Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5798 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-20armv8-m: add SecureFault exceptionTarek BOCHKATI3-1/+12
Change-Id: I4e1963631e834b6334bc917e956c2db4464b7b08 Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5797 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05target: avoid checking for non NULL pointer to free itAntonio Borneo11-87/+43
The function free() can be called with a NULL pointer as argument, no need to check the argument before. If the pointer is NULL, no operation is performed by free(). Remove the occurrences of pattern: if (ptr) free(ptr); In target/openrisc/jsp_server.c, an error is logged if the ptr was already NULL. This cannot happen since the pointer was already referenced few lines before and openocd would have been already SIGSEGV in that case, so remove the log. Change-Id: I290a32e6d4deab167676af4ddc83523c830ae49e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5809 Tested-by: jenkins
2020-09-05openrisc: Fix segv jsp due to free of unallocated dataStafford Horne1-6/+0
The prompt pointer in the jtag serial port is never zero'd or allocated. Completely remove it since there is not much use for it as the target software will provide the actual prompt. Change-Id: Id95d8ccb9f725e53b9d03386b11d91eba1cd6ef4 Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-on: http://openocd.zylin.com/4093 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05openocd: fix command's usage stringAntonio Borneo2-5/+5
The usage string should contain only the command parameters. OpenOCD will automatically prepend the command name to the usage string while dumping the usage or help message. Remove the repeated command name from the usage string. Change-Id: If10a0f1c254aee302b9ca08958390b7f21cdb21b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5824 Tested-by: jenkins
2020-09-05target/arc: fix command's usage stringAntonio Borneo1-10/+10
The usage string should contain only the command parameters. OpenOCD will automatically prepend the command name to the usage string while dumping the usage or help message. Remove the repeated command name from the usage string. Change-Id: I691094a6395acb0e4ea3bea2347ff38379002464 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5822 Tested-by: jenkins
2020-09-05target: use proper format with uint32_tAntonio Borneo30-121/+121
Modify the format strings to properly handle uint32_t data types. While there, fix prototype mismatch between header and C file of the function armv7a_l1_d_cache_inval_virt(). Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5818 Tested-by: jenkins
2020-09-05adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_apAntonio Borneo1-1/+1
Commit 11019a824d02 ("adi_v5: enforce check on AP number value") introduces the macro DP_APSEL_MAX and use it in place of hardcoded magic numbers for the upper limit of AP selection value. Use the macro also while defining the array of struct adiv5_ap in struct adiv5_dap. Change-Id: I88f53ceb710f92a48a8026a365709fbf2d9e6912 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5806 Tested-by: jenkins
2020-09-05Fix debug prints when loading to flashSamuel Obuch1-6/+6
While loading to flash with debug level at least 3, OpenOCD tries to print the whole loaded bitstream. This will be very-very-slow due to implementation of conversion from buffer to string. * fix condition on selected debug level in jtag/core.c * replace slow buf_to_str function from helper/binarybuffer.c with faster but_to_hex_str function Change-Id: I3dc01d5846941ca80736f2ed12e3a54114d2b6dd Signed-off-by: Samuel Obuch <sobuch@codasip.com> Reviewed-on: http://openocd.zylin.com/5800 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-08-08target: fix memory leaks on target_create() failAntonio Borneo1-14/+55
There are failure cases of target_create() that are not checked. Plus, in case of failure the memory allocated in not properly released before returning error. Check all the possible failure in target_create(). Change current_target only when target is successfully created. Add the new target to all_targets list only when target is successfully created. Release all the allocated memory before quit on failure. Use malloc() instead of calloc() for target->type, because the struct will be fully populated with memcpy(). Change-Id: Ib6f91cbb50c28878e7c73dc070b17b8d7d4e902f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5776 Tested-by: jenkins
2020-08-08target: fix registers reading from non examined targetMikhail Rasputin1-1/+10
If a target is not examined when the debugger tries to connect to it then it can lead to undesired/undefined behavior. In particular it leads to a zero pointer dereference on the aarch64. Change-Id: I67f2b714ab8b2727fd36f3de16d7f9017b4c55fe Signed-off-by: Mikhail Rasputin <mikhail.godlike.rasputin@yandex.ru> Reviewed-on: http://openocd.zylin.com/5727 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-08-02target/arm11: fix memory leaks, including register cacheAntonio Borneo3-0/+20
There is no deinit_target method, so few memory allocations leak at openocd exit. Issue identified by tracking all calls to arm_dpm_setup(). Implement the method arm11_dpm_deinit() to free all the memory allocated in arm11_dpm_init() and call it in the new arm11_deinit_target(). NOT TESTED on real HW. Change-Id: Icab86e290fc2db14f70eb84c8286357aadb02a35 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5694 Tested-by: jenkins
2020-08-02target: use one second timeout while halting target at gdb attachAntonio Borneo1-1/+1
By default GDB timeouts after 2 seconds, even if this value can be modified with GDB command "set remotetimeout". On OpenOCD side, the default event for GDB attach is to halt the target and wait it to halt. But here the default timeout of the halt command is 5 seconds! If the target cannot be halted (e.g. it's kept in reset by another core or the debugger doesn't have enough privileges) then GDB will timeout while OpenOCD is still waiting and is unable to communicate with GDB. Decrease the halt timeout to 1 second in the default GDB attach event handler. Change-Id: I231c740816bb6a0d74b0bc679a368a6cbfb34824 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5687 Tested-by: jenkins
2020-07-26target: fix minor typos and duplicated wordsAntonio Borneo47-114/+114
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-07-26target/arm720t: fix memory leak of register cacheAntonio Borneo1-0/+6
There is no method to free the register cache, allocated in arm720t_init_target(). Issue identified by tracking all calls to arm7tdmi_init_target(). Implement the method arm720t_deinit_target() by calling directly arm7tdmi_deinit_target(). NOT TESTED on a real arm720t target. Tested on a arm926ejs (SPEAr320) by hacking the target type and pretending it is a xscale: sed -i s/arm926ejs/arm720t/ tcl/target/spear3xx.cfg Change-Id: I53c1f46c1a355a710e8df01468b19220671569dc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5697 Tested-by: jenkins
2020-07-26target/arm7tdmi: fix memory leak of register cacheAntonio Borneo2-0/+14
There is no method to free the register cache, allocated in arm7tdmi_init_target(), so we get a memory leak. Issue identified by tracking all calls to arm_build_reg_cache(). Implement the method arm7tdmi_deinit_target() that in turn calls arm7tdmi_free_reg_cache(). NOT TESTED on a real arm7tdmi target. Tested on a arm926ejs (SPEAr320) by hacking the target type and pretending it is a arm7tdmi: sed -i s/arm926ejs/arm7tdmi/ tcl/target/spear3xx.cfg Change-Id: Iad465b708eb4ebb298725d7155fea76357e9045c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5696 Tested-by: jenkins
2020-07-26target/xscale: fix memory leak of register cacheAntonio Borneo1-0/+24
There is no method to free the register cache, allocated in xscale_build_reg_cache(), so we get a memory leak. Issue identified by tracking all calls to arm_build_reg_cache(). Implement the method xscale_deinit_target() that in turn calls the new xscale_free_reg_cache(). Fix leak of struct xscale. NOT TESTED on a real xscale target. Tested on a arm926ejs (SPEAr320) by hacking the target type and pretending it is a xscale: sed -i s/arm926ejs/xscale/ tcl/target/spear3xx.cfg Change-Id: Ibb2104c42411b76f4bb77c2fa387d1b85a3d2d5d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5695 Tested-by: jenkins
2020-07-26target: fix memory leaks on targets based on arm9tdmiAntonio Borneo7-0/+62
Similarly to the fix for arm926ejs (also base on arm9tdmi), fix the other targets based on arm9tdmi. The fix for arm926ejs is tested on SPEAr320 target. This fix is proposed separately because is not tested on a correct target device, but tested on SPEAr320 by hacking the target type and pretending it is the correct one, e.g.: sed -i s/arm926ejs/arm920t/ tcl/target/spear3xx.cfg The memory leaks detected and fixed are: - arm register cache; - EmbeddedICE register cache; - arm_jtag_reset_callback internal data; - struct <target_type>_common. Change-Id: I565f9a5bf144a9df78474434d86a64127ef0fbe5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5699 Tested-by: jenkins
2020-07-26src/target/arm_adi_v5.c: add Cortex-A35 related entriesJiri Kastner1-0/+4
ROM Table registers: https://developer.arm.com/documentation/100236/0100/debug/rom-table/rom-table-peripheral-identification-registers Debug reisters: https://developer.arm.com/documentation/100236/0100/debug/memory-mapped-debug-registers/external-debug-peripheral-identification-registers PMU registers: https://developer.arm.com/documentation/100236/0100/debug/pmu-registers/performance-monitors-peripheral-identification-registers CTI registers: https://developer.arm.com/documentation/100236/0100/debug/cti-registers/cti-peripheral-identification-registers Change-Id: Ibd57d91fb9b66bc46929f4e93d0bf23c2a32f11a Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/5773 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2020-07-26src/target/arm_adi_v5.c: resorted idsJiri Kastner1-4/+4
Change-Id: Ieeccf48254032244a86d6cd35793f8f6076527e9 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/5772 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-26target/arc: Introduce Actionpoints supportEvgeniy Didin3-9/+360
Actionpoint mechanism allows to setup HW breakpoints and watchpoints on Synopsys ARC CPUs. This mechanism is controlled by DEBUG register and by a set of auxilary registers. Each actionpoint is controlled by 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV) and AP control(AC). Note: some fields of actionpoint_t structure will be used in further support of watchpoints. Change-Id: I4efb24675f247cc19d9122501c9e63c3126fcab4 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5763 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-08coding style: add arguments to function prototypesAntonio Borneo3-22/+22
Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types FUNCTION_ARGUMENTS -f {} \; This patch also fixes an incorrect function prototype in zy1000.c. ZY1000 minidriver implementation overrides the function arm11_run_instr_data_to_core_noack_inner(), but the prototype is not the same as in src/target/arm11_dbgtap.c and to avoid compile error it was changed also the prototype of the called function arm11_run_instr_data_to_core_noack_inner_default(). Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5630 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-07-08coding style: fix space separationAntonio Borneo9-232/+232
The checkpatch script from Linux kernel v5.1 complains about using space before comma, before semicolon and between function name and open parenthesis. Fix them! Issue identified using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types SPACING -f {} \; The patch only changes amount and position of whitespace, thus the following commands show empty diff git diff -w git log -w -p git log -w --stat Change-Id: I1062051d7f97d59922847f5061c6d6811742d30e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5627 Tested-by: jenkins
2020-07-08coding style: fix print of hex values as decimalAntonio Borneo1-1/+1
It is an error to prefix with "0x" the print of values in decimal. Replace the incorrect decimal format specifier with PRIx32. Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types PRINTF_0XDECIMAL -f {} \; Change-Id: I2eb867ef654527b2737ba573a405ec8f97c6a739 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5624 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-07-08target/arm926ejs: fix memory leaksAntonio Borneo7-0/+44
The memory leaks detected and fixed are: - arm register cache; - EmbeddedICE register cache; - arm_jtag_reset_callback internal data; - struct arm926ejs_common. Issue identified with valgrind. Tested on SPEAr320 based on arm926ejs. Change-Id: If2bed02c516051ce4d0eb29b204a3f3337fe5d6a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5698 Tested-by: jenkins
2020-06-27target: do not print an error on shutdown in target eventsAntonio Borneo1-2/+6
Before commit b3ce5a0ae545 ("target: use LOG_USER to print errors in events") an error in an event handler was silently lost, while now the associated message is printed out. A "shutdown" command in a target event (e.g. in gdb-detach) causes the event to end with error code ERROR_COMMAND_CLOSE_CONNECTION, that triggers the error message: shutdown command invoked Error executing event <event-name> on target <target-name>: The error code returned by the command "shutdown" is required to stop the execution in a script/proc and avoid executing any further command in the script/proc. It is then normal to get an error code from the "shutdown" command and it should not be printed out. Intercept the return code of the event in case of "shutdown", then skip scheduling other target events and return without printing the incorrect error message. Change-Id: Ia3085fb46beacb90a5e4bf0abf7c6e28bb9e6a9b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reported-by: Laurent Lemele <laurent.lemele@st.com> Reviewed-on: http://openocd.zylin.com/5710 Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Tested-by: jenkins
2020-06-27target/arc: Introduce L1I,L1D,L2 caches supportEvgeniy Didin4-5/+328
With this commit we introduce L1 and L2 cache flush and invalidate operations which are necessary for getting/setting actual data during memory r/w operations. We introduce L2 cache support, which is not presented on currently support EMSK board. But L2 is presented on HSDK board, which soon will be introduced. Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5688 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-27aarch64: Add support for debugging in HYP mode on ARMv8-A coresLucas3-2/+12
When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would throw the following error to GDB on most operations (step, set breakpoint): cannot read system control register in this mode The mode in question is 0x1A, a privilege level 2 mode available on cores that have the virtualization extensions (such as the Raspi 3). Note: this mode is only used when running in AArch32 compatibility mode. Signed-off-by: Lucas Jenss <public@x3ro.de> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2 Reviewed-on: http://openocd.zylin.com/5255 Tested-by: jenkins Reviewed-by: Lucas Jenß <lucas.jenss@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-18target/armv7m_trace: Calculate prescaler for external capture devicesMarc Schink1-0/+16
This fixes a regression introduced in "2dc88e1479f29ef0141b05bfcd907ad9a3e2d54c" Change-Id: I04dc19ed30118a4c499b83732700b2ee0fdb67b6 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5610 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-06-06coding style: fix multi-line dereferencingAntonio Borneo1-2/+2
Issue identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types MULTILINE_DEREFERENCE -f {} \; Change-Id: Icba05613e22a72ecc3e6a0aad7cb6b479496146f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5629 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de>
2020-06-06target/cortex_a: fix memory leak of register cacheAntonio Borneo4-0/+25
There is no method to free the register cache, allocated in armv4_5, so we get a memory leak. Issue identified by valgrind. Implement the method arm_free_reg_cache() and call it in cortex_a deinit and to exit for error during arm_dpm_setup(). Tested on dual cortex-A stm32mp15x. This change is inspired from similar fix in commit b01b5fe13a67 ("armv7m: Fix memory leak in register caching."). The same allocation is also used by target types "arm7tdmi", "arm9tdmi", "arm11" and "xscale" but they all lack the deinit method and I do not have relevant HW to test the fix. For such reasons they are not addressed in this patch. Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5693 Tested-by: jenkins
2020-06-06target/mem_ap: fix two memory leaksAntonio Borneo1-0/+10
The target mem_ap misses the method 'deinit_target' and does not free the memory allocated during 'target create' and 'configure'. Add the missing method and free the allocated memory. Issue identified with valgrind. Change-Id: If0d0114a75dd76a8b65c2d46d96c6085fd31a09d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5700 Tested-by: jenkins
2020-06-06target/cortex-m: enable C_DEBUGEN during examineAntonio Borneo1-0/+13
Current code for Cortex M does not set C_DEBUGEN as soon as possible, (which means during target examine), but later-on either: 1) at command 'halt' (e.g. for 'gdb-attach' event); 2) at command 'soft_reset_halt'; 3) at commands 'reset', 'reset halt' or 'reset init'; 4) during polling, but only if the target: = enter in 'double fault', or = exit from a reset, or = halts (not possible if C_DEBUGEN is not set) Plus, if commands in 1) or 2) are executed before the very first poll of the target, the value of 'cortex_m->dcb_dhcsr' is used not initialized while writing it back in DCB_DHCSR. Another side effect of this situation is that it's possible to set a HW breakpoint with the target running, while C_DEBUGEN is not set. Accordingly to [1], C1.3.1 "Debug authentication": When DGBEN is LOW and DHCSR.S_HALT == 0: ... FPB breakpoints do not generate an entry to Debug state and, if no DebugMonitor exception is generated, will escalate to HardFault, Lockup, or be ignored. On STM32MP15x I get HW breakpoint ignored, while on STM32F411 I get HardFault. E.g. following these steps: - power-on a pre-flashed board that starts running the firmware; - connect openocd, without halting or resetting the board; - set a HW breakpoint to some address often executed; - wait, but the board doesn't halt ...; - type the command 'halt'; - if the Cortex-M has HardFault it would be visible and the fault is at the breakpoint address; - if no HardFault then type the command 'resume'; - wait and the board will finally halt at the HW breakpoint. A similar issue has been detected on Cortex-A code and fixed by commit bff87a7f28fb ("target/cortex_a: enable DSCR_HALT_DBG_MODE during examine"). Follow the same approach and set C_DEBUGEN during examine. Also, initialize 'cortex_m->dcb_dhcsr' during examine. [1] ARM DDI 0403E "ARM v7-M Architecture Reference Manual" Change-Id: I5b0b23403634f7dfce38f104bba9f59c33eb3e99 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5702 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Moritz Fischer <moritzf@google.com>
generated by cgit v1.1 at 2024-09-28 21:15:14 +0000