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2013-04-20mips: m4k alternate pracc code. Patch 4Salvador Arroyo2-105/+83
Now all the functions with only fetch accesses are modified. The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work at the same scan rates as the other pracc functions, but it needs higher scan_delays to work. Change-Id: Ifb31d8ea6de9d22674385782913d221a2494dbbf Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1196 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 3Salvador Arroyo4-120/+108
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified. mips32_cp0_read() is very similar to mips32_read_u32() with one store access. mips32_pracc_read_regs() is the only function that can not be executed from only one queue. Now this function is modified to use reg8, it saves all the registers but does not restore reg8. To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and restore it from ejtag info instead of using DeSave for save/restore. Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1195 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 2Salvador Arroyo1-14/+147
Each pracc function defines a variable ctx of type struct pracc_queue_info. To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and pracc_queue_free(). The second parameter in pracc_add() is the store address if the instruction is a store at dmseg, otherwise it should be 0. The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec() is called and it should work like with current code. To generate the delay between scans the number of clock ticks are calculated with the help of jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks are higher as it should be, specially at higher scan rates. mips32_pracc_read_u32() should now work with the new code. Change-Id: I471590a4fc89b56af10bd46c48767b4c64de154f Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1194 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo5-1/+98
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-11arm_adi_v5: fix for csw nonsecure access.Michel JAOUEN2-1/+45
Add command to fix CSW_SPROT in register AP_CSW. This solves dap apmem access in non secure access. Change-Id: I7cfcb6434d75f5cfd4a2630a059901cdeea010ce Signed-off-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-on: http://openocd.zylin.com/1276 Tested-by: jenkins Reviewed-by: mike brown Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: code cleanup in cp0 command handlersSalvador Arroyo2-8/+2
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary. Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: change in restoring debug working registerSalvador Arroyo3-25/+30
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack: mips32_pracc_read_u32() mips32_cp0_read() mips32_pracc_write_mem_generic() And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack. Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug mode and can be modified by mips32_pracc_write_regs() when leaving debug mode. There is no need to read their values from the processor registers every time. The fields reg8 and reg9 are added to struct mips_ejtag to store these register values and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order to store them before any other function needs to restore these registers. For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed, should be made after calling mips_m4k_debug_entry(). For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code, single word read takes now 10 instead of 12. This patch is really the first in a set of patches for an alternate m4k pracc code much faster that current code. At least for me with pic32mx works fine. Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1146 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02mips: mips32_pracc_fastdata_xfer() little modificationSalvador Arroyo1-5/+6
In this function after loading the handler code and the jump code there is a call to wait_for_pracc_rw() to verify that a pracc access is pending. Next the address is read to verify that the handler is running, the address should be at fastdata area. Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already that a pracc access is pending. Better we call this function before loading the end address to be sure it is loaded correctly. Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20 Reviewed-on: http://openocd.zylin.com/1142 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02pic32mx: false pending at low core clockSalvador Arroyo1-1/+6
To show up the fail try to step with the core clock set to 31.25Khz and with a ftdi/hs adapter or with a wiggler, -not with ft2232-. The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail. The code exits with error because the pracc address is at 0x0. It also fails when using the "all" register, but in this case the code works without any message because the pracc address is at 0xff202004 when it fails. I never saw this fail with the core clock set to 500Khz or higher, but ... The workaround simply puts a 1 ms delay after the execution of the DERET instruction. Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02Add abort when JTAG-DP transaction times out.Evan Hunter1-4/+10
Fixes system hang for devices that don't ignore transactions to bad addresses. Change-Id: Ia98344d7efc12951ef79dbc82b8f792b70a22cee Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/1115 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-02arm_adi_v5: fix mem_ap_read_buf_u32() JTAG nastiness..mike brown3-50/+65
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into transport specific file (adi_v5_jtag.c). Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support the move. Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74 Signed-off-by: mike brown <mike@theshedworks.org.uk> Reviewed-on: http://openocd.zylin.com/1277 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: fix broken Cortex-R4 supportSpencer Oliver1-1/+0
This regression was caused due to the recent addition of R4 support and the removal of the bulk_write_memory handler. Change-Id: Ide692737f235c0e9906becb6f3502ba52c5907aa Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1246 Tested-by: jenkins
2013-03-15target: Retire target_bulk_write_memory()Andreas Fritiofson2-16/+0
The only caller was arm_nandwrite(). Replace that call with target_write_buffer() instead, which in turn may end up calling the same bulk_write_memory target API function. Change-Id: If34c7474df5cf14af3b732fb4774816818f28e79 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1214 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson9-71/+9
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15arch: Added ARMv7R and Cortex-R4 supportEvan Hunter4-52/+168
Rewrite to merge Cortex-A and Cortex-R code Change-Id: I4541557980d43d1bba6e8d1bfeb04f536ed25a00 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/358 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15adi_v5: search for Debug and Memory AP supportEvan Hunter4-56/+134
Adds dap_find_ap() function. Change-Id: I6643025624009b12d4936de67a605da52c07be49 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/909 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter6-90/+365
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove read_memory_impAndreas Fritiofson4-26/+16
Change-Id: Idc6ef3b075ccbb5945df8fea746011cb17175d8f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1219 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove write_memory_impAndreas Fritiofson3-18/+11
Change-Id: I5d933bc19443bba8a0193c90471fdd0614324a92 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1218 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove soft_reset_halt_impAndreas Fritiofson2-8/+4
Change-Id: I12c907584ef73de570eba2dcfeb8477cabc6098f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1217 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-06target: use common target_name to access target::cmd_name memberSpencer Oliver2-9/+9
Change-Id: I203b89ef25a072c3b00b504483d5f2a83477fad6 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1182 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Move back off timer to target structMathias K2-17/+20
Move the global target back off timer to the target struct. This will fix the wrong error handling with multi target devices like smp systems. Change-Id: Ia327182ed5d13ca87323700017a8c40ecc6b25a3 Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1179 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-03-05Add the target name to debug output for better understanding and error ↵Mathias K1-2/+3
identification. Change-Id: I1054debea6cd3a6548aadeae2d84000a0039814e Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/1178 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-02-26gdbserver: use common hexify/unhexify routinesSpencer Oliver1-10/+3
Change-Id: I9989b625666e9c60ec9867cf6f4d94f41c998c3f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1105 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2013-02-25target: hla correctly use target eventsSpencer Oliver1-5/+16
Because we were always running using target state TARGET_RUNNING target algorithm's were a bit verbose compared to other targets. This brings the hla target inline with the other targets. Change-Id: I3a257fdc878b87660fac8b5eca22b421eee5b349 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1134 Tested-by: jenkins
2013-02-25armv7m: update to use correct register core_cacheSpencer Oliver1-1/+1
The was missed when the armv7m was moved over to using the std arm core_cache, probably because it is disabled by default. Change-Id: I2f5a18ef6dd783b36e8c29f4c52379104bda4583 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1138 Tested-by: jenkins
2013-02-02armv7m: use ARM_MODE_THREAD core mode for algoorithm'sSpencer Oliver1-2/+2
This makes sure we are using privileged mode when executing any loaders. Change-Id: I18bf32ec92e1c76a66ab25e3712652bc3650b332 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1108 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: restore core mode after executing algorithmSpencer Oliver1-1/+20
Make sure we restore the core mode after executing any algorithm. We also now check that we actually need to swap the core mode, we may already be in the correct mode. Change-Id: Ia48af2c108e0f9868aae241bf25f60323503f092 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1107 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm read/write_core_regSpencer Oliver4-27/+26
Change-Id: I0c15acc1278d2972269d294078495e6b069c830b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/969 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic register core_cacheSpencer Oliver4-59/+52
This removes the armv7m::core_cache and uses the generic arm::core_cache. Change-Id: If854281b31486cea8be005008f6a71a691b4c208 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/968 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: remove unused armv7m_regtypeSpencer Oliver4-20/+7
This simplifies the armv7m_core_reg structure ready for the move to using the generic struct arm_reg. Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/967 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm::core_modeSpencer Oliver6-34/+32
To simplify things change over to using the generic core_mode struct rather than maintaining a armv7m specific one. Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/966 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-01-27hla: enable DWT component and fix watchpointsSpencer Oliver1-4/+4
The makes sure the DWT component is always enabled so that watchpoints work as expected. This does need merging into the existing cortex_m logic, however at the moment this is non trivial. Change-Id: Ic6cccd1badb51f70a2ca8ea9ab6923788a94c1bf Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1122 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-01-02hla: support setting DCB_DEMCR on resumeSpencer Oliver1-0/+5
This is only minimal support to enable use to catch a Hard Fault in the stm32l flash bootloader. Change-Id: I21d6a11893e2f1d173ebff1a651d6f52bf6eec32 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1103 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: jenkins
2012-12-23hla: add ability to configure read/write buffer sizeSpencer Oliver1-6/+6
Other adapters (TI ICDI) that use this driver can use a larger read/write buffer size than the original stlink could. Change-Id: I9beb7748049097cbe29a2340799c450bd74e199d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/948 Tested-by: jenkins
2012-12-23hla: fix watchpoints not being setSpencer Oliver3-1/+8
Watchpoints were not being enabled when the hl adapter target was resumed. This effects both stlink and icdi interfaces. Change-Id: Ia9f8a9415be97a467cd099b63b6bc9f7f37d0c0d Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/931 Tested-by: jenkins
2012-12-23stlink: rename stlink cmd namesSpencer Oliver2-4/+5
As part of the switch to using the hla for the stlink interface we rename the cmds to a more generic name. Update scripts to match new names. Also add handlers for deprecated names. Change-Id: I6f00743da746e3aa13ce06acfdc93c8049545e07 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/921 Tested-by: jenkins
2012-12-23target: add deprecated target name supportSpencer Oliver4-79/+89
This enables us to change the target name without breaking any target scripts. Change-Id: I635f961e573264d3dab2560f3a803ef1986ccfde Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/919 Tested-by: jenkins
2012-12-11mips_m4k: Fixed mips_m4k_resume code for smp targetsKamal Dasu1-1/+1
Fix for bug introduced in in mips smp support code in the resume logic that is checking for wrong return value. Change-Id: Ice3e0069f936b556fecc338ccc12ddba38deeaf6 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1048 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09cortex_a: Fix target entry state route.Evan Hunter1-0/+1
If target is disabled at init, then is examined using 'arp_examine', it can get to cortex_a8_poll with the target state being unknown. Change-Id: Ifffb345bf971d275d2eb1912648b29f0a75f6ccc Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/954 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_m4k: Added SMP debug support for mips architecturesKamal Dasu1-12/+221
This change adds smp debug support for mips platforms. The change leverages the exiting gdb smp support as mentioned in the OpenOCD documentation for using gdb in smp environemnt. Added commands smp_on, smp_off, smp_gdb to control the smp mode. The implementation also provides a way to send Jc packet and toggle the gdb display core context as well. Change-Id: I0835a5aed1844b6ebf8291582912f20695346003 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/937 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_ejtag: Adding EJTAG 4.x and 5.x as valid versionsKamal Dasu1-0/+6
This is a minor change to log EJTAG version 4.x and 5.x as valid versions when debug log is enabled. Change-Id: Ie20458d033c6d22842cb4a31b56765d4ba2ff123 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-30arm: Mis-aligned data issue fix.Jason Moehlman1-2/+3
Fixes issue with big endian hosts and mis-aligned data on some hosts. Fixes unaligned access exception on hosts that do not support unaligned access when debugging some arm targets. Signed-off-by: Jason Moehlman <jmoehlma@linux-software.com> Change-Id: I6bc6fb1b3c3565b256674b9ef43ed2afd14f5178 Reviewed-on: http://openocd.zylin.com/996 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-11-16mips: patch mips32_pracc_exec_write()Salvador Arroyo1-5/+1
No function writes to MIPS32_PRACC_PARAM_IN addresses and probably has no much sense. Any attempt to write to those addresses should be an error. Change-Id: Iebea5fa9954e2cd56ad34976dd7d25009c6e6388 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/975 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_regs() codeSalvador Arroyo1-60/+29
Current code needs 101 pracc accesses for this function, this code needs 12 less. There is a singularity in this code, is the only function that restore a register from param out instead from pracc stack. Obviously the register was previously stored at param out. This save 2 pracc accesses. Change-Id: Ie95b6f983a3198dafc0eab2dd5acc11f871a8d83 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/958 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_write_regs() code.Salvador Arroyo1-61/+43
All the the loads are done with lui and ori instructions, there is no need to save any register, they will be overwritten. Like in the previous patch, for speed optimization in write code, same instructions can be saved if the lower half word or the upper half word is 0. If the lower half word is 0, it can be loaded with only a lui instruction. If the higher half word is 0 it can be done with an ori instruction with register 0. This code saves 10 pracc accesses at a minimum, and 40 at a maximum, obviously if register 2 to 31 are 0 or a half word is 0 Current code needs 91 pracc accesses. Change-Id: I892c5b440191d0c7a474c96845d41c373b7fc637 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/957 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
2012-11-16mips: optimize write code for speedSalvador Arroyo1-245/+113
All the writes are done by the new function mips32_pracc_write_mem_generic(). The code is similar to the read generic code. The reuse of register 15 as memory base address saves 3 pracc accesses. The first write takes 13(12) pracc accesses and for additional writes 3(2). Loading miniprograms should take 25% less time and loading fastdata transfer handler code should be over 2x faster. Change-Id: Ia3b24ba084af33be99da19f00a7fd4d1b291f350 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/956 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize read code for speedSalvador Arroyo1-227/+82
Really nothing new that not explained in previous patches. The code is expanded as needed, there are no loops in pracc code. For the first value pracc accesses are reduced from 39 to 16 and for aditional values from 10 to 3. dump_image should work around 3x faster. Change-Id: I37c9b13395c09eb52a91f10cdb6cbaedef8ab98b Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/955 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips32_pracc_read_u32() functionSalvador Arroyo1-24/+12
This function is highly optimized, there is not much to improve. Loading the base address for pracc access with the new defined MIPS32_PRACC_BASE_ADDR saves one instruction. The memory address is loaded in too steps. First the upper address is loaded. The lower address is passed as an offset in the memory load instruction. The offset is signed, if the lower address is in the range of 0x8000 to 0xffff the offset is a negative value, and the upper address must be incremented by 1. Pracc accesses are now 12 instead of 14. Change-Id: I286945b240ed5c5d5cc540780a41a8a5fa075da3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/952 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize CP0 read/write codeSalvador Arroyo2-51/+28
MIPS32_PRACC_BASE_ADDR is defined as 0xFF200000. Now is possible to load the base address with a lui instruction and only one pracc access. Offsets to the pracc code addresses are defined to simplify the code and probably make it a bit more readable or self-explained. Change-Id: I853dd2d7fad52745931cc6e6be68c0ae156d897e Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/951 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
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