riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-04-09	Only write hartsel if we're changing it.	Tim Newsome	1	-2/+12
2018-04-06	Cache registers while halted.	Tim Newsome	1	-15/+57
2018-04-05	Just read abstractcs once when executing a command	Tim Newsome	1	-9/+4
2018-04-03	Track misa per-hart even in -rtos mode	Tim Newsome	4	-28/+36
2018-04-02	Add gdb_report_register_access_error command	Tim Newsome	2	-9/+0
2018-03-30	Merge pull request #231 from riscv/auth	Tim Newsome	1	-2/+2
2018-03-30	Merge pull request #230 from riscv/deleg	Tim Newsome	1	-0/+8
2018-03-30	Fix auth error message.	Tim Newsome	1	-2/+2
2018-03-27	Once more... Less sloppy this time.	Tim Newsome	1	-1/+1
2018-03-26	Fix m*deleg logic.	Tim Newsome	1	-2/+1
2018-03-23	Make m*deleg regs conditional on U/S/N	Tim Newsome	1	-0/+9
2018-03-19	Add `riscv set_prefer_sba`	Tim Newsome	3	-2/+31
2018-03-19	Fix build, broken by b7c5c5d228.	Tim Newsome	1	-9/+16
2018-03-19	Merge pull request #225 from riscv/old_bus2	Tim Newsome	1	-18/+181
2018-03-15	Merge pull request #222 from riscv/dmi_commands	Tim Newsome	3	-54/+180
2018-03-09	Use TARGET_PRIxADDR instead of PRIx64.	Tim Newsome	1	-1/+1
2018-03-09	Support v0 system bus access	Tim Newsome	1	-18/+181
2018-03-07	Merge pull request #221 from riscv/reg_running	Tim Newsome	1	-4/+4
2018-03-06	Fix cut and paste error message.	Tim Newsome	1	-1/+1
2018-03-06	Add riscv dmi_read/dmi_write commands.	Tim Newsome	3	-54/+180
2018-03-02	Error instead of asserting on reg access failure	Tim Newsome	1	-4/+4
2018-03-02	Don't always error if a debug program fails	Tim Newsome	2	-2/+6
2018-03-02	Remove unable to read register error message	Tim Newsome	1	-7/+3
2018-03-01	Only propagate register errors on some targets	Tim Newsome	2	-0/+9
2018-02-28	Merge pull request #216 from kaspar030/fix_some_fallthroughs	Tim Newsome	1	-0/+5
2018-02-28	Merge pull request #218 from riscv/auth	Tim Newsome	3	-60/+289
2018-02-27	Fix authentication for multi-core targets.	Tim Newsome	1	-6/+35
2018-02-27	Add `authdata_read` and `authdata_write` commands.	Tim Newsome	3	-60/+260
2018-02-26	Merge pull request #217 from riscv/disable_target64	Tim Newsome	2	-6/+6
2018-02-20	Merge pull request #203 from riscv/sysbusbits	Tim Newsome	2	-30/+367
2018-02-20	target/riscv: add some switch fallthrough comments	Kaspar Schleiser	1	-0/+5
2018-02-19	Fix build with --disable-target64	Tim Newsome	2	-6/+6
2018-02-19	Merge pull request #208 from riscv/run_from_trigger	Tim Newsome	3	-21/+51
2018-02-08	Merge pull request #205 from riscv/update	Tim Newsome	26	-463/+1003
2018-02-07	complete reset before writing to hartsel field	Gleb Gagarin	1	-1/+3
2018-02-07	Handle resuming from a trigger...	Tim Newsome	3	-21/+51
2018-02-02	Merge branch 'master' into update	Tim Newsome	26	-463/+1003
2018-01-31	Add unreachable return for mingw build.	Tim Newsome	1	-0/+1
2018-01-31	Fix cut and paste bug.	Tim Newsome	1	-1/+1
2018-01-31	Make OpenOCD work when there is no program buffer.	Tim Newsome	2	-29/+67
2018-01-30	Mention register name instead of number in error	Tim Newsome	1	-1/+1
2018-01-30	Add error handling code to system bus read/write	Tim Newsome	1	-47/+127
2018-01-30	x86_32_common: fix some warnings	Paul Fertser	1	-15/+28
2018-01-29	Merge branch 'riscv' into sysbusbits	Tim Newsome	2	-68/+66
2018-01-29	arm_adi_v5: fix return value of mem_ap_read/write for size 0	Tomas Vanek	1	-2/+2
2018-01-29	aarch64: clean up scan-build errors	Matthias Welwarsky	1	-7/+29
2018-01-26	Detect hartsellen, limiting which harts we probe	Tim Newsome	2	-91/+116
2018-01-26	Clear errors that we see.	Tim Newsome	1	-40/+64
2018-01-26	Add support for v1 system bus access.	Tim Newsome	2	-19/+240
2018-01-26	Use new debug_defines.h	Tim Newsome	1	-11/+11