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AgeCommit message (Expand)AuthorFilesLines
2018-05-30Merge branch 'master' into from_upstreamTim Newsome2-3/+5
2018-05-30Fix warnings exposed by GCC8Paul Fertser2-3/+5
2018-05-25Merge pull request #261 from riscv/trigger_enumv20180629Tim Newsome3-5/+19
2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs3-5/+19
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs24-152/+303
2018-05-22Merge pull request #257 from riscv/commentTim Newsome2-0/+8
2018-05-22Delay trigger enumeration until it's required.Tim Newsome3-5/+19
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
2018-05-17Review feedback.Tim Newsome1-1/+1
2018-05-17Comment riscv_set_register, register_write_directTim Newsome2-0/+8
2018-05-17Merge pull request #251 from riscv/from_upstreamTim Newsome23-149/+285
2018-05-16Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compl...Megan Wachs1-8/+0
2018-05-16riscv: remove unexpected check during resetMegan Wachs1-8/+0
2018-05-14Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs3-103/+222
2018-05-08blank_check_memory prototype has changed.Tim Newsome1-17/+0
2018-05-08arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
2018-05-08target/cortex_m: allow setting the type of a breakpointTomas Vanek2-29/+1
2018-05-08armv8: valgrind memleak fixesMatthias Welwarsky5-7/+70
2018-05-08target armv7m: multi-block erase checkTomas Vanek1-39/+95
2018-05-08target, flash: prepare infrastructure for multi-block blank checkTomas Vanek10-33/+53
2018-05-08target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
2018-05-08target/arm_adi_v5: extend apcsw command to accept arbitrary bitsTomas Vanek3-18/+33
2018-05-08arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bitMatthias Welwarsky4-9/+22
2018-05-07Don't error if hart select isn't implemented.Tim Newsome1-1/+1
2018-05-03Conform to OpenOCD styleTim Newsome1-2/+1
2018-05-03Merge branch 'riscv' into optimizeTim Newsome41-944/+2911
2018-05-03counter*h registers only exist on RV32Tim Newsome1-0/+66
2018-05-01Merge pull request #246 from darius-bluespec/sysbus-bugfixTim Newsome1-1/+3
2018-05-01Properly retry system bus access if busy error was detected.Darius Rad1-0/+2
2018-05-01Fix polling for system bus busy.Darius Rad1-1/+1
2018-04-30Merge branch 'riscv' into notice_resetTim Newsome40-816/+2861
2018-04-27arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
2018-04-24Fix more style issuesRyan Macdonald1-2/+2
2018-04-24Code cleanup from feedback.Ryan Macdonald2-6/+7
2018-04-20Fix mingw32 build.Tim Newsome1-4/+4
2018-04-20Fix error messages for reset dmi timeouts.Tim Newsome1-52/+52
2018-04-20Make encoding.h pass style guide.Tim Newsome1-0/+2
2018-04-20Fix comments in encoding.h.Tim Newsome1-11/+11
2018-04-19riscv-compliance: remove whitespaceMegan Wachs1-6/+6
2018-04-19riscv-compliance: correct the HALTSUM0/HALTSUM1 checksMegan Wachs1-24/+21
2018-04-18riscv-compliance: add dummy comments to appease the linterMegan Wachs1-0/+2
2018-04-18riscv-compliance: whitespaceMegan Wachs1-1/+1
2018-04-18Merge remote-tracking branch 'origin/riscv' into HEADMegan Wachs3-16/+10
2018-04-18Use reset timeout to read dmstatus out of resetTim Newsome1-11/+28
2018-04-18Enforce OpenOCD style guide. (#239)Tim Newsome3-16/+10
2018-04-17riscv-compliance... code that compiles > code that makes linter happyMegan Wachs1-2/+3
2018-04-17riscv-compliance: whitespace cleanupMegan Wachs1-5/+15
2018-04-17Merge remote-tracking branch 'origin/notice_reset' into riscv-complianceMegan Wachs4-182/+227
2018-04-17riscv-compliance: make sure reset assertion and deassertion actually worked.Megan Wachs1-3/+2
2018-04-17riscv-compliance: make sure not to clear DMACTIVEMegan Wachs1-2/+1
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