aboutsummaryrefslogtreecommitdiff
path: root/src/target/mips_ejtag.c
AgeCommit message (Collapse)AuthorFilesLines
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2021-07-24openocd: fix simple cases of NULL comparisonAntonio Borneo1-8/+8
There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-20target/mips: rename CamelCase symbolsAntonio Borneo1-4/+4
No major cross dependencies, mostly changes internal to each file/function. Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6341 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Xiang W <wxjstz@126.com>
2021-03-10target/mips: Remove typedef'd structMarc Schink1-1/+1
The C style guide forbids typedef'd structs, see 'Naming Rules'. Change-Id: I449590251056c478c05105cdc18014ab4eb77ed8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6033 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-04target: declare local symbols as staticAntonio Borneo1-2/+3
Functions and variables that are not used outside the file should be declared as static. Change-Id: I9f97571a528f0cb3c3c26f873577ab16fdec3cdc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5895 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-07-26target: fix minor typos and duplicated wordsAntonio Borneo1-1/+1
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-04-21Remove BUILD_TARGET64Florian Fainelli1-7/+0
BUILD_TARGET64 creates a larger test matrix and mostly gates the building of the aarch64/armv8 target, make that unconditional, which would help fixing any issues with 64-bit address types anyway. Rebased by Antonio Borneo after commit 1fbe8450a9dd ("mips: Add MIPS64 support") Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb Suggested-by: Matthias Welwarsky <matthias@welwarsky.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5240 Tested-by: jenkins
2020-03-07helper/binarybuffer: fix clang static analyzer warningsTomas Vanek1-3/+3
Writing bits to an uninitialized buffer generated false warnings. Zero buffers before setting them by buf_set_u32|64() (do it only if bit-by-bit copy loop is used, zeroed buffer is not necessary if a fast path write is used) Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5383 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-01-20mips_ejtag: there is no DCR.MIPS64 bitJiri Kastner1-1/+1
available revisions (2.60, 3.10, 5.06 and 6.10) of MD00047 (EJTAG specification), have only in IMPCODE MIPS32/MIPS64 bit/flag. Change-Id: If9191b6ced760c59bb7551bb041cd72b0a060bb1 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/4628 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2019-11-28mips: Add MIPS64 supportPeter Mamonov1-0/+144
The patch adds support for processors implementing MIPS64 instruction set. Change-Id: I79a983dfdead81553457a0f3e9e739a9785afaac Signed-off-by: Konstantin Kostyukhin <kost@niisi.msk.ru> Signed-off-by: Andrey Sidorov <anysidorov@gmail.com> Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> CC: Dongxue Zhang <elta.era@gmail.com> CC: Paul Fertser <fercerpav@gmail.com> CC: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2321 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-08mips32, use scan32 function for reading impcode/idcode.Salvador Arroyo1-45/+10
There is no need to implement scan code in functions mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32(). Impcode/idcode saved in ejtag.info. Reorder the code in the callers of this functions. Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <salvador@telecable.es> Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo1-10/+10
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add option to avoid check in last instructionSalvador Arroyo1-2/+2
This option is needed, for example, when exiting debug mode in bmips targets. The last instruction is a NOP, not a DERET. When working in async mode this check is not done, mips32_pracc_queue_exec() pass the parameter to mips32_pracc_exec() and never use it. Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4021 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add realloc codeSalvador Arroyo1-4/+1
If max_code is reached realloc memory. If fails to realloc the error is propagated and every call to pracc_add() returns immediately. The exec function logs the error. Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4020 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, change in pracc_list for dynamic allocationSalvador Arroyo1-2/+2
pracc_list points to an array with code in the lower half and addr in the upper half. Change it to a struct with an instruction field and an address field. Requiered to make reallocation easier. As a side effect the code is less quirky. Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4019 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-25mips32, homogenize code in the scan functionsSalvador Arroyo1-17/+16
Change-Id: I32fed3332857737048dd12da94fcaba140acb726 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4006 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24mips32, add generic scan 32 functionSalvador Arroyo1-29/+19
Will be used later, allow queuing all needed scans in a pracc access. This makes faster execution with ftdi based adapters working in sync with pracc. Added now because the overall code is shorter. Change-Id: Ib32b89307b75785f88870db8d7c9255dc5bbd426 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4005 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24mips32, pic32 use uint8_t in 8 bit scan functionSalvador Arroyo1-14/+7
Makes code shorter. Change-Id: I6cc01adffbea063ccb071ddf3a3e3d81727b29ce Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4004 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-04-16Fix several format specifiers errors exposed by arm-none-eabiPaul Fertser1-3/+3
Change-Id: I1fe5c5c0b22cc23deedcf13ad5183c957551a1b7 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2719 Tested-by: jenkins
2014-08-19mips_ejtag.c: do not set v2.6 ECR bits on v2.0 devicesOleksij Rempel1-2/+5
Change-Id: I894abbb923282d5f84daf8e0bca69190c07567de Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1930 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips_ejtag.c|h: use version specific IMPsOleksij Rempel1-8/+49
and make version specific debug log Change-Id: I17f7ff757cfa1264a1dadbfe20c5e21de62ef87a Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1929 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-05-09mips32: new code for pracc execSalvador Arroyo1-3/+2
This is only the basic code proposed for mips32_pracc_exec() function. It checks every pracc address against the expected address when reading (instruction fetch). The code expects to start at PRACC_TEXT and any subsequent read address is obtained by adding 4 to the previous one. After shifting out all the instructions the code executes a final check. It checks now for the first pass trough PRACC_TEXT and shift out only NOP instructions. A mips core does not need an additional NOP and after the first check it exits if there is no store access pending. After shifting out one NOP the core must be reading at pracc text or the code exits with error. The code continues shifting out NOPs until all store accesses have been performed. After shifting out 10 NOPs it exits with error. No assumption is made about the number of store instruction shifted out or the ordering of the store accesses. It only checks that the number of store accesses is the same as the number of store instructions at dmseg after execution. mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to simpify a bit the code. Fields pa_ctrl and pa_addr are added in ejtag_info for storing values of pracc control and address. Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1827 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2014-03-29mips_ejtag.c: disable DMA for all platformsOleksij Rempel1-2/+5
DMA seems to be broken in many ways. Don't trust it! Change-Id: I7e28608f299abdf78d02a967c62849b6b2ce5985 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1936 Tested-by: jenkins Reviewed-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-10-31Remove unnecessary (void *)Andreas Fritiofson1-1/+1
When pointer casts are needed, cast directly to the correct type, instead of going via void*. Don't explicitly cast to void* if it would have been done implicitly. Change-Id: I4093209200051c5eb62847d00a4b9c8567480068 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1669 Tested-by: jenkins Reviewed-by: Mathias Küster <kesmtp@freenet.de> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-17mips: add breakpoint support for EJTAG 2.0Oleksij Rempel1-0/+41
EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses. This patch add support of EJTAG 2.0, which is part some broadcom SoCs. This work was testet on Broadcom BCM7401. Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1464 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-17mips_ejtag: remove memory protection bit before DMOleksij Rempel1-4/+36
Change-Id: Id1564ae063cea4f056b350436d52df5381ca9608 Signed-off-by: Oleksij Rempel <bug-track@fisher-privat.net> Reviewed-on: http://openocd.zylin.com/1341 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-17mips_ejtag: cache ejtag version to avoid recalculationOleksij Rempel1-9/+8
Some parts of code are version specific. It will be easier if we extract ejtag version and store it some where. Change-Id: I8f9addc42108cba5ae9d61b8ade8f9d7f02a0fb5 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1462 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 4Salvador Arroyo1-5/+4
Now all the functions with only fetch accesses are modified. The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work at the same scan rates as the other pracc functions, but it needs higher scan_delays to work. Change-Id: Ifb31d8ea6de9d22674385782913d221a2494dbbf Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1196 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 3Salvador Arroyo1-19/+15
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified. mips32_cp0_read() is very similar to mips32_read_u32() with one store access. mips32_pracc_read_regs() is the only function that can not be executed from only one queue. Now this function is modified to use reg8, it saves all the registers but does not restore reg8. To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and restore it from ejtag info instead of using DeSave for save/restore. Change-Id: Icc224f6d7e41abdec94199483401cb512cc0b450 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1195 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo1-0/+23
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-02pic32mx: false pending at low core clockSalvador Arroyo1-1/+6
To show up the fail try to step with the core clock set to 31.25Khz and with a ftdi/hs adapter or with a wiggler, -not with ft2232-. The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail. The code exits with error because the pracc address is at 0x0. It also fails when using the "all" register, but in this case the code works without any message because the pracc address is at 0xff202004 when it fails. I never saw this fail with the core clock set to 500Khz or higher, but ... The workaround simply puts a 1 ms delay after the execution of the DERET instruction. Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09mips_ejtag: Adding EJTAG 4.x and 5.x as valid versionsKamal Dasu1-0/+6
This is a minor change to log EJTAG version 4.x and 5.x as valid versions when debug log is enabled. Change-Id: Ie20458d033c6d22842cb4a31b56765d4ba2ff123 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/936 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: code clean up in mips_m4k_debug_entry() functionSalvador Arroyo1-23/+0
The function mips_ejtag_read_debug() is defined in mips_ejtag.c and is called only by mips_m4k_debug_entry() for reading the CP0 debug register. The comment in this function is obviously wrong. There is a generic function to read CP0 registers with similar code. A call to mips32_cp0_read() should work in the same way. The purpose of reading the debug register is to test if the DSS bit is set and clear the SSt bit. It is faster and easier if the SSt bit is cleared without any check. Remark: DSS bit set only means that a debug single-step exception ocurred, but it is not possible to step over a sdbbp instruction, in this case DSS will not be set and the SSt bit not cleared by code. Resume command at another address will step, so really the behavior is not the same. Change-Id: Ibd35f80e0f7669976d96f4ed813830cecf587971 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/950 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-11-16mips: optimize mips_ejtag_step_disable() codeSalvador Arroyo1-38/+21
The code is a bit large compared to mips_ejtag_step_enable(). With the mips32 xori instruction the code can be reused. The number of pracc accesses are reduced from 18 to 7. Change-Id: If3974ebd64da4461c22b089796646990e68e1b72 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/944 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver1-51/+45
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2011-06-01mips: fixup fastdataStefan Mahr1-6/+4
fixup fastdata
2011-05-29mips: fix swapping if running on big endian hostStefan Mahr1-3/+19
2011-05-28mips: fix swapping if openocd is running on big endian hostStefan Mahr1-1/+4
2011-04-05Added mips_ejtag_drscan_32_out() for optimization.Drasko DRASKOVIC1-0/+15
2011-04-01mips: illustrates how to improve performanceØyvind Harboe1-2/+15
Do not require unecessary roundtrips for clocking out data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-31mips: mips32_pracc_exec error propagation fixesØyvind Harboe1-13/+5
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-31mips: mips_ejtag_get_impcode error propagation addedØyvind Harboe1-1/+4
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-31mips: fix mips_ejtag_set_instr error handlingØyvind Harboe1-13/+9
this fn does not fail, it queues data. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-03-31mips: fix error handling for jtag_execute_queue()Øyvind Harboe1-4/+6
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2011-01-04mips32: add fastdata loader working areaSpencer Oliver1-0/+1
Add a working area that is preserved between calls to mips_m4k_bulk_write_memory - this gives us a speed increase of approx 3kb/sec during flash writes to the pic32mx. This area is released during a resume/reset. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-06-15mips_ejtag: -Wshadow warning fixesØyvind Harboe1-2/+2
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-04-10TARGET/MIPS_EJTAG: review scope of functionsAntonio Borneo1-3/+4
Add "static" qualifier to private functions. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-03-20jtag: move towards making out_value constØyvind Harboe1-3/+3
These were relatively straightforward fixes which are backwards compatible. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
generated by cgit v1.1 at 2024-09-27 09:07:57 +0000