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2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-02-13Change isa stringKent Brinkley1-1/+1
Laying the ground work for adding microAptiv core Change-Id: I161a8a8cb250240ebc8518c91e746d6f921c41c7 Signed-off-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-on: http://openocd.zylin.com/2400 Tested-by: jenkins Reviewed-by: Mindy Beseler <mbeseler@yahoo.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-02-11mips32: add gdb target description supportAntony Pavlov1-77/+166
This commit is inspired by commit 1255b18fc650193094666ba8afd2018089cc9794 Author: Spencer Oliver <spen@spen-soft.co.uk> Date: Fri Sep 13 09:44:36 2013 +0100 armv7m: add gdb target description support Change-Id: I75c3971fd0599d34ed49fb73975378b57f2a4af0 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> CC: Oleksij Rempel <linux@rempel-privat.de> CC: Paul Fertser <fercerpav@gmail.com> CC: Gregory Fong <gregory.0xf0@gmail.com> Reviewed-on: http://openocd.zylin.com/1972 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-02-11mips32: use 'unsigned int' for CPU register indicesAntony Pavlov1-14/+13
Change-Id: I77e94b2fe0943a87e1d18d88ebf2a0133aaad728 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2216 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-11-24mips32: fix typosAntony Pavlov1-1/+1
Change-Id: Ibb98fe3da68bf670a5bb83600bb49647db8a4163 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2338 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips32.c: cache debug caps and support EJTAG 2.0 specific changesOleksij Rempel1-10/+15
EJTAG v2.0 indicated some debug caps in IMP register. V2.6 moved them to DCR register. To make it more universal, convert this values and store them for later use. Change-Id: Id6b9f47c9c2ea94d37281ebfcae5acf357261ddf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1932 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips32.c: fix IB and DB bits check for EJTAG v2.0Oleksij Rempel1-4/+9
Change-Id: I4e28dddc1d5d9c2b923ae17beacdd7f73591b1d0 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1931 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-05-09mips: load code in buffer modeSalvador Arroyo1-34/+23
Currently the functions mips32_checksum_memory() and mips32_blank_check_memory() load the code word by word. The bug in cache code is a good reason for doing so. If there is no other reason we can load the code as a buffer to save time. mips_m4k_write_memory() expect a buffer in target endianness, this is done by target_buffer_set_u32_array(). Cleaned up exit code. Tested on ar7241 big endian and pic32mx little endian with verify_image. Flash erase check only tested in pic32mx. Change-Id: Ib63ed98732b2e23b058e7349a0a57934b7604905 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1562 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-14mips32, dsp563xx: fix segfault on Gdb attachPaul Fertser1-1/+1
Since c6216201b249e6a97fcc085e413e3d34e0de6fb7 gdb target description generation support is enabled by default and it counts on checking "feature" pointer in reg_list. Both mips32 and dsp563xx neither used calloc nor explicitly set feature (as it was a newly introduced struct field). This patch changes all targets to use calloc for consistency. Change-Id: I9eceadef8b04aacb108e24ae23cb51ca3009586f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2102 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-02-24mips32: build register cache in a more clear wayAntony Pavlov1-50/+46
This commit is inspired by armv7m_build_reg_cache(). Change-Id: I62b51b2a5f0fed788af167b6f8e60c09b53181be Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/1943 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up many C99 integer types format specifiersPaul Fertser1-1/+1
This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-08-07gdb_server: support gdb target descriptionHsiangkai Wang1-1/+2
* Add a parameter in .get_gdb_reg_list() to return different register lists as generating target description. * Modify STRUCT REG to let gdb generate target description according to register information. The modified structure of register is struct reg { const char *name; uint32_t number; /* for regnum="num" */ struct reg_feature *feature; /* for register group feature name */ bool caller_save; /* for save-restore="yes|no" */ void *value; bool dirty; bool valid; bool exist; uint32_t size; struct reg_data_type *reg_data_type; /* for type="type" */ const char *group; /* for group="general|float|vector" */ void *arch_info; const struct reg_arch_type *type; }; Change-Id: I2096b67adf94518ba0b8b23d8c6a9f64ad7932b8 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1382 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-07-17mips: add breakpoint support for EJTAG 2.0Oleksij Rempel1-6/+16
EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses. This patch add support of EJTAG 2.0, which is part some broadcom SoCs. This work was testet on Broadcom BCM7401. Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1464 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-17mips32: add new functions mips32_configure_ibs and _dbsOleksij Rempel1-28/+53
Split function mips32_configure_break_unit to mips32_configure_ibs and mips32_configure_dbs to make code more readable. This will probably make work easyer with differnet EJTAG versions. Change-Id: I666f949fd7bc3656bdf75e7bcaadb164f15855dd Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1463 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo1-0/+33
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-02mips: code cleanup in cp0 command handlersSalvador Arroyo1-4/+1
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary. Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-04-10Minor bug fixes in Mips32 codeSalvador1-3/+3
Now the the "Fast" version for memory blank check in pic32mx.c can be called: default_flash_blank_check() instead of the "fallback" default_flash_mem_blank_check(). The command "verify_image", without working area, now don't show: checksum mismatch - attempting binary compare when there are no real errors in flash. Change-Id: I256e8ae949289634e1de5c1c2861e4c4c4b7fdce Signed-off-by: Salvador <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/549 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver1-148/+86
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-18cmd: add missing usage varsSpencer Oliver1-0/+1
we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-04Change return value on error.Mathias K1-1/+1
On wrong parameters a error is signalized to the calling function. Change-Id: I484443fdb39938e20382edc9246d5ec546a5c960 Signed-off-by: Mathias K <kesmtp@freenet.de> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/282 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-04retire ERROR_INVALID_ARGUMENTS and replace with ERROR_COMMAND_SYNTAX_ERRORØyvind Harboe1-6/+6
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-08-09mips32: Added CP0 coprocessor R/W routinesDrasko DRASKOVIC1-0/+106
This patch adds MIPS32 CP0 coprocessor R/W routines, as well as adequate commands to use these routines via telnet interface. Now is becomes possible to affect CP0 internal registers and configure CPU directly from OpenOCD.
2011-06-04Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixesFreddie Chopin1-4/+0
2011-06-01mips: fix some more endian madnessStefan Mahr1-0/+7
2011-03-17Fix a bunch of typos.Uwe Hermann1-1/+1
Fix a bunch of typos. Most are in code comments, so nothing should break. UNKOWN_COMMAND and CMD_UNKOWN are not used elsewhere, so correcting the spelling should also not break anything.
2011-01-04mips32: add fastdata loader working areaSpencer Oliver1-0/+1
Add a working area that is preserved between calls to mips_m4k_bulk_write_memory - this gives us a speed increase of approx 3kb/sec during flash writes to the pic32mx. This area is released during a resume/reset. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-10-28src: add loader src descriptionSpencer Oliver1-0/+2
- add comment where to find the various loaders src files. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-07-20mips32: exit_point optional for mips32_run_algorithmSpencer Oliver1-1/+1
As the mips32 uses instruction breakpoints for algorithms we do not really need to check the pc on exit. This now matches the behaviour of the arm codebase. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-06-15mips32: -Wshadow warning fixesØyvind Harboe1-2/+2
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-05-10mips32: 20 second timeout/megabyte for CRC checkSpencer Oliver1-1/+3
There was a fixed 20 second timeout which is too little for large, slow timeout checks. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-04-11TARGET/MIPS32: review scope of functionsAntonio Borneo1-9/+9
Add "static" qualifier to private functions. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-02-28MIPS: add mips algorithm supportSpencer Oliver1-3/+312
- add mips support for target algorithms. - added handlers for target_checksum_memory and target_blank_check_memory. - clean up long lines Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-01-09MIPS: update arch_info access to match other targetsSpencer Oliver1-23/+23
- add target_to_mips32 and target_to_m4k to match test of codebase. - mips32_arch_state now shows if processer is running mips16e isa. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2010-01-05MIPS: merge mips fast_data patch from David N. ClaffeyDavid Claffey1-1/+0
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
2009-12-07target: add debug_reason_name()David Brownell1-1/+1
Provide and use debug_reason_name() instead of expecting targets to call Jim_Nvp_value2name_simple(). Less dependency on Jim, and the code becomes more clear too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24remove target_type register_command callbackZachary T Welch1-5/+0
Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
2009-11-19target: create/use register_cache_invalidate()David Brownell1-15/+0
Create a generic register_cache_invalidate(), and use it to replace three all-but-identical core-specific routines: - armv4_5_invalidate_core_regs() - armv7m_invalidate_core_regs - mips32_invalidate_core_regs() too. Make cache->num_regs be unsigned, avoiding various errors. Net code shrink and simplification. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17target: simplify register get/set opsDavid Brownell1-7/+6
No need to indirect from registered integers to pointers. Just stash the pointers directly in the register struct, and don't even bother registering. This is a small code shrink, speeds register access just a smidgeon, and gets rid of another rude exit() path. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16MIPS: no exit() callsDavid Brownell1-1/+1
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: no implicit #includes of "register.h"David Brownell1-0/+1
Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-13target: remove unused "bitfield" infrastructureDavid Brownell1-3/+7
We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-13command_context_t -> struct command_contextZachary T Welch1-1/+1
Remove misleading typedef and redundant suffix from struct command_context.
2009-11-13target_t -> struct targetZachary T Welch1-15/+15
Remove misleading typedef and redundant suffix from struct target.
2009-11-13reg_t -> struct regZachary T Welch1-6/+6
Remove misleading typedef and redundant suffix from struct reg.
2009-11-13reg_cache_t -> struct reg_cacheZachary T Welch1-3/+3
Remove misleading typedef and redundant suffix from struct reg_cache.
2009-11-13mips_ejtag_t -> struct mips_ejtagZachary T Welch1-2/+2
Remove misleading typedef and redundant suffix from struct mips_ejtag.
2009-11-13mips32_core_reg_t -> struct mips32_core_regZachary T Welch1-6/+6
Remove misleading typedef and redundant suffix from struct mips32_core_reg.
2009-11-13mips32_common_t -> struct mips32_commonZachary T Welch1-12/+12
Remove misleading typedef and redundant suffix from struct mips32_common.
2009-11-13mips32_comparator_t -> struct mips32_comparatorZachary T Welch1-2/+2
Remove misleading typedef and redundant suffix from struct mips32_comparator.
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