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2020-05-03target/armv7m: cosmetic refactorizationTomas Vanek1-5/+7
Introduce a variable 'size' and reduce the number of dereferencing *reg_list_size by using the variable. Change-Id: I3bdf1485a4ed8e34435e8acb3efd0df8d802508c Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5326 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-04-21target/armv7m: minor fixes of target algo exit point checkTomas Vanek1-7/+8
Introduce a new ERROR_TARGET_ALGO_EXIT as currently used ERROR_TARGET_TIMEOUT should be reserved for the timeout only. Do not load PC directly from CPU HW as the register value has already been cached. Change-Id: I0d3630da41fd021676789dc12b52545cc0432ba8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5329 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-03-12arm: Use different enum for core_type and core_modeAntonio Borneo1-1/+1
The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins
2019-06-10target/armv7m: fix register number in armv7m_get_core_reg()Tomas Vanek1-1/+1
armv7m_get_core_reg() calls arm->read_core_reg() arm->read_core_reg() expects the register number as an index to core reglist, not an ARMv7M specific register code. Use reg->number instead of armv7m_reg->num. The change solves assert src/target/armv7m.c:222: armv7m_read_core_reg: Assertion `num < (int)armv7m->arm.core_cache->num_regs' failed. when gdb 'info reg' is issued on a Cortex-M target and no cortex_m_debug_entry() has been called since OpenOCD start (target was halted before OpenOCD start). Change-Id: I32a2294693ef979b613be93aeceb3b0eb06ee6df Ticket: https://sourceforge.net/p/openocd/tickets/216/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5203 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv7m: Use 'bool' data typeMarc Schink1-16/+16
Change-Id: I9cfbba9d81601cc72e2b54ec410e21c7edc4f1c4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4955 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-02-07target start_algorithm: Don't copy the IN mem_params fix uninitialised value.Jean-Christian de Rivaz1-1/+2
Fix the write only out params TODO on armv7m.c Fix conditional move depends on uninitialised value. It was detected while programming a LPC8Nxx with a FTDI adapter. valgrind --leak-check=full --show-leak-kinds=all --track-origins=yes [...] ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E4D3: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E4D3: ftdi_swd_queue_cmd (ftdi.c:1206) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) ==8696== ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E506: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E506: ftdi_swd_queue_cmd (ftdi.c:1207) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) Change-Id: I50f9a8c4516b686cf62ac3c76f47c53465e949da Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4811 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07target algo: do not write reg_param if direction is PARAM_INTomas Vanek1-0/+3
Without this change xxx_start_algorithm() writes all register parameters no matter of their direction. It usually results in writing of uninitialized reg_params[].value - possibly reported by valgrind. While on it fix the wrong parameter direction in kinetis_disable_wdog_algo(). This bug did not have any impact because of unconditional write of reg_params. Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4813 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-08armv7m: always set xPSR.T=1 when starting an algorithmCody P Schafer1-0/+17
xPSR.T sets the processor to Thumb mode when set to 1. ARMv7-M only supports execution of Thumb instructions, so it must always be set to 1. If xPSR.T is set to 0 on armv7m, a usage fault is generated when a instruction execution is attempted. On armv7m, issuing a reset causes the vector table to be examined. PC and xPSR.T are loaded from the vector table at byte offset 4. xPSR.T is taken from the least significant bit this value, PC from the remaining bits. This occurs even with `reset halt`, as the reset itself causes this load to occur without the execution of any instructions. As a result of this, following a reset with a "bad" value programmed in the vector table, openocd would be unable to run algorithms on the target, as running them would immediately result in a usage fault due to xPSR.T being unset (0). Allow algorithms to run regardless of the content of the vector table by explicitly setting xPSR so that xPSR.T=1 prior to executing an algorithm. One can think of this as openocd more closely emulating a reset or branch instruction in executing it's algorithms. Ticket: https://sourceforge.net/p/openocd/tickets/203/ Signed-off-by: Cody P Schafer <openocd@codyps.com> Change-Id: I4dc3427ab195d06c3fd780ea768027fefccc4c28 Reviewed-on: http://openocd.zylin.com/4658 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-07-18Avoid null target->semihosting references.Liviu Ionescu1-3/+3
The new common semihosting code introduced a bug, in certain conditions target->semihosting was used without semihosting being initialised. The solution was to explicitly test for target->semihosting before dereferencing it. Change-Id: I4c83e596140c68fe4ab32e586e51f7e981a40798 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4603 Tested-by: jenkins Reviewed-by: Jonathan Larmour <jifl@eCosCentric.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-04Rework/update ARM semihostingLiviu Ionescu1-3/+7
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10target armv7m: multi-block erase checkTomas Vanek1-39/+95
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode, adapter_khz=1000. Plain read: flash read_bank 0 /dev/null takes 48 seconds. erase_check without this change: flash erase_check 0 takes horrible 149 seconds!! And the same command with the change applied takes 1.8 seconds. Quite a difference. Remove the erase-value=0 version of algorithm as the new one can check for any value. If the target is an insane slow clocked CPU (under 1MHz) algo timeouts. Blocks checked so far are returned and the next call uses increased timeout. Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4298 Tested-by: jenkins Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek1-5/+8
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-03-30target: restructure dap supportMatthias Welwarsky1-3/+0
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-02-10target: Add 64-bit target address supportDongxue Zhang1-6/+6
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-08semihosting: support fileio operationSteven Stallion1-2/+7
This patch adds support for bridging semihosting to GDB's File-I/O remote protocol extension. For the most part operations match up 1:1, however some require a working area to complete successfully, namely operations that devolve to read, stat, and gettimeofday. A new command was added to enable support for fileio named `arm semihosting_fileio`, which ensures that the default behavior remains intact for those that prefer it. Finally, redundant logging was removed from the target_arch_state function; this permits ARM targets to quiesce log output when polling for a fileio reply. This prevents filling the logs with halt/resume messages when using semihosting fileio. Change-Id: Ifbb864fc2373336a501cc0332675b887b552e1ee Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/3566 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-10-30flash/nor: Add erased_value to drivers and pass it to targetsAndreas Färber1-6/+22
struct flash_driver has a default_padded_value field that is similar, but it can be changed by the user for the specific purpose of padding. Add a new erased_value field and initialize it for all targets, particularly stm32lx, xmc4xxx and virtual. Use this value in core.c:default_flash_mem_blank_check(), the slow path. Extend the target API to pass erased_value down to target code. Adding an argument ensures that we catch all callers. This allows us to merge xmc4xxx.c:xmc4xxx_blank_check_memory() into armv7m:armv7m_blank_check_memory(). It further allows us to use default_flash_blank_check() in place of xmc4xxx.c:xmc4xxx_flash_blank_check(), adding a potential slow path fallback, as well as stm32lx:stm32lx_erase_check(), adding the potential armv7m fast path with fallback to default_flash_mem_blank_check(). Fix a mips32 code comment while at it (zeroed -> erased). The armv4_5 and mips32 target implementations will now error out if an erase value other than 0xff is used, causing default_flash_blank_check() to fall back to the default_flank_mem_blank_check() slow path. Change-Id: I39323fbbc4b71c256cd567e439896d0245d4745f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3497 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-22armv7m: Integrate build of checksum codeAndreas Färber1-33/+1
Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-14armv7m: Improve armv7m_blank_check_memory() error handlingAndreas Färber1-1/+2
Clean up the working area in case writing fails. Adapted from armv7m_checksum_memory(). Change-Id: I4e5950f568ed70a72a1dcfd77e3321110b17e1de Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3469 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-02-29armv7m: Integrate build of erase check codeAndreas Färber1-9/+1
Instead of documenting the file path as a comment and inline-commenting the THUMB bytecode, include the hex array via preprocessor. This assures the path is actually up-to-date and facilitates updating the code. Change-Id: Ieb0a7cd0bc14882ac96750f524616d9768a0c6f5 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3134 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-09-30armv7m: Fix memory leak in register caching.Marc Schink1-0/+28
Change-Id: I184042d277a52f3940d6d6c13f3d94afc557933d Signed-off-by: Marc Schink <openocd-dev@marcschink.de> [andreas.fritiofson@gmail.com: don't check pointers before free()] Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2881 Tested-by: jenkins
2015-03-25armv7m: add generic trace support (TPIU, ITM, etc.)Paul Fertser1-0/+3
This provides support for various trace-related subsystems in a generic and expandable way. Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2538 Tested-by: jenkins
2015-03-09armv7m: do not access FPU registers when not presentPaul Fertser1-4/+4
This is runtime and valgrind tested with l0, l1 and f3 hla boards. Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2516 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-03-09armv7m: add FPU registers supportPaul Fertser1-17/+74
This patch adds the fpv4-sp-d16 registers to the armv7m register set. The work is inspired by Mathias K but takes a different approach: instead of having both double and single presicion registers in the cache this patch works only with the doubles and counts on GDB to split the data in halves whenever needed. Tested with HLA only (on an STM32F334 disco board). Currently this patch makes all ARMv7-M targets report an FPU-enabled target description to GDB. It shouldn't harm if the user is not trying to access non-existing FPU. However, the plan is to make this depend on actual FPU presence later. Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a Signed-off-by: Mathias K <kesmtp@freenet.de> [fercerpav@gmail.com: rework to fit target description framework] Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/514 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-10-06target: constify structuresSpencer Oliver1-2/+2
Change-Id: I875cfab8dec4ade72ed9c9cd7d52baaca182a1ef Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2295 Tested-by: jenkins
2014-03-29armv7m: remove magic numbers for number of core registersSpencer Oliver1-3/+3
Change-Id: I4296b812f0211011ccf3da8d203545dfba493903 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2053 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-03-29armv7m: Do not ignore 'value' parameter in armv7m_write_core_regAndrey Smirnov1-5/+3
Ignoring the value parameter in that function makes its code rather misleading. Also the only caller of it, armv7m_restore_context already does the whole "buf_get_u32" conversion business, so using 'value' also removes the waste of doing the conversion twice. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Change-Id: I515979c314d9b59ee1065c55b5bb5747c7e93f01 Reviewed-on: http://openocd.zylin.com/2057 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-10cortex_m: target implementation renames cortex_m3 to cortex_mSpencer Oliver1-4/+4
We changed the actual target name quite a while ago. This changes the actual target function names/defines to also match this change. Change-Id: I4f22fb107636db2279865b45350c9c776e608a75 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1626 Tested-by: jenkins
2013-09-21armv7m: add gdb target description supportSpencer Oliver1-45/+56
Change-Id: I7c01109c0b85d208fb04a7ae1185fab4b2ab96b8 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1620 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-09-21armv7m: remove gdb register hacksSpencer Oliver1-27/+0
Now that we support the target description format we do not need these hacks anymore, we can now tell gdb what registers we support. Change-Id: Ie774231d296420b35efcf708bc4435475c87ff5e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1617 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-08-07gdb_server: support gdb target descriptionHsiangkai Wang1-1/+2
* Add a parameter in .get_gdb_reg_list() to return different register lists as generating target description. * Modify STRUCT REG to let gdb generate target description according to register information. The modified structure of register is struct reg { const char *name; uint32_t number; /* for regnum="num" */ struct reg_feature *feature; /* for register group feature name */ bool caller_save; /* for save-restore="yes|no" */ void *value; bool dirty; bool valid; bool exist; uint32_t size; struct reg_data_type *reg_data_type; /* for type="type" */ const char *group; /* for group="general|float|vector" */ void *arch_info; const struct reg_arch_type *type; }; Change-Id: I2096b67adf94518ba0b8b23d8c6a9f64ad7932b8 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1382 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-07-26cortex_m: change cmd output to use cortex_m rather than cortex_m3Spencer Oliver1-1/+1
Change-Id: I33834910c44d22169bcf684e9697a8db49d0b396 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1513 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-2/+2
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-02-25armv7m: update to use correct register core_cacheSpencer Oliver1-1/+1
The was missed when the armv7m was moved over to using the std arm core_cache, probably because it is disabled by default. Change-Id: I2f5a18ef6dd783b36e8c29f4c52379104bda4583 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1138 Tested-by: jenkins
2013-02-02armv7m: use ARM_MODE_THREAD core mode for algoorithm'sSpencer Oliver1-2/+2
This makes sure we are using privileged mode when executing any loaders. Change-Id: I18bf32ec92e1c76a66ab25e3712652bc3650b332 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1108 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: restore core mode after executing algorithmSpencer Oliver1-1/+20
Make sure we restore the core mode after executing any algorithm. We also now check that we actually need to swap the core mode, we may already be in the correct mode. Change-Id: Ia48af2c108e0f9868aae241bf25f60323503f092 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1107 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm read/write_core_regSpencer Oliver1-19/+19
Change-Id: I0c15acc1278d2972269d294078495e6b069c830b Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/969 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic register core_cacheSpencer Oliver1-32/+32
This removes the armv7m::core_cache and uses the generic arm::core_cache. Change-Id: If854281b31486cea8be005008f6a71a691b4c208 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/968 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: remove unused armv7m_regtypeSpencer Oliver1-3/+1
This simplifies the armv7m_core_reg structure ready for the move to using the generic struct arm_reg. Change-Id: I8edb9d77cc54965d49cd2e754568ebcea4cf6964 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/967 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-02-02armv7m: use generic arm::core_modeSpencer Oliver1-11/+7
To simplify things change over to using the generic core_mode struct rather than maintaining a armv7m specific one. Change-Id: Ibf32b785d896fef4f33307fabe0d8eb266f7086f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/966 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2012-05-14armv7m: update crc/erase_check loaders for cortex-m0Spencer Oliver1-49/+48
Use loaders that have been built for cortex-m0, making them usable for both cortex-m0 and cortex-m3 families. Change-Id: Ifd82be87eaec2cb96464290c80800cec3630d619 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/604 Tested-by: jenkins
2012-03-30armv7m: detect floating point featureMathias K1-0/+1
This patch add fp feature detection on cortex-m4. Change-Id: I99e9d1bf5534630a22b8ad9c878165683db2d0ba Signed-off-by: Mathias K <kesmtp@freenet.de> Reviewed-on: http://openocd.zylin.com/524 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-02-06build: cleanup src/target directorySpencer Oliver1-115/+110
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-18target: move regmaps to armv7m.cSpencer Oliver1-0/+18
This move will enable use to share with regmaps with the stlink target. Change-Id: If8f41c7c53323d5074cb22ec3440530c1e402004 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/377 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-04retire ERROR_INVALID_ARGUMENTS and replace with ERROR_COMMAND_SYNTAX_ERRORØyvind Harboe1-6/+6
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-10-25armv7m: improve error handlingAndreas Fritiofson1-31/+23
Propagate errors unchanged. Free allocated working area in the error return path. Remove duplicated cleanup code by rewriting the logic. As a side-effect, fixes a scan-build warning. Change-Id: I80e3c0015be672778f916e998c8c2e4f23d7588c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/117 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2011-10-09armv7m: implement async algorithm functionsAndreas Fritiofson1-40/+70
Split armv7m_run_algorithm into two pieces and use them to reimplement it. The arch_info parameter is used to keep context between the two calls, so both calls must refer to the same armv7m_algorithm struct. Ugly but works for a proof-of-concept. Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2011-03-17Fix a bunch of typos.Uwe Hermann1-1/+1
Fix a bunch of typos. Most are in code comments, so nothing should break. UNKOWN_COMMAND and CMD_UNKOWN are not used elsewhere, so correcting the spelling should also not break anything.
2010-12-29warnings: use more 'const' for char *Øyvind Harboe1-1/+1
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-10-28src: add loader src descriptionSpencer Oliver1-0/+2
- add comment where to find the various loaders src files. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
generated by cgit v1.1 at 2024-09-28 16:06:58 +0000