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2021-07-20target/arm: opcodes: rename CamelCase symbols and uppercase variablesAntonio Borneo1-93/+93
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6340 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-08-24build: fix clang warningsMartin Nowak1-2/+2
Change-Id: I3c6a63a18034535f0a8c2c62ba8a708f09d7839b Signed-off-by: Martin Nowak <dawg@dawgfoto.de> Reviewed-on: http://openocd.zylin.com/765 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver1-237/+101
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-23cleanup: rename armv4_5 to arm for readabilitySpencer Oliver1-20/+20
Nothing more than a name change, just to make reading the code a bit simpler. Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/390 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2011-10-26clang: fix warning about use of unitialized variableØyvind Harboe1-1/+1
this was a false positive, silence it. Change-Id: I432e0c466c94cf8fd6bbf0ea153c8501a8a261eb Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/126 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-06-07Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - leftover ↵Freddie Chopin1-9/+0
changes
2010-06-15arm_simulator: -Wshadow warning fixesØyvind Harboe1-11/+11
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-04-10ARM_SIMULATOR: review scope of functionsAntonio Borneo1-1/+1
Add "static" qualifier to private functions. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2009-12-07ARM: use <target/arm.h> not armv4_5.hDavid Brownell1-0/+1
Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: switch target_to_armv4_5() to target_to_arm()David Brownell1-1/+1
And remove that old symbol. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_state_* as arm_state_*David Brownell1-2/+2
And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell1-3/+3
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell1-2/+2
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell1-14/+14
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "log.h" to <helper/log.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "log.h" the following form should be used. #include <helper/log.h> The exception is from .c files in the same directory.
2009-12-03change #include "binarybuffer.h" to <helper/binarybuffer.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "binarybuffer.h" the following form should be used. #include <helper/binarybuffer.h> The exception is from .c files in the same directory.
2009-11-22ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell1-1/+1
Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: simplify CPSR handlingDavid Brownell1-1/+1
Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: don't include "log.h" from "armv4_5.h"David Brownell1-0/+1
No point in multiple includes, and that file doesn't use its functions any more. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: no implicit #includes of "register.h"David Brownell1-0/+1
Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-16target: less implicit inclusion of "command.h"David Brownell1-1/+0
Lots of files still include it, often through needless duplicate inclusion of "log.h"; sigh. This cleans up the inclusion graph a bunch, so there are fewer inclusion paths, but it doesn't change much otherwise. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-13target_t -> struct targetZachary T Welch1-2/+2
Remove misleading typedef and redundant suffix from struct target.
2009-11-13armv4_5_common_t -> struct armZachary T Welch1-8/+8
Remove misleading typedef and just use struct arm.
2009-11-13arm_instruction_t -> struct arm_instructionZachary T Welch1-1/+1
Remove misleading typedef and redundant suffix from struct arm_instruction.
2009-11-08ARM: minor simulator cleanupDavid Brownell1-25/+49
Make several functions be static. Shrink some of the overlong lines. Use pure tab indents in some places that mixed in spaces. This gives a minor object code shrink (about 2% on amd64). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-05ARM: other code uses the new inheritance/nesting schemeDavid Brownell1-12/+10
Remove most remaining uses of target->arch_info from ARM infrastructure, where it hasn't already been updated. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-27ARM: fix single-step of Thumb unconditional branchNicolas Pitre1-2/+2
Only type 1 branch instruction has a condition code, not type 2. Currently they're both tagged with ARM_B which doesn't allow for the distinction. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-26ARM: fix Thumb mode handling when single-stepping register based branch insnsNicolas Pitre1-22/+33
Currently, OpenOCD is always caching the PC value without the T bit. This means that assignment to the PC register must clear that bit and set the processor state to Thumb when it is set. And when the PC register value is transferred to another register or stored into memory then the T bit must be restored. Discussion: It is arguable if OpenOCd should have preserved the original PC value which would have greatly simplified this code. The processor state could then be obtained simply by getting at bit 0 of the PC. This however would require special handling elsewhere instead since the T bit is not always relevant (like when PC is used with ALU insns or as an index with some addressing modes). It is unclear which way would be simpler in the end. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-26ARM: allow proper single stepping of Thumb BL and BLX instructionsNicolas Pitre1-0/+12
Whenever an unconditional branch with the H bits set to 0b10 is met, the offset must be combined with the offset from the following opcode and not ignored like it is now. A comment in evaluate_b_bl_blx_thumb() suggests that the Thumb2 decoder would be a simpler solution. That might be true when single-stepping of Thumb2 code is implemented. But for now this appears to be the simplest solution to fix Thumb1 support. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-26ARM: call thumb_pass_branch_condition() only for actual branch opcodesNicolas Pitre1-8/+6
Calling it first with every opcodes and then testing if the opcode was indeed a branch instruction is wasteful and rather strange. If ever thumb_pass_branch_condition() has side effects (say, like printing a debugging traces) then the result would be garbage for most Thumb instructions which have no condition code. While at it, let's make the nearby code more readable by reducing some of the redundant brace noise and reworking the error handling construct. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-10-19fix single step of bx instruction going into Thumb modeNicolas Pitre1-1/+1
Without this fix, the following code cannot be single stepped: add ip, pc, #1 bx ip [thumb code here]
2009-10-13fix pass_condition() LE condition code checkLennert Buytenhek1-3/+3
The LE check is obviously buggy (as easily triggered during some testing), but I didn't audit the rest of the cases. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-08-27refactor arm simulator to allow arm11 code to use it as well - no observable ↵oharboe1-48/+129
changes otherwise. git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-23Remove whitespace at end of lines, step 1.zwelch1-57/+57
- Replace '\s*$' with ''. git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-23- Replace 'if(' with 'if ('.zwelch1-8/+8
git-svn-id: svn://svn.berlios.de/openocd/trunk@2357 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-18Transform 'u32' to 'uint32_t' in src/target/arm*zwelch1-24/+24
- Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2278 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-18Transform 'u16' to 'uint16_t'zwelch1-2/+2
- Replace '\([^_]\)u16' with '\1uint16_t'. - Replace '^u16' with 'uint16_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2277 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-06-18Transform 'u8' to 'uint8_t' in src/targetzwelch1-7/+7
- Replace '\([^_]\)u8' with '\1uint8_t'. - Replace '^u8' with 'uint8_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2274 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-11Audit and eliminate redundant #include directives in arm target files.zwelch1-2/+0
git-svn-id: svn://svn.berlios.de/openocd/trunk@1714 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-04-14Solve problem with single stepping.mlu1-1/+8
git-svn-id: svn://svn.berlios.de/openocd/trunk@1455 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-10-28Hongtao Zheng - fix a simulation error for "BX PC"oharboe1-0/+7
git-svn-id: svn://svn.berlios.de/openocd/trunk@1109 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-10-23hontor <hontor@126.com> - fix simulation step errorsoharboe1-3/+9
git-svn-id: svn://svn.berlios.de/openocd/trunk@1097 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-10-14Laurentiu Cocanu - add error handlingoharboe1-5/+21
git-svn-id: svn://svn.berlios.de/openocd/trunk@1057 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-03-25- rename log functions to stop conflicts under win32 (wingdi)ntfreak1-5/+5
git-svn-id: svn://svn.berlios.de/openocd/trunk@523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-03-01- removed warnings "xxxxx" might be used uninitialized in this function ↵mifi1-2/+2
(arm_simulator.c) - some cosmetic changes git-svn-id: svn://svn.berlios.de/openocd/trunk@423 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2008-01-11- debug handler file not closed - (thanks to oyvind harboe for the patch)ntfreak1-3/+6
- arm_simulate_step called incorrect arm_evaluate_opcode when in thumb mode git-svn-id: svn://svn.berlios.de/openocd/trunk@254 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2007-05-29- split fileio handling into fileio part and image handlingdrath1-14/+36
- reworked etm/etb into a generic etm part with trace capture drivers (currently only etb supported) - added XScale debug handler binary to repository - added Thumb disassembling (thanks to Vincent Palatin for this patch) - added support for non-CFI compatible flashes to cfi driver (currently only SST39VFxxx devices supported) This checkin is experimental, not suitable for general use git-svn-id: svn://svn.berlios.de/openocd/trunk@155 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2007-03-28- merged XScale branch back into trunkdrath1-0/+684
- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c - free working area and register stuff if str7x block write algorithm failed - check PC after exiting a target algorithm in armv4_5.c git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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