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2017-03-06arm_dpm: fix dpm setupGirts Folkmanis1-1/+1
When ARM64 support was being merged, a comparison ended up being inverted. This causes NULL pointer access when target attempts to use core cache. Change-Id: Ic8873ddd13dbdd8100856a71b4717f44cd336e23 Signed-off-by: Girts Folkmanis <opensource@girts.me> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4042 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: unify armv7-a and armv8 debug entry decodingMatthias Welwarsky1-10/+6
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky1-249/+75
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung1-9/+21
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add 64bit register handling.David Ung1-86/+247
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add new state ARM_STATE_AARCH64David Ung1-0/+4
Add new enum ARM_STATE_AARCH64 to the list of possible states. Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-01-20arm_dpm: avoid duplicating the register cacheMatthias Welwarsky1-4/+7
This bug was already attempted to fix in an earlier patch but merging the "defer-examine" feature caused a regression, which this patch tries to fix again. Change-Id: Ie1ad1516f0d7f130d44e003d6c29dcc1a02a82ca Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3951 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-08-09Fix resume when core state has been modifiedMatthias Welwarsky1-0/+25
Sometimes it is necessary to resume into a different state (ARM/Thumb) than at debug state entry. According to the documentation this should be possible with "arm core_state arm|thumb" before the resume command, however the original code also restores the original CPSR, which overrides whatever state the core was set to. This seems to work on some cores (e.g. Cortex-A5) but not on others (e.g. Cortex-A9). Using the "BX" instruction to set resume PC and core state works on Cortex-A9 and ARM11, but is not sufficient on Cortex-A5, where an explicit write to the PC (MOV pc, r0) is required additionally. Change-Id: Ic03153b4b250fbb8cf6c75f8e329fb34829aa35f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3386 Tested-by: jenkins Reviewed-by: Alexander Stein <alexanders83@web.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-03-09armv7m: add FPU registers supportPaul Fertser1-1/+1
This patch adds the fpv4-sp-d16 registers to the armv7m register set. The work is inspired by Mathias K but takes a different approach: instead of having both double and single presicion registers in the cache this patch works only with the doubles and counts on GDB to split the data in halves whenever needed. Tested with HLA only (on an STM32F334 disco board). Currently this patch makes all ARMv7-M targets report an FPU-enabled target description to GDB. It shouldn't harm if the user is not trying to access non-existing FPU. However, the plan is to make this depend on actual FPU presence later. Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a Signed-off-by: Mathias K <kesmtp@freenet.de> [fercerpav@gmail.com: rework to fit target description framework] Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/514 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-09-22target/arm_dpm: prevent endless loop in arm_dpm_full_context()Paul Fertser1-6/+7
The code treats registers that are shadowed in FIQ mode in a special way: to read them out the target is first switches to USR mode. But since USR != ANY the current implementation later skips register read, and the loop becomes endless in case any !valid ARM_MODE_ANY is present at the moment arm_dpm_full_context() is called. This was reported in https://sourceforge.net/p/openocd/tickets/76/. The issue surfaced because 2efb1f14f611f2ff8a380b703f3e8bcb8a95d1ad added two ARM_MODE_ANY registers ("sp" and "lr") which were not normally read, so at the time a user was calling "arm reg" they were not valid. Fix this by changing the mode appropriately while keeping the "mode" variable state intact so it would later match register's mode. Compile-tested only. Change-Id: I01840e8fa20ec392220138a3f1497ac25deb080a Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2278 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver1-156/+155
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-04retire ERROR_INVALID_ARGUMENTS and replace with ERROR_COMMAND_SYNTAX_ERRORØyvind Harboe1-6/+6
Change-Id: I6dee51e1fab1944085391f274a343cdb9014c7a4 Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com> Reviewed-on: http://openocd.zylin.com/300 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2011-09-30armv7a ,cortex a : add L1, L2 cache support, va to pa supportMichel Jaouen1-1/+1
2010-07-19arm_dpm: error propagation fixesØyvind Harboe1-2/+26
found by inspection Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-15arm_dpm: -Wshadow warning fixØyvind Harboe1-3/+3
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-25change %x and %d to PRIx32 and PRId32 where needed for cygwinDaniel Bäder1-1/+1
2010-02-21ARM: keep a handle to the PCDavid Brownell1-2/+2
Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-02-21ARM DPM: support adding/removing HW breakpointsDavid Brownell1-38/+113
Generalize the core of watchpoint setup so that it can handle breakpoints too. Create breakpoint add/remove routines which will use that, and hook them up to target types which don't provide their own breakpoint support (nothing, yet). This suffices for hardware-only breakpoint support. The ARM11 code will be able to switch over to this without much trouble, since it doesn't yet handle software breakpoints. Switching Cortex-A8 will be a bit more involved. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-28ARM: reference DPM defn from v6/v7 arch specDavid Brownell1-0/+6
The term "DPM" is probably not well known ("Device Power Management"?), so identify its source in the current ARM architecture specification. It's relevant to ARMv6, ARMv7-A, and ARMv7-R ... but not "M" profiles. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-15ARM DPM: disable some nyet-ready breakpoint codeDavid Brownell1-6/+14
Until we manage breakpoints at runtime (patches not ready for 0.4) the only way this code should touch them is to disable them at server startup (a previous debug session may have left them active). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-11ARM DPM: support updating HW breakpointsDavid Brownell1-41/+66
Abstract the DPM breakpoint and watchpoint data structures to have a shared core for housekeeping. Abstract the code updating the watchpoint registers so that it can be used to update breakpoint registers. Then do so, when something has set up the breakpoint state used by this code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: use <target/arm.h> not armv4_5.hDavid Brownell1-1/+1
Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: move opcode macros to <target/arm_opcodes.h>David Brownell1-0/+1
Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM DPM: don't write low bits of watchpoint valueDavid Brownell1-1/+1
The low two bits are defined as should-be-zero-or-presereved. We'll take the zero option, it's easier to enforce. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_build_reg_cache() as arm_*()David Brownell1-1/+1
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_mode_* AS arm_mode_*David Brownell1-9/+9
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_MODE_* as ARM_MODE_*David Brownell1-25/+25
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename ARMV4_5_STATE_* as ARM_STATE_*David Brownell1-6/+6
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04target: cygwin build fixesDavid Brownell1-2/+6
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03doxygen: remove some warningsDavid Brownell1-0/+1
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03ARM DPM: share debug reason logicDavid Brownell1-0/+36
No point in both ARM11 and Cortex-A8 having private copies of the logic sorting out e.g. DBG_REASON_WATCHPOINT. Add and use a shared routine for this ... there's actually a bunch more debug entry logic that could be shared, this is just a start on that. Note that this routine fixes a bug observed in the ARM11 code, where some abort mode quirks were displayed as being an unknown debug reason; and also silences needless ARM11 chatter. Likewise with private copies of DSCR ... add one to the DPM struct. Save it as part of setting DBG_REASON_* so later patches can switch over to using that copy. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "jtag.h" to <jtag/jtag.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "jtag.h" the following form should be used. #include <jtag/jtag.h> The exception is from .c files in the same directory.
2009-12-02ARM DPM: tweak initializationDavid Brownell1-13/+12
Move the initial breakpoint/watchpoint disable calls to arm_dpm_initialize(), and start using that routine. This split helps with arm11 support.
2009-12-02ARMv7a/Cortex-A8: report watchpoint trigger insnDavid Brownell1-0/+17
Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-01ARM: core DPM support for watchpointsDavid Brownell1-2/+242
This is a NOP unless the underlying core exposes two new methods, and neither of the two cores using this (ARM11xx, Cortex-A8) do so yet. This patch only updates those cores so they pass a flag saying whether or not to update breakpoint and watchpoint status before resuming; and removing some now-needless anti-segfault code from ARM11. Cortex-A8 didn't have that code ... yes, it segfaulted when setting watchpoints. NOTE: this uses a slightly different strategy for setting/clearing breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone unless it's *got* to change something, to speed halt/resume cycles (including single stepping). ALSO NOTE: this under-delivers for Cortex-A8, where regions with size up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can also handle (size 1/2/4 bytes). Should get fixed later. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-01ARM: implement mrc()/mcr() as DPM opsDavid Brownell1-0/+59
Instead of having separate ARM11 and Cortex-A8 implementations of this code, have one shared implementation which just builds on the existing "run instruction via R0" support. This enables followup patches to remove that now-unused code from those two drivers. (Patches to move the "mrc" and "mcr" code into "struct arm" are due too ... MIPS and other cores do not support those ARM-specific concepts.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24Cortex-A8: implement DPMDavid Brownell1-9/+4
This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24ARM: new DPM interfaceDavid Brownell1-0/+529
First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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