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2025-03-15configure.ac: show the JTAG DPI and VPI adapters in the config summaryR. Diez1-23/+12
Also enable these adapters by default (auto). Change-Id: Icbbcd470eaf1d1bfb33900885776c1dbd0cccb5f Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8758 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15rtos/linux: fix name overwrite in `linux_thread_extra_info()`Evgeniy Naydanov1-17/+7
commit 908ee4dc9641bd3df2eb00264575501867da539d ("build: remove clang unused variable assignment warnings") introduced an error: ``` - tmp_str_ptr += sprintf(tmp_str_ptr, "%s", name); + sprintf(tmp_str_ptr, "%s", name); sprintf(tmp_str_ptr, "%s", temp->name); ``` This results in `name` being overwritten by `temp->name`. Fix this, adding OOM handling along the way. Change-Id: Id41f73247c3f7e6194d7c92187ad3163a9ea6c89 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8761 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15target/arm_adiv5: print DAP name if not foundMarc Schink1-1/+3
If a DAP is not found, include its name in the error message. Change-Id: Icffc52894a1c5573f938b1f3e3b53441167f085e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8636 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15tcl/board: Add TI AM261 launchpad configShivasharan Nagalikar1-0/+25
Add basic connection details with AM261 Launchpad. For further details, see https://www.ti.com/tool/LP-AM261 Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Change-Id: Ibf1270a8e470cc6ab5846dc3da64e451a8a769fd Reviewed-on: https://review.openocd.org/c/openocd/+/8793 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Nishanth Menon <nm@ti.com>
2025-03-15tcl/target/ti_k3: Add support for AM261Shivasharan Nagalikar1-0/+7
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is the reduced number of R5F cores which is now dropped down to 2, and the DIE ID is different from AM263p, but all other definitions are compatible, so reuse the definition. [1] https://www.ti.com/product/AM2612 Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393 Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8792 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: jenkins
2025-03-15tcl/board: Add TI AM263P launchpad configShivasharan Nagalikar1-0/+25
Add basic connection details with AM263P Launchpad For further details, see: https://www.ti.com/tool/LP-AM263P Change-Id: I7232a0b9337583eab499bc72929bd059624b4ff1 Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8771 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: jenkins
2025-03-15tcl/target/ti_k3: Add support for AM263PShivasharan Nagalikar1-0/+7
AM263P[1] adds additional features to AM263 SoC. [2] provides a detailed list of differences, however, the key difference from processor usage perspective is the increased SRAM and Remote L2(RL2) Cache for improved performance of R5F. To differentiate the DIE ID is different, however rest of the processor description remain compatible to AM263, hence reuse the definition. [1] https://www.ti.com/product/AM263P4 [2] https://www.ti.com/lit/pdf/spradb3 Change-Id: If47935caf1f995d7e606547e0d6545c39544678a Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8770 Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15tcl/target/ti_k3: Add support for system reset using powerAPShivasharan Nagalikar1-0/+15
TI K3 Debug systems have a Power Access Port (Power-AP) which allows for functionality such as reset via debugger that using the SPREC register. SoCs/Boards that do not have support for SRST or TRST can make use of this to force a system reset via debug access. Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0 Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8769 Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15tcl/board: Add TI am62levm configNishanth Menon1-0/+25
Add basic connection details with AM62l SK/EVM For further details, see: https://www.ti.com/tool/TMDS62LEVM Change-Id: Ic957a904dfe01951396f9767479884f2a121b181 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8799 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-15tcl/target/ti_k3: Add AM62L SoCNishanth Menon1-0/+14
Add support for the TI K3 family AM62L SoC. For further details, see https://www.ti.com/lit/pdf/sprujb4 Change-Id: I31e4e89507a1cd70a8c8c3242dd0a9dd7d0f2a06 Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8798 Tested-by: jenkins Reviewed-by: Bryan Brattlof <bryanbrattlof@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-14target/riscv: only restore mstatus.*ie bits in riscv_interrupts_restoreSamuel Obuch2-44/+27
When value of mstatus CSR changes while stepping with "set_maskisr steponly", OpenOCD should not write back the old value to mstatus when reenabling interrupts. Signed-off-by: Samuel Obuch <samuel.obuch@espressif.com>
2025-03-14target/riscv: avoid `config` modification on `jim_getopt_obj()` failureEvgeniy Naydanov1-1/+4
Currently, `jim_getopt_obj()` only fails if `goi->argc` is zero, Link: https://github.com/riscv-collab/riscv-openocd/blob/41a225460c3b9a6c1f61a0777f101ff009f56007/src/helper/jim-nvp.c#L174-L185 so the check at the start of `jim_configure_ebreak()` Link: https://github.com/riscv-collab/riscv-openocd/blob/41a225460c3b9a6c1f61a0777f101ff009f56007/src/target/riscv/riscv.c#L526-L530 guarantees that the call will succeed. However, the modification makes the code more robust and future-proof. Change-Id: Ic8c2e057a285bf679d26e21bda138a1d2ae5d5ce Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-03-14riscv-011: Don't trigger semihosting before the target is examinedJan Matyas1-2/+10
In riscv-011 target, the handle_halt() function, and thus also riscv_semihosting(), can get called from within examine() before the examination is actually complete! The chain of the function calls is: - examine() -> riscv011_poll() -> poll_target() -> handle_halt() -> riscv_semihosting() If the target is already halted due to a breakpoint (dcsr.cause = SWBP) at the time OpenOCD connects to it, semihosting will be attempted before completing the examination, and the examination will fail. This issue was observed on HiFive1 Rev A01. Hot-fix this by making shure that semihosting is not attempted before the target gets successfully examined. Change-Id: Iccfa0da35d47a430d8674131ebd2eb8e5e2922c0 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-03-13Merge pull request #1229 from ↵Evgeniy Naydanov1-1/+4
JanMatCodasip/jm-codasip/snapshot-action-in-main-branch-only CI: Run the "snapshot" action only on the main branch
2025-03-10Merge pull request #1238 from en-sc/en-sc/abits-zeroEvgeniy Naydanov1-0/+5
src/target/riscv: error out of the `examine()` in case `abits` is zero
2025-03-09target/armv8: fix 128-bit register writesDaniel Goehring1-1/+2
Assert checking was recently added to the "buf_get_u64()" procedure for the buffer size argument. For 128-bit register writes, instead of calling "buf_get_u64()" with a 128-bit argument which fails the assert check, use two 64-bit calls. Change-Id: I32ddbdb7bbe68c43f3b0a27738537391a227b08c Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8801 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-09target/target: fix RTOS thread awareness supportDaniel Goehring1-13/+10
This prior patch replaces "LOG_xxx()" with "LOG_TARGET_xxx()" to indicate which target the message belongs to. commit 7f2db80ebc16 ("rtos/hwthread: Use LOG_TARGET_xxx()") To support this change for hardware thread awareness, the target command name needs to be established before calling the "target_configure()" routine. Change-Id: I0dc70c23b84e983a2ee694fb5b9d01758f5c84a3 Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8800 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-09tcl/board: Add MSPM0 Launchpad supportNishanth Menon1-0/+14
Add basic connection details for TI's MSPM0 Launchpad series of evaluation kits: https://www.ti.com/tool/LP-MSPM0L1306 https://www.ti.com/tool/LP-MSPM0C1104 https://www.ti.com/tool/LP-MSPM0G3507 Change-Id: I33499f2d5fef846185ff6c330f9bfd0251117eb6 Co-developed-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8386 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2025-03-09tcl/target: Add support for TI MSPM0Nishanth Menon2-0/+219
Add basic support for Texas Instruments MSPM0L, C and G family of Cortex-M0 based micro-controllers. Change-Id: If2b5b1eca001f74d501ede67ec621c7497548a85 Co-developed-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8385 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: zapb <dev@zapb.de>
2025-03-09flash/nor: Add basic support for TI's MSPM0L/G familyNishanth Menon5-0/+1184
Add basic flashing support for Texas Instruments MSPM0L, C and G family of Cortex-M0 based micro-controllers. This initial basic flashing support allows for controlling protection, erase, write and read of non-main flash region. This has been tested with: * Valgrind (3.22.0): valgrind --leak-check=full --show-leak-kinds=all \ --track-origins=yes --verbose * Ubuntu clang version 20.0.0 (++20241014053649+ed77df56f272-1~exp1~20241014053827.1987) Valgrind-clean, no new Clang analyzer or sparse warnings have been introduced. Change-Id: I29b8055ea6da9c38c5b7b91bea1ec7581c5bc8ff Co-developed-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Henry Nguyen <h-nguyen8@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8384 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-09rtos/linux: handle OOM in `linux_gdb_thread_packet()`Evgeniy Naydanov1-0/+4
Return an error in case `calloc()` fails. Change-Id: Id1b758a1edbae3d71d625d1992579b99720d77d6 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8762 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de>
2025-03-09rtos/rtos: handle OOM in `rtos_thread_packet()`Evgeniy Naydanov1-0/+4
Return an error in case `calloc()` fails. Change-Id: Ibb21a62991be83be8b219887953ccf27156f8af5 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8763 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de>
2025-03-08rtt: Raise error if control block was not foundMarc Schink1-2/+2
Since RTT is not started if the control block was not found, an error must be raised instead of just informing the user. Change-Id: I2873e72f142ca572da97ee1fe91f6f1301307555 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8757 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-08target: fix wrap-around detection for read_memory/write_memoryParshintsev Anatoly1-12/+18
while at it change the order of checks for requested region sizes to get rid of potential overflow during multiplication. Change-Id: I97dac68e7024591cfd7abb70c8c62dff791298fe Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8572 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-07Merge pull request #1225 from ↵Evgeniy Naydanov7-161/+270
JanMatCodasip/jm-codasip/fix-datatypes-around-program Fix data types around opcodes.h and program.{c,h}
2025-03-07src/target/riscv: error out of the `examine()` in case `abits` is zeroEvgeniy Naydanov1-0/+5
The spec requires `abits` to be no less then 7 ( [3.1. Debug Module Interface (DMI)]): > The DMI uses between 7 and 32 address bits Commit a450a7d4966a19c48b2543810f5b8370af6383e5 ("Fix data types around batch.{c,h}") introduced a check that issues a warning if `abits` is less then 7. The reason it's a warning and not an error -- on Spike `abits` is 6. However, if the examination is to proceed when `abits` is zero, an assert in `get_dmi_scan_length()` will trigger when attempting to communicate over DMI. Link: https://github.com/JanMatCodasip/riscv-openocd/blob/a450a7d4966a19c48b2543810f5b8370af6383e5/src/target/riscv/batch.c#L25 It's impossible to communicate over DMI with `abits == 0`, so an error is returned instead of a warning in this case. Change-Id: Ice4622adccfc8304b37bc678253cc19d8ac1457e Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-03-07Merge pull request #1171 from lz-bro/handle-all-trigger-haltEvgeniy Naydanov2-0/+61
target/riscv: Fix SMP group is in inconsistent state
2025-03-07fix expose_csr for CSR with address "0"Parshintsev Anatoly1-2/+2
This change is a quick-and-dirty workaround for the problem when user wants to expose CSR with address "0" and instead of user-specified name "csr0" was used. The problem looks as follows: riscv013_reg_examine_all eventually calls init_cache_entry for all CSRs. init_cache_entry eventually results in a call to riscv_reg_gdb_regno_name. Then in case of non-standard CSRs we have the following logic: ``` // NULL when regno == 0, since names are not generated yet if (info->reg_names[regno]) return info->reg_names[regno] ... if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) { // generate names for all exposed CSRs (the function // lazy-initializes all the required names) init_custom_csr_names(target); // And here we have an error, since we overwrite the name generated // by init_custom_csr_names info->reg_names[regno] = init_reg_name_with_prefix("csr", regno - GDB_REGNO_CSR0); ... ``` The error happens because when initially this function is called with regno = 0, the first condition false, so we have to go and generate all the names.
2025-03-05Merge up to a168c634126e9e6bb95c6e68b2db5afbb099abf7 from upstreamEvgeniy Naydanov62-393/+661
There was a bunch of conflicts due to commit 297844cf46c7de5faa9de1c4a9f223b505dc3e9c ("target: Use 'bool' data type in target_{step,resume}") Resolved by updating the corresponding data types throughout the codebase. Change-Id: I9574deeda754b2843b69b4afe80b293d4b357ddd Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2025-03-04target/riscv: Fix SMP group is in inconsistent stateliangzhen2-0/+61
If the harts are just in the process of halting due to being members of the halt group, we should wait until they finish halting, so that the true halt reason can be discovered (e.g. semihosting request, and then handled correctly).
2025-03-01configure: better differentiate CMSIS-DAP versionsTomas Vanek1-5/+8
and keep them together in the configuration summary. Change-Id: I5937393590ac72f1d499457e67763686a79cadee Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8765 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-01drivers/cmsis_dap: fix misleading error selecting not compiled backendTomas Vanek1-24/+44
If one of CMSIS-DAP backends was not compiled (due to missing library or configure --disable-cmsis-dap) and Tcl config explicitly selected it, a misleading message "invalid backend argument to cmsis-dap backend <backend>" was printed. Create dummy backends in struct cmsis_dap_backend to replace a not built backend. Check for NULL open backend method to distinguish the backend is dummy. Rework 'cmsis-dap backend' command to honour dummy backend. While on it print more helpful error messages. Change-Id: I8f12aeaaecf19302032870bc232e5135c1d935e7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8760 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-01gdb_server: fix invalid freeJim Paris1-1/+2
`gdb_service_free` calls `free(gdb_port_next)`, so this needs to be an allocated string. Otherwise we trip up detectors like Android's tagged pointers. Change-Id: Ib08ea55a38af4e15c4fbae95f10db0e3684ae1af Signed-off-by: Jim Paris <jimparis@meta.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8768 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2025-03-01tcl/target: add Bouffalo Lab BL602 and BL702L chip series supportMarek Kraus4-49/+234
BL602, BL702 and BL702L series of chips are sharing same architecture, so they all need same software reset mechanism as well. Only difference (in terms of configuration needed for JTAG) are TAP ID, workarea address and size. This is addressed by creating bl602_common.cfg tcl file, which contains all those common stuff between the chips. The script is prefixed by bl602, as this was first *publicly* available chip from Bouffalo with this architecture. This patch also improves reset mechanism. Previous reset mechanism did not worked properly when slower JTAG adapter was used (it attached too late). New reset mechanism uses various methods to keep CPU in BootROM, until the JTAG adapter does not attach again after reset. Additionally, we trigger SW Reset by directly using DMI commands to write to register with system bus method, to avoid getting error about unsuccessful write. The new method works on both FT232H (8MHz JTAG clock) and unnamed CMSIS-DAP dongle (1.5MHz JTAG clock). Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae Signed-off-by: Marek Kraus <gamelaster@outlook.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8593 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-03-01target: algorithm: change reg_name to const in init_reg_param()Antonio Borneo2-3/+4
The function init_reg_param() initializes a struct where the pointer reg_name is assigned to a 'const char *'. Change the prototype of init_reg_param() to make also the reg_name parameter as 'const char *'. Change-Id: Ib999eaa5786ad24aa2a361070162c6f362784758 Reported-by: Marek Kraus <gamelaster@outlook.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8797 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Marek Kraus <gamelaster@outlook.com>
2025-02-28Clean up return type of riscv_progbuf_size() + relatedJan Matyas5-13/+11
SSIA Change-Id: I3e0b2fad84411c530f56cdbe33f3d8b4dbf81cf6 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-02-26riscv-011: Fix datatypes to correspond to opcodes.hJan Matyas1-16/+21
Callers of functions from opcodes.h need to be updated accordingly, too. Change-Id: Ic42156b2843be682bc1cf9c720b73687008a2aa6 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-02-26opcodes.h: Do not use casts in MIN_* and MAX_* macrosJan Matyas1-9/+9
This is to make it consistent with stdint.h. Change-Id: Ibba824dad431b3a1675700ad4cc15f3e39a187f7 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-02-26Fix datatypes around opcodes.h and program.{c,h}Jan Matyas6-133/+239
- Fix and clean-up datatypes in opcodes.h and program.{c,h}. Some of the changes were pointed by -Wconversion, others come from manual code inspection. - Remove commented code from opcodes.h (unused for very long time). - Add assertions to opcodes.h to check that instruction immediates (and other fields) don't exceed their range. Change-Id: I7fc7c30ac2fdb00a93158d63d1379e7f16b1d168 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2025-02-26Merge pull request #1227 from fk-sc/fk-sc/type-safe-enumEvgeniy Naydanov1-114/+177
target/riscv: make mem_access_result_t enum type safe
2025-02-22rtos: Use lower case filenamesMarc Schink6-5/+5
Change-Id: I309c7a649e33f516e28037fef2dc6e574d48c000 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8334 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-02-22jep106: update to revision JEP106BL Feb 2025Antonio Borneo1-8/+41
Update to latest available document. Change-Id: Ic7f31bf74c25aaebc5a2ecc7d5a0e516321bf862 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8766 Tested-by: jenkins
2025-02-22target: Use 'bool' data type in target_{step,resume}Marc Schink44-285/+303
While at it, adapt data types of related functions and fix some coding style issues. Change-Id: I74db9258fc17b1ee8aa446f35ae722ea7c2f67e6 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8524 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2025-02-22drivers/linuxspidev: fix compilation on Linux older than 3.15Tomas Vanek1-1/+13
Although the commit [1] which introduced SPI_IOC_WR_MODE32 is 10 years old, some hardware may enforce old Linux because the vendor didn't bother with system updates. Change-Id: I76d0b38c8646b1be329418860916b9f01b90990d Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/include/uapi/linux/spi/spidev.h?h=linux-3.15.y&id=dc64d39b54c1e9db97a6fb1ca52598c981728157 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8759 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2025-02-21flash/nor/rsl10: drop unused `rsl10_info` in `rsl10_protect_check()`Evgeniy Naydanov1-5/+0
`struct rsl10_info *chip` is only used in `rsl10_protect_check()` in an assertion triggerring `-Wunused-variable` when compiled with `DNDEBUG`. Drop it. Change-Id: Ib302aea742131479f04f32e8fe8a88a3230ae203 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8755 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-02-21target/adi_v5_swd: drop unused `swd_driver` in `swd_queue_dp_write()`Evgeniy Naydanov1-3/+0
`struct swd_driver swd` is only used in `swd_queue_dp_write()` in an assertion triggerring `-Wunused-variable` when compiled with `DNDEBUG`. Drop it. Change-Id: Id3283b9e2c36a74cda9fc4afc16da02ac4d62b69 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8754 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2025-02-21Merge pull request #1231 from en-sc/en-sc/from_upstreamEvgeniy Naydanov97-445/+3014
Merge up to 1f3f635693a1ddc85f362dc324cb49c3e7b75f27 from upstream
2025-02-21target/riscv: make mem_access_result_t enum type safeFarid Khaydari1-91/+122
Make mem_access_result_t enum type safe and fix related problems Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE Checkpatch-ignore: TRAILING_SEMICOLON Change-Id: Ie5a8c71f3a8ad803f1660114c399c5a4dd0f7414 Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-21target/riscv: set appropriate memory access result codesFarid Khaydari1-50/+82
Set appropriate memory access result codes Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE Checkpatch-ignore: TRAILING_SEMICOLON Change-Id: Ib73b5a041e5f15aef150b80fdd45f107de19d3a6 Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2025-02-21Merge pull request #1194 from fk-sc/fk-sc/merge-read-writeEvgeniy Naydanov4-178/+111
target/riscv: merged read/write functions to one access function
generated by cgit v1.1 at 2025-09-18 20:05:29 +0000