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2017-02-10aarch64: slightly simplify breakpoint set functionMatthias Welwarsky1-6/+1
Set HDE bit through helper function instead of manual mem_ap access. Change-Id: I68c157870f3f3c47a875d425ade6e975d8075424 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove bogus os_border calculationMatthias Welwarsky2-36/+5
The artificial "os_border" doesn't exist in aarch64 state and is wrong for aarch32 state as well. Remove it. Change-Id: I7c673a1404b03aa78dbd505e115fa3a93f7ca05f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: armv8 cache functions updateMatthias Welwarsky5-271/+353
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: refactor armv8 dpmMatthias Welwarsky2-510/+440
Move all DPM related functions from aarch64.c to armv8_dpm.c. Change-Id: I43404ff5db414ae898787a523d3219e5bee44889 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky7-83/+406
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: update smp halt and resume to better facilitate CTIMatthias Welwarsky2-73/+82
Set up CTI so that halt and resume requests get routed to all PEs in the SMP group. Change-Id: Ie92cfd3fe54632e5fdc049a6bf5b24b99451a8c9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling when setting/deleting soft breakpointsMatthias Welwarsky1-0/+29
Flush D-Cache before, flush D-Cache and invalidate I-Cache after modifying the breakpoint location. Change-Id: Id2e2f4f2545c062de7e27275f66857357496d4ae Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add cache handling functionsMatthias Welwarsky4-1/+153
For now only D-Cache flush (Clean&Invalidate) and I-Cache invalidate are implemented. That's enough for software breakpoints. Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: disable interrupts when stepping [WIP]Matthias Welwarsky1-0/+32
On live hardware, interrupts will happen while the core is held for stepping. The next step will most of the time execute an interrupt service instead of the next line of code, which is not what you expect. Disable interrupts through DSCR before resuming for a step, and re-enable them again after the step happened. This should be made configurable, like on cortex_a target. Change-Id: I94d8ffb58cf7579dedb66bc756b7eb6828b6e8e4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct instruction for software breakpointsMatthias Welwarsky3-3/+6
External debuggers need to use HLT, not BRK. HLT generates a halting debug event while BRK generates a debug exception for self-hosted debugging. Change-Id: I24024b83668107f73a14cc75d951134917269e5c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: report the correct reason for halting after singlestepMatthias Welwarsky2-13/+14
Don't report breakpoint as debug reason when halt is due to a single-step event. Change-Id: Ie6c3ca1e5427c73eb726a038301b6a29a47d1217 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix register listMatthias Welwarsky1-33/+33
According to gdb documentation, a register "cpsr" is expected if aarch64 features are announced. Also, the value buffer must be capable of holding a 64bit value (8 byte, not 4) Change-Id: I7aec4e84fa87eadb26797acd0d16c988b9852616 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix duplication of register cacheMatthias Welwarsky1-3/+5
Change-Id: Ib4422e39171f19eea3f0b5a86f9dccdbb7044265 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove code for AHB-AP supportMatthias Welwarsky3-181/+31
Reduce complexity of memory access functions, anyway there are no ARMv8 platforms that actually contain an AHB-AP at all. while at it, fix virt-to-phys function signatures to expect target_addr_t. Change-Id: I55a369686f42993988b6323e5a77f38de12530a9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix stepping from addressMatthias Welwarsky1-1/+1
The step command optionally carries a resume address. In this case, stepping should start not at the current PC, but at the given address. Change-Id: Id5792a3745f470cf29efa90c63d65f33d36f6b25 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove references to armv7-rMatthias Welwarsky2-19/+9
aarch64 target doesn't support the -r profile anyway. Change-Id: Iaa470ed9f95ea495ab1bafdf401f55a1ebcefddf Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix armv8_set_core_reg when destination is cpsrMatthias Welwarsky1-2/+8
When armv8_set_core_reg is used to set the value of the CPSR, also update the internal architecture state. Change-Id: I5f6a2be6fde8d91ec3352d8ba23c4aa90eb02977 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: unify armv7-a and armv8 debug entry decodingMatthias Welwarsky4-33/+21
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct A64 instructions for cache handlingMatthias Welwarsky2-11/+10
Replace A32 MCR with proper A64 MSR opcodes Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix first examinationMatthias Welwarsky1-51/+42
properly decode debug capabilities, remove superfluous register accesses. Change-Id: I2cca699b515262dd2a508d7be97826eb17b9c607 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: correct display for aarch64 stateMatthias Welwarsky1-11/+29
Aarch64 state has different PSTATE and exception level model. Correct the printout e.g. in poll command. Change-Id: I1820fd1836c7076ae0aa405fa335fd1a14a2e5b3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic constant for register countMatthias Welwarsky1-4/+3
Aarch64 has 34 registers, but use ARMV8_LAST_REG instead of raw integer constant. Change-Id: I86481899ade74f27fc90eff9f367d444c03e535e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: remove armv7-a virt-to-phys codeMatthias Welwarsky3-93/+27
Page table layout in aarch64 is very different from armv7-a layout. Remove the incorrect handling, to be replaced correct armv8 code in a later patch Change-Id: I64c728a72a24f9f4177726ccc07a02a8ca0d56ce Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: clear breakpoint value register on removalMatthias Welwarsky1-0/+27
Not only null control but also value of the breakpoint when it is removed. Change-Id: Id99c7e3644729c64e563f1fa8b0577f350be6a98 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: correct breakpoint register offsetMatthias Welwarsky1-7/+4
armv8 breakpoint register spacing is 16, not 4 as in armv7-a Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix cache identificationMatthias Welwarsky2-28/+18
Use correct instructions to access CLIDR, CSSELR and CCSIDR. Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of translation table registersMatthias Welwarsky2-11/+100
Correctly access and parse aarch64 ttbcr. Change-Id: I1b1652791a6b5200f58033925286292d838e8410 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix entry into debug stateMatthias Welwarsky2-20/+16
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this bit are ignored but we should not do them anyway - use dpmv8 function to report the reason for debug entry - WFAR is a 64bit register Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic opcodes instead of hex valuesMatthias Welwarsky1-7/+6
Use opcode definitions from armv8_opcodes.h where appropriate Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix accesses to SCTLR_ELn registerMatthias Welwarsky1-27/+142
The system control register has several instances, depending on the exception level. Make sure to access always access the correct one. Change-Id: I9e867f4dbd9625762042f20ed905064ea4e3270f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix error recovery in aarch64_dpm_prepareMatthias Welwarsky1-4/+8
Flush DTRRX with a dummy read if it's full, clear sticky errors by writing CSE bit to EDRCR register. Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: formalize use of CTI in halt and resumeMatthias Welwarsky2-57/+68
Use configured CTI base address instead of hardcoded value, if available. Use symbolic constants instead of raw hex offsets. Trim halt and resume code to what is actually necessary. Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix context and hybrid hardware breakpointsMatthias Welwarsky1-10/+17
Fix 64bit address setting Fix register spacing (16 instead of 4) Set HMC bit for all but linked context match breakpoints, where the bit is ignored anyway Change-Id: I48428f39154a6fe5fadc075ca918d1500a0bb241 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: deconflict debug register namesMatthias Welwarsky2-127/+131
CPUDBG_ -> CPUV8_DBG_ for armv8 debug registers. Change-Id: I3d24cc209309fa9bbeb5c3e6c88a572383c9360e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Implement MA mode for bulk memory reads and writesMatthias Welwarsky1-84/+165
- 64bit addresses are supported - Aarch32 state is supported Change-Id: I8c37fa166954d09195d08c6963b8017194e350f5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: make DCC read/write functions operate on struct armv8_commonMatthias Welwarsky1-30/+31
Change the signature of aarch64_(read|write)_dcc[_64] to take a "struct armv8_common *" as the context to operate on. No functional change. Change-Id: Ie501113f65ea22aff2eee173ec717f6908a63494 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky9-260/+1400
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10target: add -ctibase config option in addition to -dbgbaseMatthias Welwarsky2-1/+21
Some vendors don't fully populate the ROM table, e.g. BCM2357 (used in Raspberry Pi 3) doesn't list CTI, however it is mandatory for halting an ARMv8 core and therefore it's always present (and required), regardless of the ROM table listing it or not. Change-Id: Ia18a4f1b5b931ccd19805b188ebf737c837c6b54 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of MPIDRMatthias Welwarsky1-1/+2
read MPIDR register through correct MSR instruction. Change-Id: I7e2d00c2871191c4168b177a7a809443b0db4c82 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add symbolic definitions for armv8 opcodesMatthias Welwarsky2-0/+127
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Correct target state for hardware stepDavid Ung2-2/+12
When using hardware step for doing stepping, the existing DSCR records the event as external debug request. This will generate a SIGINT event to GDB and causes it to stop the stepping process. For aarch64, read DESR to check if the event is a hardware step and set state to DBG_REASON_SINGLESTEP. With this patch, GDB can now do source level stepping. Change-Id: I1d06f819578c74b3ac17376c67f882adddea1f52 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Enable resuming with addressDavid Ung1-9/+5
Enable resuming to an address. Change-Id: I29c7d3b56f6cbf8b3cd02c93733fc96f45000af3 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add instruction stepping support using hardware steppierre Kuo2-36/+14
Use AARCH64's hardware step event to do stepping. Change-Id: I2d029ceeadd381913d0c3355c8787b11dacff7f7 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Enable halting debug mode on breakpoint setDavid Ung1-0/+12
Ensure that we allow halting debug mode after setting breakpoint Change-Id: I6f0d7a4a4775a93c133fb1ec31dfe3324d9f7395 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add hardware breakpoint supportpierre Kuo1-20/+19
Enable the use of hardware breakpoint on AARCH64. Change-Id: I59caaa6d92ac60278af8938625b1790a1787372f Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung9-9/+3701
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add 64bit register handling.David Ung2-86/+257
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add new state ARM_STATE_AARCH64David Ung3-0/+8
Add new enum ARM_STATE_AARCH64 to the list of possible states. Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10server: Allow 64 address to be send over GBD serverDavid Ung1-13/+13
Accept 64 bit addresses from GDB read memory packet. Also allow breakpoint/stepping addresses to take 64bit values. Change-Id: I9bf7b44affe24839cf30897c55ad17fdd29edf14 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang68-546/+728
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
generated by cgit v1.1 at 2024-10-21 10:47:57 +0000