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2023-11-06Merge commit '05ee88915520d1dd82da94a016a9374a1f3a8129' into from_upstreamTim Newsome152-713/+9246
Conflicts: src/jtag/drivers/xds110.c src/target/riscv/riscv.c src/target/riscv/riscv_semihosting.c tcl/target/esp_common.cfg Change-Id: If0c02817df03b7fd700cc84b4da2c02d36737d28
2023-11-03Merge pull request #896 from AnastasiyaChernikova/ac-sc2Tim Newsome5-482/+298
target/riscv: Adding register tables to make register names consiste
2023-11-03Merge pull request #947 from riscv/from_upstreamTim Newsome91-768/+3926
From upstream
2023-11-02Merge pull request #945 from kr-sc/kr-sc/fix-mmu-access-upstreamTim Newsome1-19/+29
target/riscv: Fix memory access when MMU is enabled and address couldn't be translated
2023-11-02target/riscv: Adding register tables to make register names consistentAnastasiya Chernikova5-482/+298
Added the ability to enter dimensionless registers Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86 Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-11-01Merge pull request #949 from riscv/remove_esp32c_targets_from_docTim Newsome1-2/+0
Remove mention of esp32c2, esp32c3 from doc
2023-10-31Merge pull request #950 from riscv/remove_set_scratch_ram_from_docTim Newsome1-5/+0
Remove mention of "riscv set_scratch_ram" from doc
2023-10-31Merge pull request #948 from riscv/uninitialized_dumpTim Newsome1-1/+6
target/riscv: Prevent dump_field() reading uninitialized memory
2023-10-31Removed mention of "riscv set_scratch_ram" from docJan Matyas1-5/+0
This command no longer exists, was removed in: https://github.com/riscv/riscv-openocd/commit/ead2a595b8491ed48ce2ced81d2935dc8a4c4973 Remove it from the doc as well. Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-31Remove mention of esp32c2, esp32c3 from docJan Matyas1-2/+0
Targets "esp32c2" and "esp32c3" should not be mentioned in the doc under "target types" because these are not standalone OpenOCD targets. They are merely a set of .cfg files which use the generic "riscv" target. Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-30target/riscv: Prevent dump_field() reading uninitialized memoryTim Newsome1-1/+6
Change-Id: I9ef8f2c2e9a824aa6595e8f20682c968ae5aed72 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-30Merge pull request #943 from riscv/remove_deprecated_gd32vf103_flashTim Newsome3-54/+0
Removed deprecated gd32vf103_flash
2023-10-30target/riscv: Fix memory access when MMU is enabled and address couldn't be ↵Kirill Radkin1-19/+29
translated Now: 1) If mmu is disabled, virt2phys succeeded and returns physical address 2) If mmu is enbaled, but translation fails, read/write_memory fails Change-Id: I312309c660239014b3278cb77cadc5618de8e4de Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-30Removed deprecated gd32vf103_flashJan Matyas3-54/+0
Removing flash driver "gd32vf103_flash". This driver has been deprecated since June-1-2022, and was scheduled for removal in June 2023. Change-Id: Ib6f4dcba11e91a095b3a20eedd864589084b7fa9 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-27Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstreamTim Newsome91-768/+3926
Conflicts: HACKING src/target/riscv/riscv-013.c Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-10-27Merge pull request #942 from riscv/from_upstreamTim Newsome123-689/+6576
From upstream
2023-10-26Merge pull request #944 from riscv/remove_extra_kept_aliveTim Newsome1-1/+0
Remove an extra call to kept_alive()
2023-10-26Merge pull request #946 from en-sc/en-sc/update-debug-printersTim Newsome1-4/+6
target/riscv: update debug register printers
2023-10-25target/riscv: update debug register printersEvgeniy Naydanov1-4/+6
Change-Id: I069bbe069a3aaa7fd3a4f6eccde40f813db33cc9 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-10-25Remove an extra call to kept_alive()Jan Matyas1-1/+0
This incorrect extra call has been removed in upstream code already in March 2022, see https://review.openocd.org/c/openocd/+/6836 . Remove it from riscv-openocd as well. Change-Id: Ie341f5578c8bfdc518adf1e4bc134919ab76f803 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-10-24Merge pull request #941 from kr-sc/kr-sc/fix-hgatp-mode-upstreamTim Newsome1-1/+1
hgatp_mode in riscv_virt2phys_v defined by vsatp value
2023-10-23Fix build.Tim Newsome1-0/+1
Change-Id: I20bd0356c63745423e23aec71f272fe2e32db88e Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-23Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstreamTim Newsome123-689/+6575
Conflicts: src/flash/nor/drivers.c src/target/riscv/riscv.c Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
2023-10-23Merge pull request #940 from ↵Tim Newsome1-8/+6
riscv/revert-908-disable-soft-bp-size-2-non-compressed Revert "target/riscv: Reject size 2 soft breakpoints when C extension not supported"
2023-10-23hgatp_mode in riscv_virt2phys_v defined by vsatp valueKirill Radkin1-1/+1
Replace `vsatp` with `hgatp` (how it should be) Change-Id: Ie548467b06d1fb266ccc56cbec1aff8d9f435973
2023-10-23Merge pull request #935 from riscv/from_upstreamTim Newsome33-1066/+857
Merge down up to 0384fe5 from upstream.
2023-10-20Revert "target/riscv: Reject size 2 soft breakpoints when C extension not ↵Tim Newsome1-8/+6
supported"
2023-10-18Merge pull request #937 from riscv/cross-buildTim Newsome1-1/+1
contrib: Match upstream.
2023-10-18Merge pull request #938 from riscv/stm32lxTim Newsome1-2/+3
flash/stm32lx: Revert to upstream version.
2023-10-18Merge pull request #936 from riscv/whitespaceTim Newsome1-1/+1
Remove end-of-line whitespace.
2023-10-17flash/stm32lx: Revert to upstream version.Tim Newsome1-2/+3
Reintroduce checkpatch problem, because now we can handle them better. Change-Id: Ib81b9910433ae1a240630b898edb19da8d2d5d83 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-17contrib: Match upstream.Tim Newsome1-1/+1
Upstream has a checkpatch failure here. I had fixed it because I didn't know how else to properly get around it back then. Reintroduce the problem. Now this file is identical to upstream. Change-Id: Ic03b6bb42945ddbcfd2fe12c0cab5b05eda1a50c Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-17Merge pull request #934 from kr-sc/kr-sc/revert-commitTim Newsome2-20/+14
Revert "target: Update messages connected with `examine`"
2023-10-17Revert "target: Update messages connected with `examine`"Kirill Radkin2-20/+14
This reverts commit a3db93b1cea56614baf04f8e88742049da9f2f1e. Reason for revert: https://github.com/riscv/riscv-openocd/pull/931#issuecomment-1761550506
2023-10-16Remove end-of-line whitespace.Tim Newsome1-1/+1
Change-Id: I0deffafe954abaaa4c593896a2d781c2fa00eef2 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-16Copy snapshot.yml from upstreamTim Newsome1-4/+1
At change 0384fe5. Change-Id: I1081e09f1014c5d240988fc25feba04fc2bb21ef Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-16Merge commit '0384fe5d596f42388f8b84d42959d899f29388ab' into from_upstreamTim Newsome33-1062/+856
Conflicts: .github/workflows/snapshot.yml src/rtos/FreeRTOS.c Change-Id: I4c9ff887b69140e0f61cb3f75a2f2c1a12071320
2023-10-16Merge pull request #929 from aap-sc/riscvTim Newsome4-38/+88
do not assume DTM version unless dtmcontrol is read successfully
2023-10-16Merge pull request #927 from riscv/unavailable_resumeTim Newsome1-1/+19
server/gdb_server: Fake resuming unavailable targets.
2023-10-13server/gdb_server: Fake resuming unavailable targets.Tim Newsome1-1/+19
When asked to resume an unavailable target, resume any available targets and report success. Change-Id: Ieafc63794c1a6eba8948c0f9ce84fa74f9765041 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-11Merge pull request #926 from riscv/unavailable_eventsTim Newsome1-2/+20
server/gdb_server: Handle events if first target is unavailable
2023-10-11Merge pull request #925 from riscv/unavailable_regTim Newsome2-57/+64
gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not imple…
2023-10-11Merge pull request #917 from kr-sc/kr-sc/disable-triggers-optionTim Newsome3-44/+173
provide riscv-specific controls to disable triggers from being used for watchpoints
2023-10-11Merge pull request #931 from kr-sc/kr-sc/update-examine-messagesTim Newsome2-14/+20
target: Update messages connected with `examine`
2023-10-10server/gdb_server: Handle events if first target is unavailableTim Newsome1-2/+20
When a target in an SMP group is unavailable, the gdb layer might get an event for a different target in that SMP group, but not one that is the primary target for that gdb connection. So propagate events if they're for any of the targets in the SMP group, not just if it's for the first one in that group. Change-Id: I8d6738762acc7c0aef96f56ce2cb7f2eeb233b33 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10rtos: Refactor rtos_get_gdb_reg()Tim Newsome1-56/+58
Exit early if conditions aren't satisfied, instead of putting the core code inside an if(). Also return ERROR_FAIL if conditions are satisfied but no matching registers were found. Change-Id: I77aa63d9f707bc38d1a71899275ba603914b52c9 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-10-10Merge pull request #920 from lz-bro/dcsr-cachableTim Newsome2-34/+28
target/riscv: use cacheable read/write function to handle DCSR
2023-10-07target/riscv: use cacheable read/write function to handle DCSRliangzhen2-34/+28
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-06do not assume DTM version unless dtmcontrol is read successfullyParshintsev Anatoly4-38/+88
Change-Id: I5f2003b7ac5ce87af6ca9a4fcb46140682a8cfdf Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-10-05Merge pull request #924 from riscv/unavailable_stepTim Newsome1-3/+9
server/gdb_server: Step unavailable targets.
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