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2023-10-05Merge pull request #915 from riscv/dpc_printTim Newsome1-1/+0
target/riscv: Remove duplicate read PC message
2023-10-05Merge pull request #930 from riscv/upstream_diffsTim Newsome2-80/+65
Copy tool files from upstream.
2023-10-03target: Update messages connected with `examine`Kirill Radkin2-14/+20
Move `examine_attempted` flag to target struct to make it target specific. `Info` messages for retry and `Error` messages for failure added. Change-Id: Id2fbe7dc68d746c936c8412289d0d149fbd80d71 Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-10-02provide riscv-specific controls to disable triggers from beeing used for ↵Kirill Radkin3-44/+173
watchpoints Add a new riscv specific commands to disable triggers Change-Id: Ic1842085aa66851c740e0abcbfbe0adbe930920e Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-29Copy tool files from upstream.Tim Newsome2-80/+65
Copy .travis.yml and tools/scripts/checkpatch.pl from upstream ee31f1578a333a75737bc5b183cd4ae98cdaf798. Addresses #913. Change-Id: I69ad6b734ebf2cf7110010aa0481b6676124610e Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-29Merge pull request #921 from lz-bro/repeat_read-fixTim Newsome1-5/+7
target/riscv: support riscv repeat_read by sysbus access
2023-09-29Merge pull request #918 from kr-sc/kr-sc/allow-to-query-status-dcsr-ebreakTim Newsome5-38/+64
openocd does not allow to query status of dcsr.ebreak{u,s,m}
2023-09-28Merge pull request #892 from en-sc/en-sc/register-printingTim Newsome7-242/+4747
target/riscv: define register printers
2023-09-27gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implementedTim Newsome2-3/+8
If it fails, then pass that failure on. If it's simply not implemented, then we can fall through and try target_get_gdb_reg_list_noread(). This difference matters when the target representing the current hwthread is unavailable, but the target that is linked to the gdb connection is available. In that case we want the operation to return an error to gdb, instead of reading the register from the target that is available. Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-27server/gdb_server: Step unavailable targets.Tim Newsome1-3/+9
When gdb requests to step an unavailable target, report success. When the target becomes available, the step can complete. Change-Id: I969ab56139f72a757552928d59edf6eabd598fa4 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-26openocd does not allow to query status of dcsr.ebreak{u,s,m}Kirill Radkin5-38/+64
Extend riscv set_ebreak* commands. Now it can be called without args to print current value. riscv_ebreak* flags are moved to riscv_info struct. Change-Id: Ib46e6b6dfc0117599c7f6715c7aaf113e63bd7dc Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-09-25target/riscv: Remove duplicate `read PC` messageTim Newsome1-1/+0
Change-Id: Ie085758e3cf193f2671ea53fb82fd401d0c52d86 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-25Merge pull request #913 from riscv/from_upstreamTim Newsome66-1127/+2433
From upstream
2023-09-22target/riscv: define register printersEvgeniy Naydanov7-242/+4747
`riscv_debug_reg_to_s()` can be used to decode register value. If the pointer to buffer is `NULL` it does not print anything, just returns the length of the string. The format is: `<register_value> { <field_name>=<field_value_name or field_value>, ..., }` e.g: `0x400382 { version=2, ... ndmresetpending=false, }` `0x321009 { regno=0x1009, ... cmdtype=0, }` Change-Id: I63733d8d36385d89ca15de1a43139134bc488c4f Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-21target/riscv: support riscv repeat_read by sysbus accessliangzhen1-5/+7
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-09-14Merge pull request #916 from riscv/getreg_assertTim Newsome1-2/+5
target/riscv: Don't assert in riscv013_get_register()
2023-09-13target/riscv: Don't assert in riscv013_get_register()Tim Newsome1-2/+5
When the target isn't halted, simply return an error. This used to be purely internal code so an assert was appropriate. Now after some refactoring and with unavailable harts you could get here when the hart is unavailable. In that case the right thing is simply to return an error message. Change-Id: I49d26a11fe7565c645fd2480e89a2c35ea9b1688 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-12target/xtensa: Fix build warning.Tim Newsome1-1/+1
Change-Id: I9ee69807bec729480dd94da874fe1771d8f06078 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-12Merge commit 'ee31f1578a333a75737bc5b183cd4ae98cdaf798' into from_upstreamTim Newsome66-1127/+2433
Conflicts: Makefile.am jimtcl src/helper/Makefile.am src/rtos/rtos.c src/rtos/rtos.h src/rtos/rtos_standard_stackings.c Change-Id: I00c98d20089558744988184370a8cb7f95f03329
2023-09-11Merge pull request #911 from riscv/from_upstreamTim Newsome23-269/+379
From upstream
2023-09-08Merge pull request #912 from MarekVCodasip/make-unknown-semihosting-errorTim Newsome1-3/+3
target/riscv_semihosting: Make the unknown operation number an error
2023-09-08Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggersTim Newsome2-75/+125
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-07Merge pull request #908 from MarekVCodasip/disable-soft-bp-size-2-non-compressedTim Newsome1-6/+8
target/riscv: Reject size 2 soft breakpoints when C extension not supported
2023-09-07target/riscv: cleanup riscv_enumerate_triggers()Evgeniy Naydanov2-75/+125
1. Propagate error codes. 2. Disable leftover triggers in case `tinfo` is supported. Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07target/riscv_semihosting: Make the unknown operation number an errorMarek Vrbka1-3/+3
Previously, an unknown semihosting operation number was logged as debug. This patch changes it and few other places to be logged as error instead. Change-Id: I83cae5ca1e3daed440f92b08bd372bfffbbad63c Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04target/riscv: Reject size 2 soft breakpoints when C extension not supportedMarek Vrbka1-6/+8
This patch disables software breakpoints of size 2 for targets which don't support compressed instructions. Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5 Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-30Merge pull request #906 from MarekVCodasip/zero-no-cacheTim Newsome1-0/+3
target/riscv: Don't write to zero.
2023-08-29Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstreamTim Newsome23-269/+379
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-29Merge pull request #900 from aap-sc/aap-sc/simplify_state_managmentTim Newsome1-25/+16
riscv: simplify state management during examine
2023-08-26target/cortex_m: check core implementor fieldKarl Palsson7-38/+52
Presently, we only look at the Part Number field of the CPUID, and completely ignore the Implmentor field, simply assuming it to be ARM. Parts have since been found, with different implementors, that use overlapping part numbers, causing detection to fail. Expand the "part number" field to be a full implementor+part number, excluding the revision/patch fields, to make checking more reliable. Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522 Signed-off-by: Karl Palsson <karlp@tweak.au> Reviewed-on: https://review.openocd.org/c/openocd/+/7845 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-08-26efm32: drop unnecessary and incomplete checksKarl Palsson1-12/+0
There's really no reason to try and add an extra layer of cpu verification here. Change-Id: If8c4aa03754607be6c089f514ae300b09b067ffa Signed-off-by: Karl Palsson <karlp@tweak.au> Reviewed-on: https://review.openocd.org/c/openocd/+/7844 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-25target/riscv: Don't write to zero.Marek Vrbka1-0/+3
During a previous patch, the ignoring of writes to register zero was deleted. This patch restores it to the original. Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-23Merge pull request #904 from kr-sc/kr-sc/support-sv57Tim Newsome2-2/+37
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_runningTim Newsome1-6/+6
fix crash when we try to read vector register on a running target
2023-08-18Merge pull request #903 from wxjstz/riscvTim Newsome1-8/+28
target/riscv: fix execute_fence
2023-08-18riscv: simplify state management during examineParshintsev Anatoly1-25/+16
This also fixes a bug when, after `examine` completion, the target still has `unknown` status. To reproduce this one spike, it is enough to do the following: --- // make sure spike harts are halted openocd ... -c init -c 'echo "[targets]"' --- this behavior is quite dangerous and leads to segfaults in some cases Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18 Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18fix crash when we try to read vector register on a running targetParshintsev Anatoly1-6/+6
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2 Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-17Merge pull request #901 from aap-sc/aap-sc/refactor_reg_rw_progbufTim Newsome1-72/+147
[riscv] refactor functions that register read/write via progbuf
2023-08-17target/riscv: fix execute_fenceXiang W1-8/+28
This patch improves the following issues: 1. Makes it compatible with targets with progbufsize == 1. 2. Although exceptions don’t update any registers, but do end execution of the progbuf. This will make fence rw, rw impossible to execute. Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6 Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-15[riscv] refactor functions that register read/write via progbufParshintsev Anatoly1-72/+147
The motivation for this refactor is to fixup error handling for some corner cases. These functions attempt to cache S0 register and only then perform a bunch of extra checks to figure out if the requested register is valid one in this context. The problem is that there are few corner cases when _*progbuf functions could receive a GPR as an input. For example, an abstract read could fail (for whatever reason) leading to infinite recursion: ```` save S0 -> read S0 -> save S0 -> read S0 -> ... ``` The case described above could be fixed by adding extra sanitity checks, however I decided to make these functions more modular since I find self-contained functions easier to read. Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-14Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlblTim Newsome1-2/+4
target/riscv: improve error handling in trigger setup
2023-08-14Merge pull request #897 from aap-sc/aap-sc/wp_data_not_implementedTim Newsome1-0/+8
add diagnostics for non-implemented data watchpoints
2023-08-14target/riscv: Add support for Sv57 translation mode (including second-stage ↵Kirill Radkin2-2/+37
translations) Also fix Sv48x4 translation mode
2023-08-12flash/nor/spi: Improve erase performance on zd25q16Nikolay Dimitrov1-1/+1
Use blocks (64 KiB) instead of sectors (4 KiB) when erasing the zd25Q16 SPI flash memory (thanks to Tomas Vanek!) Change-Id: I969a69ad35f51b84eb3e11b93f0d79db3e98613a Signed-off-by: Nikolay Dimitrov <nikolay.dimitrov@retrohub.org> Reviewed-on: https://review.openocd.org/c/openocd/+/7850 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-08-12flash/nor/spi: add zetta zd25q16Nikolay Dimitrov1-0/+1
* Zetta 16 Mbit (2 MiB) SPI flash * Tested on Olimex RP2040-PICO30 and Neo6502 boards Change-Id: I02224dd7a72a9b72f01b31edbd958daa23f28956 Signed-off-by: Nikolay Dimitrov <nikolay.dimitrov@retrohub.org> Reviewed-on: https://review.openocd.org/c/openocd/+/7849 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-08-12pld: allow calling of configuration functions before 'init'Daniel Anselmi2-3/+3
Change-Id: I7c475fbbf8c13ae227e3393f01528eb180e9de51 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7835 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-12pld: fix sparser warningsDaniel Anselmi2-2/+2
Change-Id: I31c5b19cd93ac41b026f824337488c9aa9b12439 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7828 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-12target/aarch64: add missing aarch64_poll() callsDaniel Goehring1-0/+9
Add missing aarch64_poll() calls to ensure the event TARGET_EVENT_HALTED is called when necessary. This is needed with the poller update introduced in commit 95603fae18f8 ("openocd: revert workarounds for 'expr' syntax change") Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Change-Id: I6e91f1b6bc1f0d16e6f0eb76fc67d20111e3afd2 Reviewed-on: https://review.openocd.org/c/openocd/+/7737 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-12tcl: add configuration files for the ARC HSDK-4xD boardArtemiy Volkov2-0/+69
This commit provides startup files for the Synopsys DesignWare ARC HSDK-4xD board. These have been adapted from the corresponding snps_hsdk.cfg files, the only functional change being the JTAG IDs for the new board's CPU cores. Change-Id: I19a0cd13bc09de90cfe2a7cccf1239e459fd8077 Signed-off-by: Artemiy Volkov <artemiy@synopsys.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7829 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Evgeniy Didin <didin@synopsys.com>
2023-08-12tcl/interface/ftdi: support for SIPEED RV-Debuggergudvinr1-0/+13
BL702-based JTAG debugger that emulates FT2232D device Change-Id: Iefbf03645e6d8d154f4b1cad3385b8bc09da37dd Signed-off-by: gudvinr <gudvinr@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7830 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
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