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2018-06-15src/flash/tms470: remove testing of sectors[].is_erased stateTomas Vanek1-24/+12
The erase check routine checked sectors only if is_erased != 1 Check sector unconditionally. While on it fix clang static analyzer warnings. Change-Id: I9988615fd8530c55a9b0c54b1900f89b550345e9 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4401 Tested-by: jenkins
2018-06-15flash/nor/nrf5: remove is_erased setting and autoerase before writeTomas Vanek1-53/+5
Cached flash erase state in sectors[].is_erased is not reliable as running target can change the flash. Autoerase was issued before flash write on condition is_erased != 1 Remove autoerase completely as it is a quite non-standard feature. Change-Id: I19bef459e6afdc4c5fcaa2ccd194cf05be8a42b6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4400 Tested-by: jenkins
2018-06-15flash/nor: Add support for TI CC26xx/CC13xx flashEdward Fewell25-14/+7676
Added cc26xx flash driver to support the TI CC26xx and CC13xx microcontrollers. Driver is capable of determining which MCU is connected and configures itself accordingly. Added config files for four specific variants: CC26x0, CC13x0, CC26x2, and CC13x2. Note that the flash loader code is based on the sources used to support flash in Code Composer Studio and Uniflash from TI. Removed cc26xx.cfg file made obsolete by this patch. Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4358 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
2018-06-06psoc5lp: Add NV Latch flash driverAndreas Färber4-0/+344
Erasing is not supported by the hardware, it can be written directly. Tested on CY8CKIT-059, except modifying-write. Change-Id: I6e920ed930dcd5c7f0b10c5b1b4791a828d9080a Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3434 Tested-by: jenkins
2018-06-06flash/nor/psoc5lp: fix bad commit 2d5f2ede55150235352773a976166c3ab68297bcTomas Vanek1-27/+39
Change #3432 was merged into git master without adapting it to #4297 "prepare infrastructure for multi-block blank check". This is a fast fix of PSoC5LP specific blank check. Not tested on real PSoC5LP device. Change-Id: I7dc13ee7bd1f07b2bfe5a93a5030c0c482d30f00 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4557 Tested-by: jenkins
2018-06-06drivers: xds110: Remove unnecessary and deprecated libusb function.Edward Fewell1-6/+2
libusb-1.0.22 has deprecated the libusb_set_debug function. This function was present in the XDS110 driver as an artifact left over from early debugging. It isn't required because logging is disabled by default. Removing it to simplify the code and no longer need to have libusb version specific #if's in the code. Change-Id: I9c3f16c039da3f3fad9c4a1169978b0d85a1b45c Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4553 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2018-06-06psoc5lp: Add EEPROM flash driverAndreas Färber4-0/+285
Tested on CY8CKIT-059. Change-Id: Ib02262e8eebf0df3d29492b8a7daa65b262da580 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3433 Tested-by: jenkins
2018-06-06flash/nor: Add PSoC 5LP flash driverAndreas Färber6-2/+1036
Always probe for ECC mode and display ECC sectors if disabled. Non-ECC write is implemented as zeroing the ECC/config bytes. Erasing ECC sectors is ignored, erase-checking takes them into account. Tested with CY8CKIT-059 (CY8C5888), except ECC mode. Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3432 Tested-by: jenkins
2018-06-06flash/nor: Add support for TI CC3220SF internal flashEdward Fewell13-54/+804
Added cc3220sf flash driver to support the TI CC3220SF microcontrollers. Implemented flash driver to support the internal flash of the CC3220SF. The implementation does not support the serial flash of the CC32xx family that requires connection over UART, and not via JTAG/SWD debug. Added config files for both CC32xx devices (no flash) and CC3220SF (with flash). Updated to implement comments from code review. Additional updates to handle remaining comments from review. Additional updates per review. Added code to only request aligned writes and full 32-bit words down to flash helper algorithm. Updated for recent changes in OpenOCD flash code. Removed cc32xx.cfg file made obsolete by this patch. Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-06Fix Semihosting FileIO for targets using vcont packetOmair Javaid1-0/+2
This patch fixes a bug where target fails to resume after completing GDB FileIO. We need to update target last run control information to decide resumption. This was not being done for vcont packets. Change-Id: I44bea31720f8b877dba97d77a202303d546ea5bd Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4539 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-06target/target.c: free semihosting memberLiviu Ionescu1-0/+3
When destroying the target, if the semihosting pointer is set, free it. Change-Id: I07d34918bb3fddab1eee11219dd66f4842708ec1 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4552 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-05Fix libusb-1.0.22 deprecated libusb_set_debug with libusb_set_optionKhem Raj1-1/+4
libusb_set_debug is deprecated in libusb >= 1.0.22 therefore replace with equivalent libusb_set_option() API Change-Id: Ic0287a1bc0ccc90afe8e4c688085f0b25a7fb004 Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-on: http://openocd.zylin.com/4540 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-05target/cortex_m: constify some variablesChristopher Head1-4/+4
Change-Id: I1f3fddd89597333fc1bb9535c0cd76ca3e008324 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4503 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-05flash/nor/virtual: copy missing fields from master flash_bank structureBohdan Tymkiv1-0/+5
Change-Id: I4ac71ad4b46ed613192310d85eb385b727649a11 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4505 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2018-06-05flash/nor/core: fix double-free crash with 'virtual' flash banksBohdan Tymkiv1-2/+10
flash_bank structure of 'virtual' flash driver is a full copy of the master flash_bank structure including bank->sectors and bank->prot_blocks pointers. These pointers point to memory locations allocated by the master driver and thus master driver is responsible for deallocating them. Do not free bank->sectors and bank->prot_blocks of 'virtual' driver since they were already released by master flash driver. Change-Id: I01f373d4adb3fc79e2724964926b9276442c5c52 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4504 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-04breakpoints: simplify the test to find a breakpointAntonio Borneo1-5/+2
The test is overly complicated and unreadable. Simplify it while keeping the exact same behaviour. Change-Id: I6b22291ca454e1eddeeab4024d3983dc4c603d3a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4512 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-04target: fix syntax in help messageAntonio Borneo1-3/+1
The name of the command is already printed before the string in ->usage, thus it appears twice. E.g. > help examine stm32f4x.cpu arp_examine arp_examine ['allow-defer'] used internally for reset processing stm32f4x.cpu examine_deferred examine_deferred used internally for reset processing stm32f4x.cpu was_examined was_examined used internally for reset processing Remove the command name from the string in ->usage. Change-Id: If3b1368ffff8a94eb629ae3679e2e5f2f11ae92e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4536 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-04target: aarch64: Adding mcr, mrc 32-bit coprocesor read/write supportKamal Dasu1-0/+153
Adding mrc and mcr support for 32-bit boot mode on aarch64 target. Change-Id: I3879908253ccdf79509dcad752871f422526ec64 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/4483 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-04Rework/update ARM semihostingLiviu Ionescu13-747/+1895
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-31jtag: drivers: sysfsgpio: lift upper gpio number limitPaul Fertser1-4/+4
Recent Linux maps GPIOs from 1023 downwards so do not limit the number to 1000. This should fix #183. Change-Id: I6d4f493b670be9ed9b82759f0fb686a9faddbbf5 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4502 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-31jtag/drivers: Add support for TI XDS110 debug probeEdward Fewell7-2/+2009
Add support for the XDS110 debug probe using the APIs in the probe's firmware. Includes support for older versions of the firmware (with reduced performance) and support for a newer version that includes OpenOCD specific APIs. Tested on various TI LauchPads including MSP432P4, MSP432E4, CC2650, CC2652, and CC3220SF. Updated to add better support for swd switch. Removed issues found with clang static analysis. Updated to add rules entry for the XDS110 probe and Tiva DFU mode (which affects both XDS110 and ICDI probes). Change-Id: Ib274143111a68e67e80003797c6a68e3e80976b2 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4322 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-30Fix warnings exposed by GCC8Paul Fertser4-10/+12
gcc (GCC) 8.1.0 generates new warnings and thus fails the build. The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and SMUL instructions decoding. Reported by Eimers on IRC. Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4526 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-19configure.ac: Fix required libjaylink versionMarc Schink1-1/+1
Change-Id: I9ede86eeef8991db52ffa188ff293c14bd50a1f4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4450 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-05-09doc: fix several typos within manual documentsAntonio Borneo11-71/+71
Mostly trivial fixes spotted by spell checker Change-Id: I3af693faf5506c866e2abe253a0e37aea3c4d284 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4510 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-27arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
Neither the initial loop to clear dirty registers (which visits all registers starting at R2 and counting upwards) nor the final explicit flushes ensure a write-back in arm_dpm_write_dirty_registers. This change makes sure that both our scratch registers (i.e. R0 and R1) are written back to the target. Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-on: http://openocd.zylin.com/4506 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-26doc: fix several typos in openocd.texiAntonio Borneo1-75/+75
Mostly trivial fixes spotted by spell checker One fix s/are/is/ No changes in the content of the document Change-Id: Ic2d8696860c540e901e8c5190f8f1e7dce80545f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4402 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23ChibiOS thread states: Update thread state to label mappingFaisal Shah1-4/+3
Fixed style issue. Removed #define with list of strings, and just put the strings in the array initialization directly. Removed empty space at the start of line. Change-Id: I76580be203d7d69b8c5b5440f820156543e0d5cc Signed-off-by: Faisal Shah <faisal.shah@gmail.com> Reviewed-on: http://openocd.zylin.com/4488 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv2-142/+236
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .incTomas Vanek16-178/+87
Flash loaders refactored to the new style - use generated .inc instead of hexadecimal machine code in the flash driver source. Change-Id: If65a2099589e210f9450819b467d67819fd841fc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4439 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-23board: add configuration for stm32f103c8 "Blue Pill"Matthias Welwarsky2-1/+23
The "Blue Pill" is a popular development board with an STM32F103C8 micro controller. According to sources, it has a 128kB Flash on board even though the option bytes only report 64kB. This patch therefore also modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into account which the board file sets to 0x20000. Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4495 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-18tcl/target: Add Renesas R-Car R8A7790 H2 targetMarek Vasut1-0/+36
Add configuration for the Renesas R-Car R8A7790 H2 target. This is an SoC with four Cortex A15 and four Cortex A7 ARMv7a cores, only the four A15 cores are supported. Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4490 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-17jtag: adapter: fix indentation in handle_interface_commandAntonio Borneo1-8/+8
Minor fix, no code change, just align it to the block it belongs to. Change-Id: I4c3b0d0bd00a55d5109d3723e5c4bfb2fc72e366 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4492 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-12target: add Cortex-M4 target to VF6xx targetMatthias Welwarsky1-1/+1
The Vybrid VF6xx SoCs contain an additional Cortex-M4 core connected to AP number 3 of the main DAP. Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3640 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-12target/cortex_m: allow setting the type of a breakpointTomas Vanek3-32/+5
Cortex-M target used 'auto_bp_type' mode. The requested type of breakpoint was ignored and hard (FPB) breakpoints were set in 'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above 0x20000000. The code memory area of Cortex-M does not mean the memory is flash and vice versa. External flash (parallel or QSPI) is usually mapped above code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis has a RAM block under 0x20000000 boundary. Remove 'auto_bp_type' mode, set breakpoints to requested type. Change 'cortex_m maskisr auto' handling to use a hard temporary breakpoint everywhere: it can also workaround not working soft breakpoints on Cortex-M7 with ICache enabled. Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4429 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10armv8: valgrind memleak fixesMatthias Welwarsky7-9/+74
Various fixes for memory leaks, adds a target cleanup for aarch64 and ARM CTI objects. Change-Id: I2267f0894df655fdf73d70c11ed03df0b8f8d07d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4478 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-10target: add configuration for NXP MC-IMX8M-EVKMatthias Welwarsky2-0/+77
includes target configuration for i.MX8M SoC family, board file needs to set up CHIPNAME and CHIPCORES to match the actual hardware configuration Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4434 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10tcl/board: add board configuration for NXP IMX7SABREMatthias Welwarsky1-0/+114
configuration also contains a reset-init procedure that disables the watchdog and initilizes the boards DDR memory so that you can upload baremetal (e.g. boot loader) code into DDR and start it from there. Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10flash/nor/at91sam: implement flash bank deallocation for SAM seriesTomas Vanek4-53/+61
Microchip (former Atmel) SAM drivers allocate a struct per chip. at91sam3, at91sam34: Deallocate all chip structs from the list at once, on the first bank deallocation. at91samd and at91sam4l drivers do not handle more than one bank. Convert them to simple driver_priv allocation and use default_flash_free_driver_priv(). Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
2018-04-10flash/nor/kinetis: implement flash bank deallocationTomas Vanek1-1/+18
Change-Id: I8ef80eae646d3b3eb7f6dd42067f8516adc5abef Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4415 Tested-by: jenkins
2018-04-10flash/nor: handle flash write alignment/padding in the infrastructureTomas Vanek3-121/+312
Most of flash drivers have to ensure proper flash write block alignment and padding. As there was no support for it in the flash infrastructure, each driver does it its own way. Sometimes this part of code is not properly tested and contains bugs. flash_write(_unlock) joins all image sections targeted to one flash bank using padded areas as a glue. This solves alignment problems on section boundaries but imposes other problems. Introduce new flash bank parameters write_start_alignment, write_end_alignment and minimal_write_gap. New flash drivers can just properly set these values instead of handling alignment by its own. Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command() and handle_flash_write_bank_command()) to prepare write data padded to an alignment required by the flash bank. Rework flash_write_unlock() to discontinue write block when the gap between sections is bigger than minimum specified in minimal_write_gap. minimal_write_gap is set to one sector by default. Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target armv7m: multi-block erase checkTomas Vanek6-98/+137
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode, adapter_khz=1000. Plain read: flash read_bank 0 /dev/null takes 48 seconds. erase_check without this change: flash erase_check 0 takes horrible 149 seconds!! And the same command with the change applied takes 1.8 seconds. Quite a difference. Remove the erase-value=0 version of algorithm as the new one can check for any value. If the target is an insane slow clocked CPU (under 1MHz) algo timeouts. Blocks checked so far are returned and the next call uses increased timeout. Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4298 Tested-by: jenkins Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek12-95/+82
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-09tcl/target: Add Renesas R-Car R8A7791 M2W targetNiklas Söderlund1-0/+27
Add configuration for the Renesas R-Car R8A7791 M2W target. This is an SoC with two Cortex A15 ARMv7a cores, both cores are supported. This patch is based on initial submission by Adam Bass and improvements by Niklas Söderlund. Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Adam Bass <adam.bass@renesas.com> Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se> Reviewed-on: http://openocd.zylin.com/4485 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-09HACKING: document practices to improve code qualityPaul Fertser1-4/+50
Change-Id: I58a7d978b7d5bca3037c4535f06746b9f4411950 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4343 Tested-by: jenkins
2018-04-09configure: disable all drivers when zy1000 is enabledPaul Fertser2-4/+4
This also fixes the transport_is_hla FIXME. Change-Id: I33960f373f11e3e203f9aed9c6d02bf7ca48ac97 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4473 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07gdb_server: gdb_memory_map() reworkTomas Vanek1-17/+21
Use sector sizes instead of bank size. Detect a gap between sectors and emit xml blocks accordingly. Detect sector overflow over the bank size. Change-Id: If0e0e44b0c3b93067b4d717c9c7b07c08582e57b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4436 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-07rtos: Fix XPSR_OFFSET for cortex_m4f stackingArmin van der Togt1-2/+21
Structures rtos_standard_Cortex_M4F_stacking and rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c where using rtos_standard_Cortex_M3_stack_align for the stack-align function. This function calls rtos_Cortex_M_stack_align with XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for cortex-M4F and cortex-M4F with fpu. This patch adds stack_align functions for M4F an M4F_FPU Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl> Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
On SMP targets, the "target smp" command creates a list of targets that belong to the SMP cluster. Free this list when a target gets destroyed on shutdown. For simplicity, the complete list is free'd as soon as the first target of the SMP cluster is destroyed instead of individually removing targets from the list. Change-Id: Ie217ae1efb2e819c288ff3b1155aeaf0a19b06be Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4481 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-07target/arm_adi_v5: extend apcsw command to accept arbitrary bitsTomas Vanek4-21/+75
apcsw command was limited to SPROT bit only. Now user can manipulate any bit except size and addrinc fields. Can be used e.g. to set bus signal 'cacheable' on Cortex-M7 Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4431 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-07Add gdb_report_register_access_error commandTim Newsome2-6/+57
With this option enabled (it's disabled by default) errors accessing registers are returned to gdb. Otherwise they are ignored and success is reported to gdb. (This is the current behavior.) We want this for RISC-V, but there's still some cleanup that needs to be done before that can be upstreamed. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I7e56109ea52d18b780c14a07fb35f9e6e8979da4 Reviewed-on: http://openocd.zylin.com/4452 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
generated by cgit v1.1 at 2024-09-27 23:03:55 +0000