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2017-02-10aarch64: correct breakpoint register offsetMatthias Welwarsky1-7/+4
armv8 breakpoint register spacing is 16, not 4 as in armv7-a Change-Id: I0d49d06878a0c9dab35cde478064e5366f01a8e0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix cache identificationMatthias Welwarsky2-28/+18
Use correct instructions to access CLIDR, CSSELR and CCSIDR. Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of translation table registersMatthias Welwarsky2-11/+100
Correctly access and parse aarch64 ttbcr. Change-Id: I1b1652791a6b5200f58033925286292d838e8410 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix entry into debug stateMatthias Welwarsky2-20/+16
- armv8 EDSCR has no ITR_EN bit, ITR is always enabled. Writes to this bit are ignored but we should not do them anyway - use dpmv8 function to report the reason for debug entry - WFAR is a 64bit register Change-Id: I07b81ecf105ceb7c3ae2f764bb408eb973c1d1de Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use symbolic opcodes instead of hex valuesMatthias Welwarsky1-7/+6
Use opcode definitions from armv8_opcodes.h where appropriate Change-Id: Iead33fb8e62eb2dd2419ef8932f7d46c087f51a8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix accesses to SCTLR_ELn registerMatthias Welwarsky1-27/+142
The system control register has several instances, depending on the exception level. Make sure to access always access the correct one. Change-Id: I9e867f4dbd9625762042f20ed905064ea4e3270f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix error recovery in aarch64_dpm_prepareMatthias Welwarsky1-4/+8
Flush DTRRX with a dummy read if it's full, clear sticky errors by writing CSE bit to EDRCR register. Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: formalize use of CTI in halt and resumeMatthias Welwarsky2-57/+68
Use configured CTI base address instead of hardcoded value, if available. Use symbolic constants instead of raw hex offsets. Trim halt and resume code to what is actually necessary. Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix context and hybrid hardware breakpointsMatthias Welwarsky1-10/+17
Fix 64bit address setting Fix register spacing (16 instead of 4) Set HMC bit for all but linked context match breakpoints, where the bit is ignored anyway Change-Id: I48428f39154a6fe5fadc075ca918d1500a0bb241 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: deconflict debug register namesMatthias Welwarsky2-127/+131
CPUDBG_ -> CPUV8_DBG_ for armv8 debug registers. Change-Id: I3d24cc209309fa9bbeb5c3e6c88a572383c9360e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Implement MA mode for bulk memory reads and writesMatthias Welwarsky1-84/+165
- 64bit addresses are supported - Aarch32 state is supported Change-Id: I8c37fa166954d09195d08c6963b8017194e350f5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: make DCC read/write functions operate on struct armv8_commonMatthias Welwarsky1-30/+31
Change the signature of aarch64_(read|write)_dcc[_64] to take a "struct armv8_common *" as the context to operate on. No functional change. Change-Id: Ie501113f65ea22aff2eee173ec717f6908a63494 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky9-260/+1400
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10target: add -ctibase config option in addition to -dbgbaseMatthias Welwarsky2-1/+21
Some vendors don't fully populate the ROM table, e.g. BCM2357 (used in Raspberry Pi 3) doesn't list CTI, however it is mandatory for halting an ARMv8 core and therefore it's always present (and required), regardless of the ROM table listing it or not. Change-Id: Ia18a4f1b5b931ccd19805b188ebf737c837c6b54 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix reading of MPIDRMatthias Welwarsky1-1/+2
read MPIDR register through correct MSR instruction. Change-Id: I7e2d00c2871191c4168b177a7a809443b0db4c82 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add symbolic definitions for armv8 opcodesMatthias Welwarsky2-0/+127
To replace hexadecimal constants with descriptive names and increase flexibility. Change-Id: I6f7b6f045866ed8b9360f54b640ecdb307eebc51 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Correct target state for hardware stepDavid Ung2-2/+12
When using hardware step for doing stepping, the existing DSCR records the event as external debug request. This will generate a SIGINT event to GDB and causes it to stop the stepping process. For aarch64, read DESR to check if the event is a hardware step and set state to DBG_REASON_SINGLESTEP. With this patch, GDB can now do source level stepping. Change-Id: I1d06f819578c74b3ac17376c67f882adddea1f52 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Enable resuming with addressDavid Ung1-9/+5
Enable resuming to an address. Change-Id: I29c7d3b56f6cbf8b3cd02c93733fc96f45000af3 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add instruction stepping support using hardware steppierre Kuo2-36/+14
Use AARCH64's hardware step event to do stepping. Change-Id: I2d029ceeadd381913d0c3355c8787b11dacff7f7 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Enable halting debug mode on breakpoint setDavid Ung1-0/+12
Ensure that we allow halting debug mode after setting breakpoint Change-Id: I6f0d7a4a4775a93c133fb1ec31dfe3324d9f7395 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add hardware breakpoint supportpierre Kuo1-20/+19
Enable the use of hardware breakpoint on AARCH64. Change-Id: I59caaa6d92ac60278af8938625b1790a1787372f Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: Add ARMv8 AARCH64 support filesDavid Ung9-9/+3701
Add new AARCH64 target and ARMv8 support files. This is an instantiation from the cortex_a files but modified to support 64bit ARMv8. Not all features are complete, notably breakpts and single stepping are not yet implemented. Currently it lets you halt of the processors, resume, dump cpu registers, read/write memory and getting a stack trace with gdb. > halt invalid mode value encountered 5 target state: halted unrecognized psr mode: 0x5 target halted in ARM state due to debug-request, current mode: UNRECOGNIZED cpsr: 0x600001c5 pc: 0x00093528 MMU: disabled, D-Cache: disabled, I-Cache: disabled > targets TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* cpu0 aarch64 little cpu.dap halted > reg ===== arm v8 registers (0) r0 (/64): 0x00000000FFFFFFED (dirty) (1) r1 (/64): 0x00000000F76E4000 (2) r2 (/64): 0x0000000000000000 (3) r3 (/64): 0x0000000000010000 (4) r4 (/64): 0xFFFFFFC06E2939E1 (5) r5 (/64): 0x0000000000000018 (6) r6 (/64): 0x003A699CFB3C8480 (7) r7 (/64): 0x0000000053555555 (8) r8 (/64): 0x00FFFFFFFFFFFFFF (9) r9 (/64): 0x000000001FFEF992 (10) r10 (/64): 0x0000000000000001 (11) r11 (/64): 0x0000000000000000 (12) r12 (/64): 0x00000000000000F0 (13) r13 (/64): 0x00000000EFDFEAC8 (14) r14 (/64): 0x00000000F6DDA659 (15) r15 (/64): 0x0000000000000000 (16) r16 (/64): 0xFFFFFFC0000F9094 (17) r17 (/64): 0x0000000000000000 (18) r18 (/64): 0x0000000000000000 (19) r19 (/64): 0xFFFFFFC00087C000 (20) r20 (/64): 0x0000000000000002 (21) r21 (/64): 0xFFFFFFC000867C28 (22) r22 (/64): 0xFFFFFFC000916A52 (23) r23 (/64): 0xFFFFFFC00116D8B0 (24) r24 (/64): 0xFFFFFFC000774A0C (25) r25 (/64): 0x000000008007B000 (26) r26 (/64): 0x000000008007D000 (27) r27 (/64): 0xFFFFFFC000080450 (28) r28 (/64): 0x0000004080000000 (29) r29 (/64): 0xFFFFFFC00087FF20 (30) r30 (/64): 0xFFFFFFC000085114 (31) sp (/64): 0xFFFFFFC00087FF20 (32) pc (/64): 0xFFFFFFC000093528 (33) xPSR (/64): 0x00000000600001C5 And from gdb (gdb) bt #0 cpu_do_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/mm/proc.S:87 #1 0xffffffc000085114 in arch_cpu_idle () at /mnt/host/source/src/third_party/kernel/3.14/arch/arm64/kernel/process.c:107 #2 0x0000000000000000 in ?? () Change-Id: Iccb1d15c7d8ace7b9e811dac3c9757ced4d0f618 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add 64bit register handling.David Ung2-86/+257
Add various function to read/write ARMv8 registers. Change-Id: I16f2829bdd0e87b050a51e414ff675d5c21bcbae Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add new state ARM_STATE_AARCH64David Ung3-0/+8
Add new enum ARM_STATE_AARCH64 to the list of possible states. Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10server: Allow 64 address to be send over GBD serverDavid Ung1-13/+13
Accept 64 bit addresses from GDB read memory packet. Also allow breakpoint/stepping addresses to take 64bit values. Change-Id: I9bf7b44affe24839cf30897c55ad17fdd29edf14 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang68-546/+728
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-01-23Restore normal development cyclePaul Fertser3-124/+157
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2017-01-22The openocd-0.10.0 releasePaul Fertser1-1/+1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2017-01-22NEWS: last pre-release changesPaul Fertser1-1/+1
Change-Id: I93203717f9096880298c10efebf05d59f888f34b Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3954 Tested-by: jenkins
2017-01-20arm_dpm: avoid duplicating the register cacheMatthias Welwarsky1-4/+7
This bug was already attempted to fix in an earlier patch but merging the "defer-examine" feature caused a regression, which this patch tries to fix again. Change-Id: Ie1ad1516f0d7f130d44e003d6c29dcc1a02a82ca Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3951 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15Restore -dev suffixPaul Fertser1-1/+1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15The openocd-0.10.0-rc2 release candidatePaul Fertser1-1/+1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15NEWS: mention SWO capture facility of the new J-Link driverPaul Fertser1-2/+2
Change-Id: I4fc150584f3f0c5df5c39ae512125b42893331f0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3948 Tested-by: jenkins
2017-01-15jtag: core: report TRST and SRST as asserted only when they really arePaul Fertser1-2/+2
When SRST is never enabled, the global jtag_srst variable is left at its initial state, that is, -1, and it does _not_ mean SRST is currently asserted. Same about TRST. Fixes "reset halt" in cases when srst_pulls_trst but srst usage is not enabled. Change-Id: I8d2e9120479de4cfbf5561033926c9ef945eecc9 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3943 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-01-15flash/nor: fix doc/help and range test for flash protectTomas Vanek3-10/+21
Commit 77a1c01ccbb1150ffe749a7373cf6c4dc15ecad0 introduced infrastructure for utilizing protection blocks of different size than erase sector. Parts of doc/help kept reading 'sector' instead of 'protection block'. flash_driver_protect() parameter range testing did not switched to bank->num_prot_blocks. This change fixes it. Change-Id: Iec301761190a1a1bcc4cb005a519b9e5e4fede51 Reported-by: Mark Odell <mark@odell.ws> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3917 Tested-by: jenkins Reviewed-by: Mark Odell <mrfirmware@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15tcl at91samdXX.cfg: partially revert change 3722Tomas Vanek1-1/+2
Commit 25d7ba19c9e70cf5b912f660cf6aaa93d9ca120f introduced a problem with 'reset halt' due to setting srst_pulls_trst: Error: cortex_m.c:595 cortex_m_halt(): can't request a halt while in reset if nSRST pulls nTRST Sorry, I don't know why I overlooked it when I tested #3722. Change-Id: I41e9473dd91a86d93cf3e78b1fbbdfe1dd188d83 Reported-by: Ladislav Laska <laska@kam.mff.cuni.cz> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3942 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-01-15adi_v5_jtag: make sure SSTICKYERR is cleared after a PORMatthias Welwarsky1-6/+1
Don't terminate the transaction end-check early if debug power-loss was detected, without clearing SSTICKYERR. Change-Id: I83b6a4a20523eea42e48a15297f972a730aa21a8 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3947 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15doc: Improve ftdi driver sectionAndreas Fritiofson1-7/+11
Fix typo and a sentence that sounds strange since the ft2232 driver was removed. Add documentation for the SWD signal usage. Remove the text mentioning a default VID:PID which doesn't exist. Change-Id: I27eba571f2f7c46bdb6ae623ab285595018e99d9 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3935 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15helper,rtos,server: Restore missing warning flagsAndreas Fritiofson3-3/+3
These libraries override the used CFLAGS without adding the defaults. This didn't have any effect until change http://openocd.zylin.com/3870 (ef4c139). Restore by adding AM_CLAGS to the per-target CFLAGS. Interestingly, automake seems to clear the CFLAGS for the target even if the override variable is only mentioned within a non-active conditional branch, such as the IS_MINGW for the affected libraries. Change-Id: I805206865e59e3fa33a7ea3c0d3472e51219351c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3927 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-01-15jtag: drivers: build usb_blaster only if enabledPaul Fertser1-1/+1
Fix build failure when libusb dev files are not available and so usb_blaster is disabled. Change-Id: I4cda7df689cdb4b62b733cbbab813241cf561e29 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3920 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-01-15libjaylink: Update to 0.1.0 releaseMarc Schink1-0/+0
Change-Id: I5a905ccda346c09187f7f8e8229ae71d3353128f Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3946 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-25Restore -dev suffixPaul Fertser1-1/+1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2016-12-25The openocd-0.10.0-rc1 release candidatePaul Fertser1-1/+1
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
2016-12-25NEWS: prepare for new releasePaul Fertser1-1/+123
Change-Id: I141ff17f6dcab7e164a19c91b975ddd455d26dbc Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3854 Tested-by: jenkins
2016-12-25doc: fix underfull and overfull boxesPaul Fertser1-11/+17
This is needed to generate PDF user manual without typesetting artifacts. Change-Id: Ibcbd804dac2b9415459327f53f6fad0dc38fa5c6 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3919 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-12-25doc: add a cross-reference to GDB threading commandsPaul Fertser1-1/+5
Change-Id: If4766ba0053fc94cd47495e442fcf288241af218 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3557 Tested-by: jenkins
2016-12-25target: armv7a: remove unused level_num field from armv7a_cachesizePaul Fertser1-1/+0
This was never used and produces warnings on some systems. Change-Id: I48d2c5b79890bb2d70c5fae95278b8eb62743398 Reported-by: Tommy Murphy <tm1234@users.sf.net> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3891 Tested-by: jenkins
2016-12-25tcl: target: imx5{1,3}: remove bogus tapenable commandPaul Fertser2-6/+0
This seems to be a leftover from borrowing from omap3* configs. Since SJC is not enabling or disabling the DAP tap, and the tap is always available, the extra tapenable command causes warnings on startup (can't enable what's already enabled). Change-Id: I7514436d565aa5b91876dbdab547956f36dcab77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3892 Tested-by: jenkins
2016-12-25target: cortex_a: fix segfault when SPSR is not properly handledPaul Fertser1-9/+11
OpenOCD doesn't (yet) know how to handle HYP mode properly so spsr register is not getting initialised when OpenOCD connects to a target stopped in this mode. Reported on IRC by thinkfat and nearffxx. Change-Id: I4bda9ba0c582c8e9cacefe708cc4a3d947151f84 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3906 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Chengyu Zheng <chengyu.zheng@polimi.it>
2016-12-25README: fix a typoPaul Fertser1-1/+1
Change-Id: I1ad1ba001f8fad0fffa9b6bd5b21dd58be4f6181 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3902 Tested-by: jenkins Reviewed-by: Chengyu Zheng <chengyu.zheng@polimi.it>
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