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2022-11-22target/riscv: Share single-target and SMP resume code.Tim Newsome1-30/+33
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22rtos/hwthread: Hide unavailable targets from thread list.Tim Newsome1-2/+4
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22target/riscv: Make poll() use TARGET_UNAVAILABLE.Tim Newsome2-60/+152
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21target/riscv: Refactor riscv_openocd_poll()Tim Newsome1-101/+74
There used to be entirely separate code paths depending on whether we're in SMP mode or not. Now they're both the same. Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21target/riscv: Error when hart becomes unavailable during resumeTim Newsome1-0/+2
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21Merge pull request #769 from riscv/0.11Tim Newsome2-27/+22
Revive 0.11 debug spec support
2022-11-17target/riscv: 0.11, call handle_halt() after stepTim Newsome1-1/+3
This ensures that we populate the register cache and set target->state. Some RISC-V changes had upset the balance. Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17target/riscv: Ignore maskmax when reading back tdata1Tim Newsome1-15/+18
We don't correctly write it, so we shouldn't expect it to read back the same value. Fixes hardware breakpoints on mcontrol triggers. Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17target/riscv: Don't always read on DMI batch write (#768)Tim Newsome3-13/+19
Indicate to the JTAG driver that it does not need to read and return the DR register value after scanning the JTAG chain. riscv_batch_run(), calls jtag_add_dr_scan() to schedule a DR scan operation. Eventually, this will result in the JTAG driver performing a JTAG scan to write to or read from DR. The decision on whether to write to and/or read from DR register is determined by the second parameter to jtag_add_dr_scan(), i.e. a "struct scan_field". Of particular interest here is if batch->fields[i]->in_value is not NULL, the JTAG developer must return the DR value collected from the JTAG scan operation. When creating the DR scan operation instruction with riscv_batch_add_dmi_write(), batch->fields[i]->in_value points to a location in batch->data_in buffer, meaning batch->field[i]->in_value is not NULL, and the JTAG developer must therefore read and return the DR value collected. The returning of the DR value is redundant in a write operation. This patch set batch->fields[i]->in_value to NULL to indicate the DR value need not be returned. This allows the JTAG developer to optimize away any code associated with returning the DR value. Normally, the extra work to return the DR value is negligible. However, in one usecase it introduces significant delays In this use case a JTAG driver forwards all JTAG scan to a server on a network. If the server has to return the DR value, it has to perform the JTAG scan before replying to the JTAG driver, and only then the JTAG driver can send the next JTAG scan operation. However, if there is no need to return the DR value, the server can acknowledge the JTAG operation request immediately,thus signalling to the JTAG driver that it is free to send the next JTAG scan operation. At the same time of receiving the second JTAG operation the server will process the original JTAG scan. This saves time and mitigates network delay. Also, not having to include the DR value in resulting in smaller reply packet from server to JTAG driver and save on network traffic. This doubles download speeds to spike using remote bitbang. Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17target/riscv: Ignore debug_execution in 0.11 resumeTim Newsome1-11/+1
It's only used to change what callback events are generated, and there are none anyway. (That's probably a bug, but since 0.11 is so rare I'm not going to worry about it.) Fixes #757. Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-16Fix breackpoint_add for rtos swbp (#734)Evgeniy Naydanov2-14/+11
breakpoint_add should use rtos only if request is done by gdb. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-15Workaround for fp register access in case fp unit is disabled (#766)Evgeniy Naydanov1-11/+11
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus set to 0), accessing any fp register results in a hang (any abstract command timeouts, untill the board is rebooted). Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-10Improve a couple of user/debug messages. (#763)Tim Newsome2-2/+3
* gdb_server: Improve info message. Add target name and state to "Not running when halt was requested" message. Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd Signed-off-by: Tim Newsome <tim@sifive.com> * rtos/hwthread: Nicer debug message in hwthread_update_threads() Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10target/riscv: Use vlenb to check whether vector registers exist (#762)Tim Newsome3-24/+13
E.g. the Zve* vector extensions have all the same registers as the full V extension, but leaves misa.V clear. Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10riscv/target: Replace is_halted() with get_hart_state() (#756)Tim Newsome3-61/+84
Prep work for handling unavailable harts. Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-09Use match field for trigger (#725)Xiang W3-193/+305
* Use match field for trigger The watchpoint cannot capture all data modifications only through the trigger of ANY SIZE and EQUAL, and an error will occur. This patch accommodates watchpoints by adding more types of matches Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a Signed-off-by: Xiang W <wxjstz@126.com> * Add variable type trigger support Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1 Signed-off-by: Xiang W <wxjstz@126.com> * remove trailing whitespace Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84 Signed-off-by: Xiang W <wxjstz@126.com> * update triggers enumerate Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)Tim Newsome1-5/+16
* target/riscv: Deal with DMI busy in sample_memory_bus_v1() Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231 Signed-off-by: Tim Newsome <tim@sifive.com> * Comment code more clearly. Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Remove extra tab Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-01Fix dm->current_hartid corruption on hartsellen discovery (#754)Dolu19901-1/+9
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2 Signed-off-by: Charles Papon <charles.papon.90@gmail.com> * target/riscv Ensure HART_INDEX_DIRTY does not have side effects Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027 Signed-off-by: Charles Papon <charles.papon.90@gmail.com> Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-10-31github/workflow: enable libftdi based adapters (#755)Tim Newsome2-4/+19
Change-Id: I74b07b21573294dd7d9d3caf41c5755622c77149 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7008 Tested-by: jenkins Reviewed-by: Xiaofan Chen <xiaofanc@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-10-27target: Add TARGET_UNAVAILABLE state. (#752)Tim Newsome2-0/+4
This is added for future RISC-V changes. The RISC-V debug interface can explicitly tell a debugger when a hart is unavailable. This is used for instance when that hart is powered down (or yet to be powered up out of reset). Change-Id: I8a062d59eea1e5b3c788281a75159592db024683 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-21target/riscv: Correctly set target->state in deassert_reset (#750)Tim Newsome1-2/+7
* target/riscv: Correctly set target->state in deassert_reset This bug didn't lead to problems, but it would with some upcoming changes. Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb Signed-off-by: Tim Newsome <tim@sifive.com> * Keep debug_reason in sync with state Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-14[riscv] step operation handler should respect handle_breakpoints parameter ↵Anatoly Parshintsev1-3/+22
(#741) * [riscv] step operation handler should respect handle_breakpoints parameter When step operation is requested the OpenOCD frontend (like gdb server or TCL server) has an option to control how existing breakpoints are handled upon step. Some OpenOCD frontends (like gdbserver) may choose to disable special handling of existing breakpoints - thus handle_breakpoints is set to 0, while others (like TCL server) expect target handler to temporary disable the matching breakpoint to allow the step operation to complete successfully. In the current implementation handle_breakpoints parameter was ignored by target-specific handler. Thus, the following sequence of commands: ``` halt bp <current_pc> 4 step ``` Resulted in *step* operation to not change PC because of bp match. This commit addresses this issue. * Adjusted calls to logging facilities (addressed review comments) Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-12Properly track selecting multiple harts at once. (#743)Tim Newsome1-59/+64
* Properly track selecting multiple harts at once. use_hasel is a bit of a hack. Change-Id: Ia589ebc16bca32038d915df9988361b88e940917 Signed-off-by: Tim Newsome <tim@sifive.com> * Clarifying comment. Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Rename set_hartsel to set_dmcontrol_hartsel Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850 * Make set_dmcontrol_hartsel() more idiomatic. Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486 * Use constant for multiple harts instead of -1. Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-12filter_openocd: Prefer high repetitions.Tim Newsome1-1/+1
I'd rather see "these 10 lines were repeated 100 times" than "these 100 lines were repeated 10 times." Change-Id: I88fcf86b10c5fb0ba1d19b21fe054065da90fedd Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-11target/riscv: Clean up halt_go for multiple harts.Tim Newsome1-6/+11
Also add an early exit for if any harts are unavailable. Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-10Merge pull request #745 from dmitryryzhov/fix-bracesTim Newsome1-2/+2
Fix incorrect braces caused by #732
2022-10-10Merge pull request #744 from mrv96/cjtagTim Newsome1-5/+6
Handle correctly cJTAG reset
2022-10-07(Re)Init cJTAG before move JTAG to reset statemrv961-1/+1
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-07(Re)Init cJTAG only after trst (not after srst)mrv961-4/+5
2022-10-07Fix incorrect braces caused by #732Dmitry Ryzhov1-2/+2
2022-10-06Merge pull request #742 from mrv96/cjtagTim Newsome1-5/+3
Fix Digilent JTAG-HS2 cJTAG configuration script
2022-10-05Fix Digilent JTAG-HS2 cJTAG configuration scriptmrv961-5/+3
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-05riscv: Minor formatting cleanup.Tim Newsome1-9/+7
Change-Id: I0256fd047d8369ca7b327172225a9d1f827673c5 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-05Use TMSC_EN signal for cJTAG escape seq if definedmrv961-0/+5
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-05Support cJTAG JScan3 modemrv963-14/+69
2022-10-05Rename ftdi_oscan1 to ftdi_cjtagmrv963-14/+14
2022-10-05OScan1 code cleanupmrv962-119/+119
- change OSCAN1 to OScan1 - fix spacing
2022-10-04Merge pull request #738 from riscv/current_hartidTim Newsome4-121/+79
Remove riscv_info_t.current_hartid
2022-09-30Remove riscv_info_t.current_hartidTim Newsome4-121/+79
This was used to track which hart a given operation must apply to. But we already have a target associated with each operation, and from there we can find the desired hart id. dm013_info_t already tracks current_hartid (meaning which hart ID is currently selected by the DM). This makes the code simpler to understand. Also it turns out we don't need to make sure the correct hart ID is currently selected because there are only a few real entry points. Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-29Use LOG_TARGET_FOO() functions in more places. (#731)Tim Newsome3-43/+34
Change-Id: Id2266dbfb6209bf0676f28e7383a12705ce2a70e Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-27Merge pull request #727 from riscv/poll_backoffTim Newsome2-35/+34
Make poll backoff time based.
2022-09-27Merge pull request #733 from en-sc/en-sc/remove-erroneous-debuglogTim Newsome1-14/+0
Remove incorrect debug_log in wait_for_idle
2022-09-27Merge pull request #732 from en-sc/en-sc/error-code-regwrite-directTim Newsome1-12/+25
Propagate error code in register_read/write_direct
2022-09-26Remove incorrect debug_log in wait_for_idleEvgeniy Naydanov1-14/+0
According to RISC-V External Debug Support Version 0.13.2 (paragraph 3.12.6), cmderr field contains a valid value only if busy is 0, so it is incorrect to analize it on timeout.
2022-09-26Propagate error code in register_read/write_directEvgeniy Naydanov1-12/+25
In some cases error code returned by riscv_program_insert was ignored
2022-09-23Merge pull request #729 from mrv96/patch-1Tim Newsome3-3/+51
Support for custom TMSC buffer: cJTAG OScan1 improvement
2022-09-22Improve oSCAN1 documentationmrv961-3/+16
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-09-22Don't use const on temporary variable.Tim Newsome1-1/+1
It's not part of OpenOCD style: https://review.openocd.org/c/openocd/+/6319/5..10/src/target/aarch64.c#b1500 Change-Id: Ifb612a942507ca5ed8cac3e3ec59e0e14b0298ed Signed-off-by: Tim Newsome <tim@sifive.com>
2022-09-19Add Digilent JTAG-HS2 cJTAG configurationmrv961-0/+19
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-09-19Support for custom TMSC buffermrv961-0/+16
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
generated by cgit v1.1 at 2024-10-12 13:36:57 +0000