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2018-01-19Incorporate review feedback from OpenOCD teamTim Newsome1-17/+9
Remove unused file handle, and rename the only remaining one to make more sense. Close file descriptor if initialization fails. Change-Id: I383567aaadb1aa59d86f814eba8bc65f24e91928
2018-01-17Merge pull request #184 from riscv/cleanupTim Newsome1-9/+0
Remove dead code.
2018-01-15Remove dead code.Tim Newsome1-9/+0
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-10Merge pull request #172 from riscv/dbus_read_commentMegan Wachs1-1/+6
Add a comment in dbus_read
2018-01-10Merge pull request #178 from riscv/cleanupTim Newsome1-2/+2
Rename dummy variable to be correct.
2018-01-10Merge pull request #181 from riscv/propagate_errorsTim Newsome6-63/+128
Propagate register read errors
2018-01-09Muck with mstatus to always be able to read FPRsTim Newsome1-1/+13
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-08Propagate register read errors.Tim Newsome6-62/+115
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-05Merge pull request #179 from riscv/multicore_hart_selectionTim Newsome1-4/+12
Select current hart before reading memory.
2018-01-05Merge pull request #173 from riscv/warn_namesTim Newsome2-6/+5
Use register names instead of numbers in warnings
2018-01-05Rename dummy variable to be correct.Tim Newsome1-2/+2
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05Merge pull request #174 from riscv/delay_infoTim Newsome2-4/+4
Make delay update messages debug instead of info.
2018-01-04Select current hart before reading memory.Tim Newsome1-4/+12
This avoids trying to read memory from the wrong hart, if the current hart was changed by an earlier call (eg. to poll()). Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04Make delay update messages debug instead of info.Tim Newsome2-4/+4
They confuse users otherwise. Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04Add a comment in dbus_readMegan Wachs1-1/+6
This just comments the current behavior
2018-01-04Use register names instead of numbers in warningsTim Newsome2-6/+5
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-03Merge pull request #170 from riscv/strtoullTim Newsome1-1/+1
Parse 64-bit CRC addrs even on 32-bit hosts
2018-01-02Parse 64-bit CRC addrs even on 32-bit hostsTim Newsome1-1/+1
Change-Id: I38720163eff292b2c24f25da4e25feb8245ff672
2018-01-02Merge pull request #169 from riscv/unused_boardsTim Newsome3-96/+0
Remove board files that I shouldn't have added
2017-12-29Remove board files that I shouldn't have addedTim Newsome3-96/+0
There are 3 other ones for the SiFive target. Change-Id: I987331a82186a3738096cc390c91889118bf9ac2
2017-12-29Merge pull request #168 from gnu-mcu-eclipse/sifive-cfgv20171231Tim Newsome3-0/+78
Add config files for the SiFive boards
2017-12-29add configs for the SiFive boardsLiviu Ionescu3-0/+78
- the HiFive1 board definition includes the FTDI interface - the Arty boards require external interface definitions
2017-12-28Merge pull request #167 from riscv/sifive_cfgTim Newsome3-0/+96
Add config files for SiFive RISC-V hardware.
2017-12-28Merge pull request #165 from riscv/typoTim Newsome1-1/+1
Fix typo.
2017-12-28Add config files for SiFive RISC-V hardware.Tim Newsome3-0/+96
Copied from https://github.com/gnu-mcu-eclipse/openocd Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
2017-12-28Fix typo.Tim Newsome1-1/+1
Issue #164 Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
2017-12-27Merge pull request #163 from riscv/no_abortTim Newsome5-54/+77
Get rid of abort() calls.
2017-12-27Get rid of abort() calls.Tim Newsome5-54/+77
Also changed a few asserts that could trigger due to broken hardware. Fixes Issue #142. Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27Merge pull request #162 from riscv/no_abortTim Newsome3-34/+62
Propagate error instead of calling abort().
2017-12-26Propagate error instead of calling abort().Tim Newsome3-34/+62
As part of this I improved the memory read/write fatal error handling a bit. Now at least we try to leave autoexec turned off, and will even restore the temp registers if the situation isn't too hosed for that. Partly addresses Issue #142 Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26Merge pull request #161 from riscv/dead_codeTim Newsome2-18/+0
Remove unused code.
2017-12-26Remove unused code.Tim Newsome2-18/+0
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26Merge pull request #160 from riscv/styleTim Newsome16-735/+848
Conform to OpenOCD style guide.
2017-12-26Conform to OpenOCD style guide.Tim Newsome16-735/+848
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26Merge pull request #159 from riscv/updateTim Newsome109-906/+5299
Merge changes from master
2017-12-22Merge branch 'master' into updateTim Newsome109-906/+5299
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-22Merge pull request #156 from riscv/fespiTim Newsome2-15/+20
fix fespi flash after registers were renamed.
2017-12-21Fix flash/run algorithm with new register namesTim Newsome2-5/+8
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21Make functions static. Free memory.Tim Newsome1-10/+12
Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
2017-12-21Merge pull request #155 from riscv/debug_definesMegan Wachs1-22/+48
Update debug_defines to the one used with spike.
2017-12-21Merge pull request #148 from riscv/macbuildMegan Wachs1-1/+1
Use %ll instead of %L in scanf.
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21Merge pull request #145 from riscv/rbb_winTim Newsome3-8/+40
Fix Windows build
2017-12-21Merge pull request #151 from riscv/use_parenTim Newsome1-1/+1
Use parens after if.
2017-12-21Use parens after if.Tim Newsome1-1/+1
I'm surprised this built with gcc before. Fixes Issue #150. Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-20config for ESPRESSObin from Globalscale Tech. Inc.Jiri Kastner1-0/+7
Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/4303 Tested-by: jenkins Reviewed-by: Forest Crossman <cyrozap@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-12-20configs for Marvell Armada 3700Jiri Kastner3-0/+78
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd Signed-off-by: Jiri Kastner <cz172638@gmail.com> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/4302 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-19Merge pull request #149 from riscv/xml_registersTim Newsome8-361/+583
Send gdb an XML target description that contains only a list of registers we think exist on this target
2017-12-19Add `riscv expose_csrs` command.Tim Newsome1-0/+110
This lets users tell OpenOCD which non-standard CSRs exist on their target, that will also be accessible and whose existence will be communicated to gdb. Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19Hide supervisor registers if there is no S mode.Tim Newsome2-28/+32
Also update encoding.h. Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
generated by cgit v1.1 at 2024-11-16 21:05:28 +0000