| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-07-25 | Print out which port OpenOCD is listening on.print_port | Tim Newsome | 1 | -0/+6 | |
| This is essential when a test environment asks OpenOCD to listen on port 0, so that the environment can easily discover which port is actually being used. | |||||
| 2017-07-16 | Merge pull request #84 from riscv/reset | Tim Newsome | 1 | -2/+23 | |
| Fix infinite loop in reset. | |||||
| 2017-07-16 | Use a wall clock timeout to complete reset. | Tim Newsome | 1 | -5/+9 | |
| 2017-07-14 | Fix infinite loop in reset. | Tim Newsome | 1 | -1/+18 | |
| 2017-07-13 | Merge pull request #83 from riscv/triggers | Tim Newsome | 4 | -643/+359 | |
| Share trigger code between 0.11 and 0.13 code. | |||||
| 2017-07-12 | Share trigger code between 0.11 and 0.13 code. | Tim Newsome | 4 | -643/+359 | |
| The actual implementation of triggers didn't change between those two versions, so there's no need to duplicate the code. In the process, I also fixed a minor multicore bug where tselect didn't always get written on all harts. | |||||
| 2017-07-12 | Merge pull request #82 from riscv/comment | Tim Newsome | 1 | -0/+3 | |
| Forgot to commit this follow up to PR #79 | |||||
| 2017-07-12 | Forgot to commit this follow up to PR #79 | Tim Newsome | 1 | -0/+3 | |
| 2017-07-12 | Merge pull request #79 from riscv/abstract_regs | Tim Newsome | 1 | -99/+287 | |
| Use abstract command to access registers if possible | |||||
| 2017-07-12 | Keep around cmderr for callers to inspect. | Tim Newsome | 1 | -26/+39 | |
| Use this to only change abstract register access behavior when cmderr explicitly says the requested operation is unsupported. | |||||
| 2017-07-12 | Try abstract register writes as well. | Tim Newsome | 1 | -55/+133 | |
| 2017-07-12 | Try using abstract commands to read registers | Tim Newsome | 1 | -62/+159 | |
| This is the only way the spec guarantees that GPRs are accessible, and depending on the implementation this might be the only way that CSRs are accessible. Also changed the debug code that parses out DMI fields to be simpler to maintain (albeit a little slower). riscv013_execute_debug_buffer() now automatically clears cmderr if the command fails. That feels like the right behavior. (It does return the error to its caller.) | |||||
| 2017-07-11 | Merge pull request #80 from riscv/triggers | Tim Newsome | 4 | -82/+135 | |
| Disable debugger-set triggers on connect | |||||
| 2017-07-10 | Merge pull request #81 from riscv/llp64 | Palmer Dabbelt | 1 | -27/+27 | |
| Use LL for 64-bit defines, as Windows is LLP64 | |||||
| 2017-07-10 | Use LL for 64-bit defines, as Windows is LLP64 | Palmer Dabbelt | 1 | -27/+27 | |
| This should also fix bugs on ILP32 systems. | |||||
| 2017-07-10 | Disable debugger-set triggers on connect | Tim Newsome | 4 | -82/+135 | |
| When first connecting to a target, have the debugger disable any hardware triggers that are set by a previously connected debugger. The 0.11 code already did this, but 0.13 did not. To achieve this I decided to share the code to enumerate triggers between 0.11 and 0.13, which required me to implement get_register() and set_register() for 0.11, which made the whole change a lot larger than you might have guessed. Hopefully this sets us up to in the future share the code to set/remove triggers as well. | |||||
| 2017-07-06 | Merge pull request #78 from riscv/build32 | Tim Newsome | 2 | -1/+14 | |
| Add 32-bit build | |||||
| 2017-07-06 | Fix 32-bit build.build32 | Tim Newsome | 1 | -1/+1 | |
| Code taken from http://openocd.zylin.com/#/c/4178/ | |||||
| 2017-07-06 | Build 32- and 64-bit binaries with Travis. | Tim Newsome | 1 | -0/+13 | |
| 2017-07-06 | Merge pull request #74 from riscv/build32 | Tim Newsome | 3 | -7/+10 | |
| Fix 32-bit build errors. | |||||
| 2017-07-06 | Merge pull request #77 from riscv/travis | Tim Newsome | 1 | -0/+5 | |
| Perform regular build with travis. | |||||
| 2017-07-05 | Perform regular build with travis. | Tim Newsome | 1 | -0/+5 | |
| 2017-07-03 | Merge pull request #73 from riscv/old_triggers | Tim Newsome | 1 | -44/+130 | |
| Add back support for type 1 triggers | |||||
| 2017-07-03 | Merge pull request #69 from riscv/multi-gdb | Palmer Dabbelt | 3 | -43/+66 | |
| Fix the multi-GDB mode bugs | |||||
| 2017-07-03 | Merge pull request #72 from dmitryryzhov/examine_restore_temp_reg | Palmer Dabbelt | 1 | -0/+12 | |
| Restore value of temporary register (s0) in examine OpenOCD procedure… | |||||
| 2017-07-03 | Fix 32-bit build errors. | Tim Newsome | 3 | -7/+10 | |
| I only compiled the source. Didn't have the tooling installed to link. Hopefully that's good enough. Fixes #71. | |||||
| 2017-07-03 | Fix trigger set/clear bug. | Tim Newsome | 1 | -2/+2 | |
| 2017-07-03 | Add back support for type 1 triggers.old_triggers | Tim Newsome | 1 | -42/+120 | |
| They were implemented, and people want to keep using them. Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the current address of 0x301. Actually return an error when we fail to read a CSR. Tweak cache_set32() debug output. | |||||
| 2017-07-01 | Fix comment about saving the temporary register in examine procedure. | Dmitry Ryzhov | 1 | -2/+6 | |
| 2017-06-30 | Restore value of temporary register (s0) in examine OpenOCD procedure in ↵ | Dmitry Ryzhov | 1 | -0/+8 | |
| case of core can not execute 64 bit instruction. | |||||
| 2017-06-27 | Check for errors in read_csr(). | Tim Newsome | 1 | -2/+10 | |
| Also slightly improve debugging output. | |||||
| 2017-06-21 | Don't set breakpoints on disabled hartsv20170621 | Palmer Dabbelt | 1 | -0/+6 | |
| 2017-06-21 | No longer hard-code the non-RTOS hart to 0 | Palmer Dabbelt | 1 | -3/+4 | |
| I was just being lazy here. | |||||
| 2017-06-21 | Allow memory writes to proceed on all harts | Palmer Dabbelt | 1 | -6/+0 | |
| 2017-06-21 | Refactor examine, to avoid some assertions | Palmer Dabbelt | 1 | -9/+16 | |
| Now that we're supporting non-RTOS multi-hart mode there's some more assertions that you're running on the right hart. Those assertions aren't sane very early in examine, so I avoid them. | |||||
| 2017-06-21 | Factor out checking if harts should be used | Palmer Dabbelt | 3 | -18/+35 | |
| Rather than having a bunch of "if rtos" stuff, I now just check "if hart_enabled". This makes some code paths cleaner, all of which were buggy in the non-RTOS multi-hart mode. | |||||
| 2017-06-20 | Set current_hartid from coreid | Palmer Dabbelt | 3 | -7/+5 | |
| This avoids a bunch of RTOS special cases. | |||||
| 2017-06-20 | Merge pull request #68 from riscv/multicore | Palmer Dabbelt | 4 | -38/+89 | |
| Testsuite now passes on multicore target | |||||
| 2017-06-20 | Set hardware triggers on all harts.multicore | Tim Newsome | 1 | -33/+69 | |
| Right now we're using "threads" to represent harts. gdb/OpenOCD assume there's only one set of hardware breakpoints among all threads. Make it so. | |||||
| 2017-06-20 | Don't immediately segfault with -rtos on v0.11. | Tim Newsome | 1 | -0/+3 | |
| 2017-06-20 | Comment curious code. | Tim Newsome | 1 | -0/+4 | |
| 2017-06-20 | Update list of "threads" when harts are discovered. | Tim Newsome | 3 | -5/+13 | |
| This ensures that "info threads" is accurate as soon as gdb connects. Also print out number of triggers that is discovered in examine(). | |||||
| 2017-06-20 | Merge pull request #67 from riscv/cosmetics | Tim Newsome | 3 | -77/+147 | |
| Various cosmetic improvements | |||||
| 2017-06-19 | Put early DEBUG notice of XLEN back. | Tim Newsome | 1 | -0/+5 | |
| 2017-06-16 | Update debug_defines. Clarify debug output. | Tim Newsome | 2 | -52/+118 | |
| Update debug_defines from the spec, commit 920ec9a690. Decode dmstatus scans in the debug output. | |||||
| 2017-06-16 | Fix comment. | Tim Newsome | 1 | -1/+1 | |
| 2017-06-16 | Tell the user about detected harts. | Tim Newsome | 1 | -8/+10 | |
| 2017-06-16 | Tighten up debug output. | Tim Newsome | 1 | -17/+14 | |
| Assuming the program allocating code works, we don't need its output. Only output parts of the debug RAM that are actually doing something. | |||||
| 2017-06-16 | Merge pull request #66 from riscv/whitespace | Tim Newsome | 6 | -335/+333 | |
| Fix indentation to match OpenOCD style. | |||||
| 2017-06-15 | Fix indentation to match OpenOCD style. | Tim Newsome | 6 | -335/+333 | |
| This change is just in the whitespace. There are no code changes. See http://openocd.org/doc-release/doxygen/stylec.html | |||||
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