| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-02-17 | Fix use of REG vs CSR constants. | Tim Newsome | 1 | -26/+30 | |
| 23 gdbserver.py tests pass now. Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b | |||||
| 2017-02-17 | Bunch of register access refactoring. | Tim Newsome | 2 | -546/+161 | |
| Got rid of the last reference to the old debug RAM code! (Mostly?) SimpleF18Test passes now. Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be | |||||
| 2017-02-16 | Check busy before triggering another command. | Tim Newsome | 1 | -46/+50 | |
| This version was able to download code, and run to a breakpoint. Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21 | |||||
| 2017-02-15 | Check for errors after read/write. | Tim Newsome | 1 | -4/+12 | |
| The code doesn't do anything intelligent if errors are found. But MemTestBlock now also passes. I'm not quite sure why. Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1 | |||||
| 2017-02-15 | Fix double read, which might have side effects. | Tim Newsome | 1 | -4/+6 | |
| Now passing MemTest{8,16,32,64} Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1 | |||||
| 2017-02-15 | Make MemTest32 pass. | Tim Newsome | 1 | -2/+2 | |
| Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513 | |||||
| 2017-02-15 | Some memory access works. | Tim Newsome | 2 | -351/+161 | |
| MemTest16 passes, but MemTest32 fails. Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65 | |||||
| 2017-02-14 | Merge pull request #15 from sifive/get_set_reg_error | Tim Newsome | 2 | -9/+45 | |
| Use the set/reg register error return code when registers don't exist. | |||||
| 2017-02-14 | Make general CSR reads work. | Tim Newsome | 1 | -36/+22 | |
| Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd | |||||
| 2017-02-14 | Make it all the way through examine(). | Tim Newsome | 1 | -220/+85 | |
| This includes reading GPRs (although I haven't confirmed the values) and doing some CSR reading/writing to disable triggers that may be left over from a previous setting. Change-Id: I2c627bd002d601e302a40f838087541897c025fd | |||||
| 2017-02-14 | More dbus->dmi. | Tim Newsome | 1 | -21/+65 | |
| Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb | |||||
| 2017-02-13 | Read misa during examine(), using program buffer. | Tim Newsome | 2 | -100/+939 | |
| Change-Id: Icad5324d216b61207cb5f6024b2deab065658640 | |||||
| 2017-02-13 | dbus -> dmi | Tim Newsome | 2 | -160/+160 | |
| Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839 | |||||
| 2017-02-13 | Discover XLEN using abstract reg reads. | Tim Newsome | 2 | -42/+64 | |
| Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b | |||||
| 2017-02-10 | Attempt to discover XLEN with abstract reg reads | Tim Newsome | 4 | -108/+118 | |
| Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a | |||||
| 2017-02-10 | riscv: Add register name to message when they do not exist. | Megan Wachs | 2 | -7/+7 | |
| 2017-02-10 | Halt target in riscv_examine(). | Tim Newsome | 2 | -30/+45 | |
| Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded | |||||
| 2017-02-09 | Add debug_defines.h. | Tim Newsome | 1 | -0/+630 | |
| Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893 | |||||
| 2017-02-08 | Detect and smoketest data and ibuf registers. | Tim Newsome | 1 | -28/+69 | |
| Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207 | |||||
| 2017-02-08 | Correctly parse dmcontrol. | Tim Newsome | 1 | -51/+29 | |
| Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4 | |||||
| 2017-02-07 | Update DMI bus width for 0.13. | Tim Newsome | 2 | -10/+2 | |
| Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0 | |||||
| 2017-02-07 | Merge remote-tracking branch 'origin/riscv' into HEAD | Megan Wachs | 7 | -2297/+6016 | |
| 2017-02-06 | Merge pull request #16 from sifive/0.13 | Tim Newsome | 6 | -2297/+5375 | |
| Refactor code to support multiple debug spec versions. | |||||
| 2017-02-05 | Add missing header file. | Tim Newsome | 1 | -0/+62 | |
| Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df | |||||
| 2017-02-05 | Use the set/reg register error return code when registers don't exist. | Megan Wachs | 2 | -9/+45 | |
| 2017-02-05 | Add the first difference for 0.13 targets. | Tim Newsome | 1 | -1/+1 | |
| Just to confirm the 0.13 code takes a different path. Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36 | |||||
| 2017-02-05 | Use the csrNNN name instead of "mstatus". | Tim Newsome | 1 | -2/+6 | |
| Fixes flashing code. Change-Id: Id12c926f5ada009e06f6601362deefec946afc98 | |||||
| 2017-02-05 | Most gdbserver tests pass now. | Tim Newsome | 5 | -2296/+5308 | |
| Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719 | |||||
| 2017-01-26 | Merge pull request #13 from sifive/disable_interrupts | Tim Newsome | 1 | -0/+18 | |
| riscv: Globally disable interrupts when running algorithms. | |||||
| 2017-01-25 | riscv: disable interrupts for all priviledge levels | Megan Wachs | 1 | -3/+2 | |
| 2017-01-25 | riscv: Use proper UINT packing and unpacking routines for disabling ↵ | Megan Wachs | 1 | -5/+12 | |
| interrupts before running algorithms. | |||||
| 2017-01-25 | riscv: Globally disable interrupts when running algorithms. | Megan Wachs | 1 | -0/+12 | |
| 2016-12-24 | Merge pull request #11 from sifive/malloc_off_by_1 | Tim Newsome | 1 | -1/+1 | |
| Correct off by 1 in malloc | |||||
| 2016-12-23 | Correct off by 1 in malloc, which causes this to fail on macOS (and in ↵ | mwachs5 | 1 | -1/+1 | |
| theory on any platform). | |||||
| 2016-12-19 | Merge pull request #9 from sifive/increase_as_size | Tim Newsome | 1 | -1/+1 | |
| riscv: Increase the number of Algorithm Steps | |||||
| 2016-12-18 | riscv: Increase the number of Algorithm Steps | Megan Wachs | 1 | -1/+1 | |
| 2016-12-08 | Merge pull request #7 from sifive/temp_verify_blank_check | Tim Newsome | 1 | -0/+30 | |
| riscv: implement skeletons for Memory Blank Check and CRC. | |||||
| 2016-12-07 | riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you ↵ | Megan Wachs | 1 | -0/+30 | |
| just get a segfault when attempting to perform these actions. | |||||
| 2016-12-01 | Fix issue #6: build failure on gcc 6 | Tim Newsome | 1 | -1/+1 | |
| Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078 | |||||
| 2016-11-30 | Merge pull request #5 from sifive/format-warning | Tim Newsome | 1 | -1/+1 | |
| Use portable format specifier for size_t | |||||
| 2016-11-30 | Use portable format specifier for size_t | Albert Ou | 1 | -1/+1 | |
| This fixes a gcc warning [-Werror=format] on an i686-pc-linux-gnu host, which defines size_t as unsigned int instead of long int. | |||||
| 2016-11-30 | Merge pull request #4 from sifive/mwachs5-patch-sckdiv | Megan Wachs | 1 | -4/+0 | |
| Don't write SCKDIV when flashing | |||||
| 2016-11-27 | Don't write SCKDIV when flashing | Megan Wachs | 1 | -4/+0 | |
| The target may have already configured its clock to run at a higher frequency and would have set SCKDIV and other dividers at that time. Don't restore the SCKDIV to its default or the flash interface may run too fast and programming will fail. Otherwise, the default value is fine and there is no need to write SCKDIV. | |||||
| 2016-11-27 | Add timeout to infinite loop. | Tim Newsome | 1 | -1/+13 | |
| Change-Id: I7d005b4779154b4dfe8c9a26f4f0e351f426df9b | |||||
| 2016-11-25 | Add some timeouts that I ran into. | Tim Newsome | 1 | -11/+48 | |
| Change-Id: I8eeb1c934ceead0d99dcdc618a3f8aa351119cb0 | |||||
| 2016-11-25 | Cope better if the target unexpectedly resets. | Tim Newsome | 1 | -4/+11 | |
| Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9 | |||||
| 2016-11-23 | Fix typo. | Tim Newsome | 1 | -1/+1 | |
| Change-Id: If04ba1103817f772fe55659cb3b5b4533c734f2a | |||||
| 2016-11-19 | Merge branch 'sifive/add_issi_flash' into riscv | Tim Newsome | 1 | -1/+1 | |
| 2016-11-19 | Fix off-by-one error in assert. | Tim Newsome | 1 | -1/+1 | |
| Change-Id: I86447c747a212175be560170378c655ac801f5a6 | |||||
| 2016-11-19 | Add the ISSI SPI Flash to the list | Megan Wachs | 1 | -1/+1 | |
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index : riscv-openocd.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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