aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-01-23arm_adi_v5: fix and update sequences to spec IHI 0031EAntonio Borneo1-16/+110
Fix the SWD line reset sequence accordingly to Arm specification IHI 0031E that requires at least 2 idle clocks after the 50 clocks with SWDIO high. Fix the value of the activation code in the (currently unused) sequence dormant-to-SWD. Make each sequence's length multiple of 8, so it is compatible with adapters that have such limitation (e.g. buspirate) and try to split and comment each part of the sequence (when possible keep each part byte aligned, inspired from commit 3ef9beb52cd0). This slightly increases the sequence length but does not impact run-time performance because these are rarely used sequences. Add the missing sequence dormant-to-JTAG and JTAG-to-dormant, not used yet. On devices that implements the dormant state, IHI 0031E deprecates the direct switching between SWD and JTAG, and recommends using a transition through dormant. This is not implemented. Change-Id: Iad18c0e736cfd9366be175d22658d664b0c61eab Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4851 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-23target/arm_dap: fix segmentation fault in 'dap info' cmdTomas Vanek1-0/+5
'dap info' command fails hard on a hla target. Change-Id: Ia188b1afe527e0ed64512d1bddadd507f978e40b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4860 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-22Move version check until after dmactive=1.Tim Newsome1-10/+10
This should allow OpenOCD to work with targets where version is not readable when dmactive=0, which is allowed by the spec.
2019-01-21nrf5: add nrf5 device definition for HWID 0x00E3Mirko Vogt1-0/+1
This hardware id is e.g. used by the Insight SiP ISP1507-AX. Change-Id: I82568d292f9882372ab061d8e3e36906b0cc5882 Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com> Reviewed-on: http://openocd.zylin.com/4845 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2019-01-18Halt all SMP harts on halt request.Tim Newsome1-8/+20
38/45 tests pass. Change-Id: Ia4fd523139c197020d9277be4bf5f92079520068
2019-01-18Don't reset current thread id on single step.Tim Newsome1-13/+20
Now passing 36/45 tests. Change-Id: I244b045f84397b058cf526e3bff238cb05d8ad06
2019-01-17Fix reading of non-general registers for hwthreadTim Newsome8-12/+102
Previously the code made the assumption (which is valid for conventional RTOSs) that special registers (e.g. CSRs) are the same across threads. 26/45 tests pass. Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-16cortex_m: fix bug in poll() machine state (external resume awareness)Tarek BOCHKATI1-0/+11
This patch covers the fact that cortex_m could be resumed externally by Cross Trigger Interface or by direct write to DHSCR ... To reproduce: - halt the target - then run the core through DHCSR (mww 0xe000edf0 0xa05f0001) => this resumes the core, but target state in OpenOCD remains HALTED. Change-Id: Ifa1ae18645bfeb863acc78a039bbf04873fd78fe Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4817 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-16cortex_a_poll: minor code factorization to enhance readabilityTarek BOCHKATI1-24/+11
cortex_a_debug_entry and update_halt_gdb are called in two consecutive conditions which are complementary, so externalizing the common code makes the conditions' body lighter With the removal of LOG_DEBUG(" ") since it does not look too informative Change-Id: I0c54e413619576bb3af164f2dcf256c5a862c5fd Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4832 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2019-01-16at91samd: added SAM-DA1 partsSeverin Junker1-0/+22
Change-Id: I1b206461052ee1897432e379505fdf95372a9e24 Signed-off-by: Severin Junker <s.junker@cartelsol.com> Reviewed-on: http://openocd.zylin.com/4835 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-16helper/command: check for malloc failure in __command_nameAntonio Borneo1-3/+6
If malloc fails in __command_name, the following strcpy will segfault, thus preventing __command_name to return. The actual calls to command_name() implement the correct check for the NULL pointer, but propagate error -ENOMEM, that is not an error value coherent within OpenOCD. Plus, in one case it overwrites an already detected error. Check the pointer returned by malloc and, in case of failure, issue an error message and return the NULL pointer. Let the caller of command_name() to keep the already detected error or to return ERROR_FAIL in case of end of memory. Change-Id: I151a24569409777dd5bc09a3daf5dba2b8e2829b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4838 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-14target/stm8: add missing destroy_reg_param()Tomas Vanek1-0/+1
Change-Id: Ibd8a423a4400226790cfbb9a6f113b7ea762c436 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4814 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Ake Rehnman <ake.rehnman@gmail.com>
2019-01-14drivers/sysfsgpio: fix usage messagesAntonio Borneo1-2/+10
The notation "(tck tms tdi tdo)* " is incorrect, because it means the quadruple of gpio can be repeated on the command-line. The correct syntax of the command requires instead to provide either all the four gpio numbers (in order to set the values) or to pass an empty command-line (to dump the values previously set). Change the .usage field to "[tck tms tdi tdo]". Change similarly the corresponding .usage field for SWD command. Add the .usage field for the commands that individually set each gpio. Change-Id: If5b3c618097b71dfe7fcf988fb3c1499ae03a6d5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4833 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-11rtos support to write registers on current threadTim Newsome4-61/+93
I don't understand how it was ever possible to change the registers on a thread that's not the current active one when a halt happened. Really instead of the RTOS tracking what the currently selected thread is, it would make more sense to have gdb_server do that and simply pass it along in every call to the RTOS layer. Now MulticoreRegTest passes. Change-Id: I399b9b2b05a147aa6b41463714ed3a39534b1fc8
2019-01-11Add flash support for SiFive's Freedom E platformsTim Newsome8-6/+1215
Valgrind and Clang Static Analyzer have no complaints about this change. Change-Id: I7757615ec52448372bdc57729cdf97c7016d97e8 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4656 Tested-by: jenkins Reviewed-by: Philipp Guehring <pg@futureware.at> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-11Merge pull request #345 from darius-bluespec/set_irTim Newsome4-16/+49
Add 'riscv set_ir' command to set IR value for JTAG registers.
2019-01-10Clean up register caching a little.Tim Newsome2-19/+29
Change-Id: Id039aedac44d9c206ac4bd30eb3ef754e190c3fe
2019-01-09Add 'riscv set_ir' command to set IR value for JTAG registers.Darius Rad4-16/+49
This allows using different TAP addresses, for example, if using BSCANE2 primitives on a Xilinx FPGA.
2019-01-09Merge pull request #344 from riscv/idleTim Newsome4-111/+197
Deal with DMI busy in block reads/writes
2019-01-08Add comment for reset_delays_wait.Tim Newsome4-34/+18
Also refactor so there's just one of them in riscv, instead of one for 0.11 and one for 0.13. Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
2019-01-08stlink_usb: Submit multiple USB URBs at once to improve performanceAustin Phillips1-2/+201
Commands to stlink devices are typically comprised of multiple transactions with each transaction completing before moving to the next. This change allows for multiple USB transactions to be issued at once followed by a check that all transactions completed successfully. This improves performance on some machines where there is a large turn-around time between USB transfers such as is seen on some virtual machines. This change is only supported when compiled with libusb1 as libusb1 supports and asynchronous interface. Multi-transaction queueing introduced in this change paves the way for improving speed of other transactions in the future such as memory and register reads where multiple USB transactions in succession are required to complete a command. Multiple USB transactions can be submitted at once using jtag_libusb_bulk_transfer_n function. Change-Id: I924e049217a789ef445b14e00aa1983576970fbf Signed-off-by: Austin Phillips <austin_phillips@hotmail.com> Reviewed-on: http://openocd.zylin.com/4484 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-08libusb: add debug message on adapter not found due to wrong serialAntonio Borneo2-0/+14
When few adapters of the same type are in use, the serial string is the way to select the right one. Currently a serial string that does not match any of the connected adapters will just fail the open, without specific information to track the issue. Add a specific message to highlight that the open failure is caused by a serial mismatch. Change-Id: I5cb77f1045cc746e532d395b2e5ced40a23ab638 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4701 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08jtag/drivers/usb_common: return oocd error valuesAntonio Borneo1-4/+7
Where possible, keep the same style for returning error. Change-Id: I3a04220c0b9f129a36e9fe83038b7c19dd57fe61 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4699 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08libusb0: return oocd error valuesAntonio Borneo1-3/+3
Commit d1b74376336814266236054f925a9964b87dd8a5 fixes libusb1 to return OpenOCD error values instead of negative errors in Linux kernel's style. The same fix should be applied to libusb0 too. Fix return value of libusb0 to uniform it to OpenOCD style. Change-Id: I68478c29c91c6be720074f58c432fe51477e03ed Fixes: d1b743763368 ("libusb: return oocd error values") Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4698 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08target/aarch64: add support for multi-architecture gdbAntonio Borneo3-0/+7
GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. aarch64-linux-gnu-gdb 8.2 uses "aarch64" as default architecture, but also supports the value "aarch64:ilp32" and all the values supported by arm-none-eabi-gdb. These values can be displayed on arm gdb prompt by typing "set architecture " followed by a TAB for autocompletion. Set the gdb architecture value for aarch64 target to "aarch64". Change-Id: I63e9769f47d8e73f048eb84fa73e082dd1c8e52c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4755 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08target/arm: add support for multi-architecture gdbAntonio Borneo16-0/+31
GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. arm-none-eabi-gdb 8.2 uses "arm" as default architecture, but also supports the following values: "arm_any", "armv2", "armv2a", "armv3", "armv3m", "armv4", "armv4t", "armv5", "armv5t", "armv5te", "armv5tej", "armv6", "armv6k", "armv6kz", "armv6-m", "armv6s-m", "armv6t2", "armv7", "armv7e-m", "armv8-a", "armv8-m.base", "armv8-m.main", "armv8-r", "ep9312", "iwmmxt", "iwmmxt2", "xscale". These values can be displayed on arm gdb prompt by typing "set architecture " followed by a TAB for autocompletion. Set the gdb architecture value for all arm targets to "arm". Change-Id: I176cb89878606e1febd546ce26543b3e7849500a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4754 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08target/stm8: add support for multi-architecture gdbAntonio Borneo1-0/+6
GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. The gdb patches for stm8 are still not merged in the official repository and are temporarily hosted in https://stm8-binutils-gdb.sourceforge.io/ The latest patch set stm8-binutils-gdb-sources-2018-03-04.tar.gz define only one possible value ("stm8") for this architecture; it can be displayed typing "set architecture " followed by a TAB for autocompletion in gdb for stm8. Set the gdb architecture value for stm8 to "stm8". Change-Id: I643ceba662de46cecf061d1dc672b9178a077f1b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4753 Tested-by: jenkins Reviewed-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08armv7m: always set xPSR.T=1 when starting an algorithmCody P Schafer1-0/+17
xPSR.T sets the processor to Thumb mode when set to 1. ARMv7-M only supports execution of Thumb instructions, so it must always be set to 1. If xPSR.T is set to 0 on armv7m, a usage fault is generated when a instruction execution is attempted. On armv7m, issuing a reset causes the vector table to be examined. PC and xPSR.T are loaded from the vector table at byte offset 4. xPSR.T is taken from the least significant bit this value, PC from the remaining bits. This occurs even with `reset halt`, as the reset itself causes this load to occur without the execution of any instructions. As a result of this, following a reset with a "bad" value programmed in the vector table, openocd would be unable to run algorithms on the target, as running them would immediately result in a usage fault due to xPSR.T being unset (0). Allow algorithms to run regardless of the content of the vector table by explicitly setting xPSR so that xPSR.T=1 prior to executing an algorithm. One can think of this as openocd more closely emulating a reset or branch instruction in executing it's algorithms. Ticket: https://sourceforge.net/p/openocd/tickets/203/ Signed-off-by: Cody P Schafer <openocd@codyps.com> Change-Id: I4dc3427ab195d06c3fd780ea768027fefccc4c28 Reviewed-on: http://openocd.zylin.com/4658 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08icepick.cfg: add cancel reset bit to TAP register writesEdward Fewell1-3/+3
The Agama family of devices (CC26x2/CC13x2) required an additional bit to be set when adding the core's TAP into the scan chain. The cancel reset bit 0x10000 tells the ICEPick to take the bus out of reset so that the other bits will take effect. This bit is a NOP on other devices and ICEPicks, so the change shouldn't adversely affect other devices. Change-Id: I9245eef0936ea7eea28ae84ab5e8ce05fa63af40 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4789 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08drivers: xds110: Add support for XDS110 stand-alone probeEdward Fewell2-1/+90
The XDS110 stand-alone version has the ability to supply voltage to the target board via it's AUX FUNCTIONS port. Added command to enable setting the voltage on the XDS110 stand-alone. Change-Id: I2f21c4a3d15ed99e649f3a83973c5e724c4bfeb6 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4793 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-08HACKING: add note about refs/for/masterJerome Forissier1-0/+4
The fact that one needs to always push contributions to a single remote reference (refs/for/master) might seem odd to people unfamiliar with Gerrit. GitHub, for instance, hosts personal repositories where developers typically create topic branches for each contribution and use a proprietary mecanism to request a review (the "pull request"). More generally, one normally does not expect to be able to push non-fast-forwarding stuff to a remote branch. This commit adds a clarifying note to the patch guidelines. Change-Id: Ia750b815b82b18e92b6109c07f451000dcbecf9b Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-on: http://openocd.zylin.com/4806 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-01-08HACKING: replace refs/publish/master with refs/for/masterJerome Forissier2-3/+3
refs/publish/master is deprecated and gives a warning in newer Gerrit. Replace with refs/for/master. Change-Id: I56871cc6e80c014ba81f4458230cd67dc318ecb3 Suggested-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-on: http://openocd.zylin.com/4810 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-01-07Make riscv_get_gdb_reg_list read the registers.Tim Newsome1-0/+13
This may not be the correct behavior, but it gets me further through the tests. Change-Id: I6e9b77e927700de706b6ece723f4d530fa566761
2019-01-07Clean up debug printf.Tim Newsome1-2/+2
I only need to see 64 bits of PC if the high bits are non-zero. Change-Id: I29397791da1e3f1705e573b2eaafc3eac202e178
2019-01-07Handler target_get_gdb_reg_list() better.Tim Newsome1-0/+1
That function might change from NULL reg_list but then return failure. In that case reg_list shouldn't be freed. Change-Id: I5380630c871d056fb52e25bda16836e346bd74b2
2019-01-07Implement hwthread_get_thread_reg_list.Tim Newsome1-4/+22
MulticoreRegTest now gets past the first check on all GPRs. Change-Id: I35f3c51273542668985f7a86965c1e947fc12194
2019-01-03WIP make riscv work with -rtos hwthread.Tim Newsome1-2/+23
Change-Id: I37bb16291fa87a83f21e5fd8bad53492a4d69425
2019-01-03Neuter hwthread_get_thread_reg_list so it buildsTim Newsome1-66/+6
Change-Id: I07cf72ea1874ca7cb5557677ecb751c931174419
2019-01-02NOR: lpc2000 Add support for LPC84x devicesRod Boyce4-3/+51
These devices differ from LPC8xx devices in that they have a different IAP entry point, but everything else is the same. Using Tcl to pass different IAP entry point. no new Clang analyser warnings and no new build sanitizers issues. Change-Id: I2d654dd250f416e74262c0228cad8713a283402f Signed-off-by: Rod Boyce <developer@teamboyce.co.uk> Reviewed-on: http://openocd.zylin.com/4684 Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-02flash: nor: ath79: remove base calculationOleksij Rempel6-20/+6
Currently it is impossible to flash ELF with correct offsets. The reason is a bogus offset calculation extracted from base. Since any other spi drivers do not care about base, do the same for ath79 as well. Change-Id: I9e46e01c9e7a709c2d07da9203c634f302603afd Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4821 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-02flash/nor/nrf5: set correct timeout for nvmc operationsJānis Skujenieks1-1/+1
Longest erase all FLASH for nRF5 series is 295.3 ms for nRF52832. Timeout period now is set to 340 ms (295.3 + 15%) Change-Id: Iae00ed7b634f111b9798db11e35e4e066d4aaa95 Signed-off-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-on: http://openocd.zylin.com/4822 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-02rtos/hwthread: add hardware-thread pseudo rtosMatthias Welwarsky4-51/+464
This patch adds "hwthread", a pseudo rtos that represents cpu cores in an SMP system as threads to gdb. This allows to debug SMP system kernels in a more sensible manner and removes the current atrocities of switching gdb manually between CPU cores to update the context. Change-Id: Ib781c6c34097689d21d9e02011e4d74a4a742379 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Source: http://openocd.zylin.com/#/c/3999
2019-01-02Fix typo.Tim Newsome1-1/+1
Change-Id: Ibdd26c5c524b10a3518fe708e9b7fc917b0cb1b6
2018-12-31Merge pull request #335 from aka-sps/merge-master-to-riscvTim Newsome0-0/+0
Merge master to riscv
2018-12-27target/arm_cti : export CTI APPPULSE and INACK registerTarek BOUCHKATI1-1/+3
this permits the full control of CTI from config files Change-Id: Ia27ac8e12e08ec72da05f26dcbd81d24fa1a0f6f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4815 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-12-27target/arm_cti: add debug message when an incorrect CTI register name is usedTarek BOCHKATI1-2/+4
the patch also contains some typo fixes Change-Id: Ia4267036068455144cdcbfdffed15518d48f445e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4816 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-12-25command: Log the failed command nameJean-Christian de Rivaz1-1/+1
Change-Id: I03938a845110002755636a9514b17a213bf1cc72 Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4808 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2018-12-23Add LPC8Nxx and NHS3xx support.Jean-Christian de Rivaz4-4/+113
Change-Id: I0bdbca8dd9b234aca355230af7269463c9f70bd1 Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4515 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-12-21add w600 supportSimon Qian4-0/+404
w600 is a wifi soc from winner micro(www.winnermicro.com). Change-Id: Ib8ccd6e52baefca6547fb97d29db75db0ee73948 Signed-off-by: Simon Qian <versaloon@simonqian.com> Reviewed-on: http://openocd.zylin.com/4801 Tested-by: jenkins Reviewed-by: yichen <wdyichen@wdyichen.cn> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-12-19flash/nor/spi: add adesto AT25DF081ATomas Vanek1-0/+1
8Mbit SPI flash on SAM D21 Xplained board Change-Id: Iec087f5d889c1cbdd4fed90863e73511f6101cec Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4802 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.1 at 2024-10-12 16:03:35 +0000