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2018-02-08Applied fence.i fix on memory write to v20171231 releasefence_i_fix_for_releaseGleb Gagarin1-1/+25
2017-12-29Merge pull request #168 from gnu-mcu-eclipse/sifive-cfgv20171231Tim Newsome3-0/+78
Add config files for the SiFive boards
2017-12-29add configs for the SiFive boardsLiviu Ionescu3-0/+78
- the HiFive1 board definition includes the FTDI interface - the Arty boards require external interface definitions
2017-12-28Merge pull request #167 from riscv/sifive_cfgTim Newsome3-0/+96
Add config files for SiFive RISC-V hardware.
2017-12-28Merge pull request #165 from riscv/typoTim Newsome1-1/+1
Fix typo.
2017-12-28Add config files for SiFive RISC-V hardware.Tim Newsome3-0/+96
Copied from https://github.com/gnu-mcu-eclipse/openocd Change-Id: Ia0b3e192ca8b3bae6035623d605c9980e9bccd2c
2017-12-28Fix typo.Tim Newsome1-1/+1
Issue #164 Change-Id: I083ba0d7df72a83a802297baa25753f8d274519a
2017-12-27Merge pull request #163 from riscv/no_abortTim Newsome5-54/+77
Get rid of abort() calls.
2017-12-27Get rid of abort() calls.Tim Newsome5-54/+77
Also changed a few asserts that could trigger due to broken hardware. Fixes Issue #142. Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27Merge pull request #162 from riscv/no_abortTim Newsome3-34/+62
Propagate error instead of calling abort().
2017-12-26Propagate error instead of calling abort().Tim Newsome3-34/+62
As part of this I improved the memory read/write fatal error handling a bit. Now at least we try to leave autoexec turned off, and will even restore the temp registers if the situation isn't too hosed for that. Partly addresses Issue #142 Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26Merge pull request #161 from riscv/dead_codeTim Newsome2-18/+0
Remove unused code.
2017-12-26Remove unused code.Tim Newsome2-18/+0
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26Merge pull request #160 from riscv/styleTim Newsome16-735/+848
Conform to OpenOCD style guide.
2017-12-26Conform to OpenOCD style guide.Tim Newsome16-735/+848
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26Merge pull request #159 from riscv/updateTim Newsome109-906/+5299
Merge changes from master
2017-12-22Merge branch 'master' into updateTim Newsome109-906/+5299
Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
2017-12-22Merge pull request #156 from riscv/fespiTim Newsome2-15/+20
fix fespi flash after registers were renamed.
2017-12-21Fix flash/run algorithm with new register namesTim Newsome2-5/+8
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21Make functions static. Free memory.Tim Newsome1-10/+12
Change-Id: Iadf7b2a926d6d5abc4c8daa2f5620886bcb09b31
2017-12-21Merge pull request #155 from riscv/debug_definesMegan Wachs1-22/+48
Update debug_defines to the one used with spike.
2017-12-21Merge pull request #148 from riscv/macbuildMegan Wachs1-1/+1
Use %ll instead of %L in scanf.
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21Merge pull request #145 from riscv/rbb_winTim Newsome3-8/+40
Fix Windows build
2017-12-21Merge pull request #151 from riscv/use_parenTim Newsome1-1/+1
Use parens after if.
2017-12-21Use parens after if.Tim Newsome1-1/+1
I'm surprised this built with gcc before. Fixes Issue #150. Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-20config for ESPRESSObin from Globalscale Tech. Inc.Jiri Kastner1-0/+7
Change-Id: I77f536a9d2e901ebcef0a7dd0f205e5332b1d382 Signed-off-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/4303 Tested-by: jenkins Reviewed-by: Forest Crossman <cyrozap@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-12-20configs for Marvell Armada 3700Jiri Kastner3-0/+78
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd Signed-off-by: Jiri Kastner <cz172638@gmail.com> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/4302 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-19Merge pull request #149 from riscv/xml_registersTim Newsome8-361/+583
Send gdb an XML target description that contains only a list of registers we think exist on this target
2017-12-19Add `riscv expose_csrs` command.Tim Newsome1-0/+110
This lets users tell OpenOCD which non-standard CSRs exist on their target, that will also be accessible and whose existence will be communicated to gdb. Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19Hide supervisor registers if there is no S mode.Tim Newsome2-28/+32
Also update encoding.h. Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19Give FPRs ABI names.Tim Newsome2-2/+67
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19Remove some debug printfs.Tim Newsome1-2/+0
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19Avoid another assertion failure.Tim Newsome1-1/+5
Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19Read misa before using it to check for extensions.Tim Newsome1-1/+2
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19Don't rely on hart count until it's correct.Tim Newsome1-1/+1
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19Remove no-longer-true comment.Tim Newsome1-1/+0
Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19Simplify examine()Tim Newsome1-43/+13
Now we don't have to play tricks fooling other parts of our code that might assert. Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19Make priv register 8 bits.Tim Newsome1-0/+1
(It's really only 2 bits, but something wonky happens between gdb and OpenOCD if I make it that size.) Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19WIP xml register for 0.11.Tim Newsome4-392/+290
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of 0x40001105. Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19Hide unknown registers, which probably don't existTim Newsome2-13/+21
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19Fix register names.Tim Newsome5-46/+108
Use the ABI ones for every register that we have one for. Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19WIP better CSR names, and include only existingTim Newsome1-1/+32
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19WIP. Hide FPRs if the hart doesn't support F/D.Tim Newsome2-23/+31
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19`make all` debug tests now pass.Tim Newsome3-73/+106
Also properly support (I think) D extension on RV32. Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19Checkpoint that seems to work.Tim Newsome1-0/+30
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-15Use %ll instead of %L instead of scanf.macbuildTim Newsome1-1/+1
Mac build barfs on L, and the manpage says they're equivalent. Hopefully fixes #147 Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-14Merge pull request #146 from riscv/scratch_ramTim Newsome1-1/+1
Fix cut and paste bug.
2017-12-14Fix cut and paste bug.Tim Newsome1-1/+1
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work. Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14Use abstraction because Windows is not POSIXTim Newsome2-2/+13
Fixes #138 Change-Id: I4d9b49762e318fe91f1561ed315829b43daefef4
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