diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/at91sam9260_ext_RAM_ext_flash.cfg | 31 |
1 files changed, 12 insertions, 19 deletions
diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index d2bf66f..535ae0f 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -1,8 +1,4 @@ - - - -adapter_khz 4 - +jtag_rclk 4 ###################################### # Target: Atmel AT91SAM9260 @@ -44,26 +40,29 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs -$_TARGETNAME invoke-event halted - # Internal sram1 memory $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1 scan_chain -$_TARGETNAME configure -event reset-deassert-post {at91sam_init} +$_TARGETNAME configure -event reset-start { + # at reset chip runs at 32khz + jtag_rclk 8 +} +$_TARGETNAME configure -event reset-init {at91sam_init} # Flash configuration #flash bank <name> cfi <base> <size> <chip width> <bus width> <target> set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME +# Faster memory downloads. This is disabled automatically during +# reset init since all reset init sequences are too short for +# fast memory access +arm7_9 dcc_downloads enable +arm7_9 fast_memory_access enable proc at91sam_init { } { - - # at reset chip runs at 32khz - adapter_khz 8 - halt mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog @@ -79,16 +78,13 @@ proc at91sam_init { } { sleep 10 # wait 10 ms # Now run at anything fast... ie: 10mhz! - adapter_khz 10000 # Increase JTAG Speed to 6 MHz - arm7_9 dcc_downloads enable # Enable faster DCC downloads + jtag_rclk 10000 # Increase JTAG Speed to 6 MHz mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0 mww 0xffffec08 0x00160016 # SMC_CYCLE0 mww 0xffffec0c 0x00161003 # SMC_MODE0 - flash probe 0 # Identify flash bank 0 - mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 @@ -123,6 +119,3 @@ proc at91sam_init { } { mww 0x20000000 0 mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us } - - - |