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-rw-r--r--tcl/cpld/xilinx-xcu.cfg72
1 files changed, 72 insertions, 0 deletions
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
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+# Xilinx Ultrascale (Kintex, Virtex, Zynq)
+# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xcu
+}
+
+# The cvarious chips in the Ultrascale family have different IR length.
+# Set $CHIP before including this file to determine the device.
+array set _XCU_DATA {
+ XCKU025 {0x03824093 6}
+ XCKU035 {0x03823093 6}
+ XCKU040 {0x03822093 6}
+ XCKU060 {0x03919093 6}
+ XCKU095 {0x03844093 6}
+ XCKU3P {0x04A63093 6}
+ XCKU5P {0x04A62093 6}
+ XCKU9P {0x0484A093 6}
+ XCKU11P {0x04A4E093 6}
+ XCKU13P {0x04A52093 6}
+ XCKU15P {0x04A56093 6}
+ XCVU065 {0x03939093 6}
+ XCVU080 {0x03843093 6}
+ XCVU095 {0x03842093 6}
+ XCVU3P {0x04B39093 6}
+ XCKU085 {0x0380F093 12}
+ XCKU115 {0x0390D093 12}
+ XCVU125 {0x0392D093 12}
+ XCVU5P {0x04B2B093 12}
+ XCVU7P {0x04B29093 12}
+ XCVU160 {0x03933093 18}
+ XCVU190 {0x03931093 18}
+ XCVU440 {0x0396D093 18}
+ XCVU9P {0x04B31093 18}
+ XCVU11P {0x04B49093 18}
+ XCVU13P {0x04B51093 24}
+}
+
+if { ![info exists CHIP] } {
+ error "set CHIP to one of "[concat [array names _XCU_DATA]]
+}
+
+if { ![llength [array names _XCU_DATA $CHIP]] } {
+ error "unknown CHIP: "$CHIP
+}
+
+set _EXPID [lindex $_XCU_DATA($CHIP) 0]
+set _IRLEN [lindex $_XCU_DATA($CHIP) 1]
+
+# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
+jtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID
+
+pld device virtex2 $_CHIPNAME.tap 1
+
+set XCU_JSHUTDOWN 0x0d
+set XCU_JPROGRAM 0x0b
+set XCU_JSTART 0x0c
+set XCU_BYPASS 0x3f
+
+proc xcu_program {tap} {
+ global XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS
+ irscan $tap $XCU_JSHUTDOWN
+ irscan $tap $XCU_JPROGRAM
+ runtest 60000
+ #JSTART prevents this from working...
+ #irscan $tap $XCU_JSTART
+ runtest 2000
+ irscan $tap $XCU_BYPASS
+ runtest 2000
+}