diff options
Diffstat (limited to 'tcl/board')
29 files changed, 244 insertions, 22 deletions
diff --git a/tcl/board/gti/espressobin.cfg b/tcl/board/gti/espressobin.cfg new file mode 100644 index 0000000..20d0452 --- /dev/null +++ b/tcl/board/gti/espressobin.cfg @@ -0,0 +1,7 @@ +# config for ESPRESSObin from +# Globalscale Technologies Inc. + +# srst is isolated through missing resistor +reset_config trst_only + +source [find target/marvell/88f3720.cfg] diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg index 1051c25..db3cb03 100644 --- a/tcl/board/openrd.cfg +++ b/tcl/board/openrd.cfg @@ -3,6 +3,8 @@ source [find interface/ftdi/openrd.cfg] source [find target/feroceon.cfg] +adapter_khz 2000 + $_TARGETNAME configure \ -work-area-phys 0x10000000 \ -work-area-size 65536 \ diff --git a/tcl/board/st_nucleo_f0.cfg b/tcl/board/st_nucleo_f0.cfg index e9fda19..e6a03bb 100644 --- a/tcl/board/st_nucleo_f0.cfg +++ b/tcl/board/st_nucleo_f0.cfg @@ -6,7 +6,7 @@ # STM32F091RC # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_f103rb.cfg b/tcl/board/st_nucleo_f103rb.cfg index 71a92f7..e1990dc 100644 --- a/tcl/board/st_nucleo_f103rb.cfg +++ b/tcl/board/st_nucleo_f103rb.cfg @@ -1,7 +1,7 @@ # This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip. # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_f3.cfg b/tcl/board/st_nucleo_f3.cfg index 9dffdcb..fec612b 100644 --- a/tcl/board/st_nucleo_f3.cfg +++ b/tcl/board/st_nucleo_f3.cfg @@ -1,7 +1,7 @@ # This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip. # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_f4.cfg b/tcl/board/st_nucleo_f4.cfg index b5a78c1..11f6f87 100644 --- a/tcl/board/st_nucleo_f4.cfg +++ b/tcl/board/st_nucleo_f4.cfg @@ -4,7 +4,7 @@ # STM32F411RET6 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg new file mode 100644 index 0000000..baedeb6 --- /dev/null +++ b/tcl/board/st_nucleo_h743zi.cfg @@ -0,0 +1,10 @@ +# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip. +# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html + +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only diff --git a/tcl/board/st_nucleo_l1.cfg b/tcl/board/st_nucleo_l1.cfg index 56e2756..d97eb7c 100644 --- a/tcl/board/st_nucleo_l1.cfg +++ b/tcl/board/st_nucleo_l1.cfg @@ -1,7 +1,7 @@ # This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip. # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_l476rg.cfg b/tcl/board/st_nucleo_l476rg.cfg index 2baa34e..4426c3b 100644 --- a/tcl/board/st_nucleo_l476rg.cfg +++ b/tcl/board/st_nucleo_l476rg.cfg @@ -1,7 +1,7 @@ # This is a ST NUCLEO L476RG board with a single STM32L476RGT6 chip. # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF261636 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm320518_eval_stlink.cfg b/tcl/board/stm320518_eval_stlink.cfg index ce074cb..a7fef07 100644 --- a/tcl/board/stm320518_eval_stlink.cfg +++ b/tcl/board/stm320518_eval_stlink.cfg @@ -4,7 +4,7 @@ # # This is for using the onboard STLINK/V2 -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm3220g_eval_stlink.cfg b/tcl/board/stm3220g_eval_stlink.cfg index 43a4df9..b58e42f 100644 --- a/tcl/board/stm3220g_eval_stlink.cfg +++ b/tcl/board/stm3220g_eval_stlink.cfg @@ -4,7 +4,7 @@ # # This is for using the onboard STLINK/V2 -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg index 9c7ad5d..b1c54a2 100644 --- a/tcl/board/stm3241g_eval_stlink.cfg +++ b/tcl/board/stm3241g_eval_stlink.cfg @@ -4,7 +4,7 @@ # # This is for using the onboard STLINK/V2 -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32429i_eval_stlink.cfg b/tcl/board/stm32429i_eval_stlink.cfg index 2b51cea..010d371 100644 --- a/tcl/board/stm32429i_eval_stlink.cfg +++ b/tcl/board/stm32429i_eval_stlink.cfg @@ -4,7 +4,7 @@ # # This is for using the onboard STLINK/V2 -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32439i_eval_stlink.cfg b/tcl/board/stm32439i_eval_stlink.cfg index 5995fb1..b722ce6 100644 --- a/tcl/board/stm32439i_eval_stlink.cfg +++ b/tcl/board/stm32439i_eval_stlink.cfg @@ -4,7 +4,7 @@ # # This is for using the onboard STLINK/V2 -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f0discovery.cfg b/tcl/board/stm32f0discovery.cfg index bae9a69..e2b5e38 100644 --- a/tcl/board/stm32f0discovery.cfg +++ b/tcl/board/stm32f0discovery.cfg @@ -1,7 +1,7 @@ # This is an STM32F0 discovery board with a single STM32F051R8T6 chip. # http://www.st.com/internet/evalboard/product/253215.jsp -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f3discovery.cfg b/tcl/board/stm32f3discovery.cfg index 5a17b4c..9bb62f5 100644 --- a/tcl/board/stm32f3discovery.cfg +++ b/tcl/board/stm32f3discovery.cfg @@ -1,7 +1,7 @@ # This is an STM32F3 discovery board with a single STM32F303VCT6 chip. # http://www.st.com/internet/evalboard/product/254044.jsp -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f429disc1.cfg b/tcl/board/stm32f429disc1.cfg index 9d3cdd7..c0bceba 100644 --- a/tcl/board/stm32f429disc1.cfg +++ b/tcl/board/stm32f429disc1.cfg @@ -3,7 +3,7 @@ # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 # -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f429discovery.cfg b/tcl/board/stm32f429discovery.cfg index e06d2a5..7aef09d 100644 --- a/tcl/board/stm32f429discovery.cfg +++ b/tcl/board/stm32f429discovery.cfg @@ -3,7 +3,7 @@ # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 # -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f469discovery.cfg b/tcl/board/stm32f469discovery.cfg index 63b1363..a9559a7 100644 --- a/tcl/board/stm32f469discovery.cfg +++ b/tcl/board/stm32f469discovery.cfg @@ -3,7 +3,7 @@ # http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395 # -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f4discovery.cfg b/tcl/board/stm32f4discovery.cfg index 963e0f9..60b7f42 100644 --- a/tcl/board/stm32f4discovery.cfg +++ b/tcl/board/stm32f4discovery.cfg @@ -1,7 +1,7 @@ # This is an STM32F4 discovery board with a single STM32F407VGT6 chip. # http://www.st.com/internet/evalboard/product/252419.jsp -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg index 085340f..7d1bc96 100755 --- a/tcl/board/stm32f7discovery.cfg +++ b/tcl/board/stm32f7discovery.cfg @@ -2,7 +2,7 @@ # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641 # This is for using the onboard STLINK/V2-1 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg new file mode 100644 index 0000000..2949ded --- /dev/null +++ b/tcl/board/stm32h7x3i_eval.cfg @@ -0,0 +1,13 @@ +# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards. +# This is an ST EVAL-H743XI board with single STM32H743XI chip. +# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html +# This is an ST EVAL-H753XI board with single STM32H753XI chip. +# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html + +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32h7x_dual_bank.cfg] + +reset_config srst_only diff --git a/tcl/board/stm32l0discovery.cfg b/tcl/board/stm32l0discovery.cfg index a035062..aabbf81 100644 --- a/tcl/board/stm32l0discovery.cfg +++ b/tcl/board/stm32l0discovery.cfg @@ -1,7 +1,7 @@ # This is an STM32L053 discovery board with a single STM32L053 chip. # http://www.st.com/web/en/catalog/tools/PF260319 -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32l4discovery.cfg b/tcl/board/stm32l4discovery.cfg index eb19331..8b79841 100644 --- a/tcl/board/stm32l4discovery.cfg +++ b/tcl/board/stm32l4discovery.cfg @@ -4,7 +4,7 @@ # an stlink-v2-1 interface. # This is for STM32L4 boards that are connected via stlink-v2-1. -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32ldiscovery.cfg b/tcl/board/stm32ldiscovery.cfg index 8678d29..3e397cb 100644 --- a/tcl/board/stm32ldiscovery.cfg +++ b/tcl/board/stm32ldiscovery.cfg @@ -1,7 +1,7 @@ # This is an STM32L discovery board with a single STM32L152RBT6 chip. # http://www.st.com/internet/evalboard/product/250990.jsp -source [find interface/stlink-v2.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32vldiscovery.cfg b/tcl/board/stm32vldiscovery.cfg index 970b510..60805b3 100644 --- a/tcl/board/stm32vldiscovery.cfg +++ b/tcl/board/stm32vldiscovery.cfg @@ -1,7 +1,7 @@ # This is an STM32VL discovery board with a single STM32F100RB chip. # http://www.st.com/internet/evalboard/product/250863.jsp -source [find interface/stlink-v1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg new file mode 100644 index 0000000..fd66156 --- /dev/null +++ b/tcl/board/tocoding_poplar.cfg @@ -0,0 +1,28 @@ +# +# board configuration for Tocoding Poplar +# + +# board does not feature anything but JTAG +transport select jtag + +adapter_khz 10000 + +# SRST-only reset configuration +reset_config srst_only srst_push_pull + +source [find tcl/target/hi3798.cfg] + +# halt the cores when gdb attaches +${_TARGETNAME}0 configure -event gdb-attach "halt" + +# make sure the default target is the boot core +targets ${_TARGETNAME}0 + +proc core_up { args } { + global _TARGETNAME + + # examine remaining cores + foreach _core [set args] { + ${_TARGETNAME}$_core arp_examine + } +} diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg index b7d8d5b..7e040b3 100644 --- a/tcl/board/tp-link_tl-mr3020.cfg +++ b/tcl/board/tp-link_tl-mr3020.cfg @@ -42,3 +42,5 @@ $_TARGETNAME configure -event reset-init { set ram_boot_address 0xa0000000 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 diff --git a/tcl/board/tp-link_wdr4300.cfg b/tcl/board/tp-link_wdr4300.cfg new file mode 100644 index 0000000..c317916 --- /dev/null +++ b/tcl/board/tp-link_wdr4300.cfg @@ -0,0 +1,160 @@ +source [find target/atheros_ar9344.cfg] + +reset_config trst_only separate + +proc ar9344_40mhz_pll_init {} { + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0x13210f00 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0x13210f00 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_BB_DPLL_BASE_REG + mww 0xb8116188 0x03000000 + + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x0130001C + mww 0xb8050008 0x0130001C + mww 0xb8050008 0x0130001C + + # QCA_PLL_CPU_PLL_CFG_REG + mww 0xb8050000 0x40021380 + # QCA_PLL_DDR_PLL_CFG_REG + mww 0xb8050004 0x40815800 + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x0130801C + + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0x10810F00 + mww 0xb81161C0 0x41C00000 + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0xD0810F00 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_CPU_DPLL2_REG + mww 0xb81161C4 0xD0800F00 + + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x03000000 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x43000000 + # QCA_PLL_SRIF_CPU_DPLL3_REG + mww 0xb81161C8 0x030003E8 + + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0x10810F00 + mww 0xb8116240 0x41680000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0xD0810F00 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL2_REG + mww 0xb8116244 0xD0800F00 + + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000000 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x43000000 + # QCA_PLL_SRIF_DDR_DPLL3_REG + mww 0xb8116248 0x03000718 + + # QCA_PLL_CPU_DDR_CLK_CTRL_REG + mww 0xb8050008 0x01308018 + mww 0xb8050008 0x01308010 + mww 0xb8050008 0x01308000 + + # QCA_PLL_DDR_PLL_DITHER_REG + mww 0xb8050044 0x78180200 + # QCA_PLL_CPU_PLL_DITHER_REG + mww 0xb8050048 0x41C00000 + +} + +proc ar9344_ddr_init {} { + # QCA_DDR_CTRL_CFG_REG + mww 0xb8000108 0x40 + # QCA_DDR_RD_DATA_THIS_CYCLE_REG + mww 0xb8000018 0xFF + # QCA_DDR_BURST_REG + mww 0xb80000C4 0x74444444 + # QCA_DDR_BURST2_REG + mww 0xb80000C8 0x0222 + # QCA_AHB_MASTER_TOUT_MAX_REG + mww 0xb80000CC 0xFFFFF + + # QCA_DDR_CFG_REG + mww 0xb8000000 0xC7D48CD0 + # QCA_DDR_CFG2_REG + mww 0xb8000004 0x9DD0E6A8 + + # QCA_DDR_DDR2_CFG_REG + mww 0xb80000B8 0x0E59 + # QCA_DDR_CFG2_REG + mww 0xb8000004 0x9DD0E6A8 + + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x08 + mww 0xb8000010 0x08 + mww 0xb8000010 0x10 + mww 0xb8000010 0x20 + # QCA_DDR_EMR_REG + mww 0xb800000C 0x02 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x02 + + # QCA_DDR_MR_REG + mww 0xb8000008 0x0133 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x1 + mww 0xb8000010 0x8 + mww 0xb8000010 0x8 + mww 0xb8000010 0x4 + mww 0xb8000010 0x4 + + # QCA_DDR_MR_REG + mww 0xb8000008 0x33 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x1 + + # QCA_DDR_EMR_REG + mww 0xb800000C 0x0382 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x2 + # QCA_DDR_EMR_REG + mww 0xb800000C 0x0402 + # QCA_DDR_CTRL_REG + mww 0xb8000010 0x2 + + # QCA_DDR_REFRESH_REG + mww 0xb8000014 0x4270 + + # QCA_DDR_TAP_CTRL_0_REG + mww 0xb800001C 0x0e + # QCA_DDR_TAP_CTRL_1_REG + mww 0xb8000020 0x0e + # QCA_DDR_TAP_CTRL_2_REG + mww 0xb8000024 0x0e + # QCA_DDR_TAP_CTRL_3_REG + mww 0xb8000028 0x0e +} + +$_TARGETNAME configure -event reset-init { + + # mww 0xb806001c 0x1000000 + ar9344_40mhz_pll_init + sleep 100 + + # flash remap + # SPI_CONTROL_ADDR + mww 0xbF000004 0x43 + + ar9344_ddr_init + sleep 100 +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000 + +flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 |