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Diffstat (limited to 'src/target/arm_dpm.c')
-rw-r--r--src/target/arm_dpm.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 8b99570..72215f9 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -145,6 +145,9 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4),
((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0);
+ if (retval != ERROR_OK)
+ break;
+
/* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
@@ -209,7 +212,6 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
break;
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_read_reg_u64(dpm, r, regnum);
- break;
case ARM_VFP_V3_FPSCR:
/* "VMRS r0, FPSCR"; then return via DCC */
retval = dpm->instr_read_data_r0(dpm,
@@ -248,6 +250,9 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ break;
+
/* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
@@ -288,7 +293,6 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
break;
case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31:
return dpm_write_reg_u64(dpm, r, regnum);
- break;
case ARM_VFP_V3_FPSCR:
/* move to r0 from DCC, then "VMSR FPSCR, r0" */
retval = dpm->instr_write_data_r0(dpm,
@@ -1092,10 +1096,11 @@ int arm_dpm_setup(struct arm_dpm *dpm)
dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
- dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
- dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
+ dpm->dbp = calloc(dpm->nbp, sizeof(*dpm->dbp));
+ dpm->dwp = calloc(dpm->nwp, sizeof(*dpm->dwp));
if (!dpm->dbp || !dpm->dwp) {
+ arm_free_reg_cache(arm);
free(dpm->dbp);
free(dpm->dwp);
return ERROR_FAIL;