diff options
Diffstat (limited to 'src/jtag/swd.h')
| -rw-r--r-- | src/jtag/swd.h | 126 |
1 files changed, 110 insertions, 16 deletions
diff --git a/src/jtag/swd.h b/src/jtag/swd.h index 52f41d5..3ff4de0 100644 --- a/src/jtag/swd.h +++ b/src/jtag/swd.h @@ -53,16 +53,25 @@ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum) /* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */ +/* + * The following sequences are updated to + * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E + */ + /** - * Line reset. + * SWD Line reset. * - * Line reset is at least 50 SWCLK cycles with SWDIO driven high, followed - * by at least one idle (low) cycle. + * SWD Line reset is at least 50 SWCLK cycles with SWDIO driven high, + * followed by at least two idle (low) cycle. + * Bits are stored (and transmitted) LSB-first. */ static const uint8_t swd_seq_line_reset[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03 + /* At least 50 SWCLK cycles with SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* At least 2 idle (low) cycles */ + 0x00, }; -static const unsigned swd_seq_line_reset_len = 51; +static const unsigned swd_seq_line_reset_len = 64; /** * JTAG-to-SWD sequence. @@ -71,36 +80,53 @@ static const unsigned swd_seq_line_reset_len = 51; * high, putting either interface logic into reset state, followed by a * specific 16-bit sequence and finally a line reset in case the SWJ-DP was * already in SWD mode. + * Bits are stored (and transmitted) LSB-first. */ static const uint8_t swd_seq_jtag_to_swd[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x9e, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, + /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* Switching sequence from JTAG to SWD */ + 0x9e, 0xe7, + /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* At least 2 idle (low) cycles */ + 0x00, }; -static const unsigned swd_seq_jtag_to_swd_len = 118; +static const unsigned swd_seq_jtag_to_swd_len = 136; /** * SWD-to-JTAG sequence. * * The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO * high, putting either interface logic into reset state, followed by a - * specific 16-bit sequence and finally at least 5 TCK cycles to put the - * JTAG TAP in TLR. + * specific 16-bit sequence and finally at least 5 TCK/SWCLK cycles with + * TMS/SWDIO high to put the JTAG TAP in Test-Logic-Reset state. + * Bits are stored (and transmitted) LSB-first. */ static const uint8_t swd_seq_swd_to_jtag[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x9c, 0xff + /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* Switching sequence from SWD to JTAG */ + 0x3c, 0xe7, + /* At least 5 TCK/SWCLK cycles with TMS/SWDIO high */ + 0xff, }; -static const unsigned swd_seq_swd_to_jtag_len = 71; +static const unsigned swd_seq_swd_to_jtag_len = 80; /** * SWD-to-dormant sequence. * * This is at least 50 SWCLK cycles with SWDIO high to put the interface * in reset state, followed by a specific 16-bit sequence. + * Bits are stored (and transmitted) LSB-first. */ static const uint8_t swd_seq_swd_to_dormant[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x8e, 0x03 + /* At least 50 SWCLK cycles with SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* Switching sequence from SWD to dormant */ + 0xbc, 0xe3, }; -static const unsigned swd_seq_swd_to_dormant_len = 66; +static const unsigned swd_seq_swd_to_dormant_len = 72; /** * Dormant-to-SWD sequence. @@ -110,14 +136,82 @@ static const unsigned swd_seq_swd_to_dormant_len = 66; * sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by * a specific protocol-dependent activation code. For SWD the activation code * is an 8-bit sequence. The sequence ends with a line reset. + * Bits are stored (and transmitted) LSB-first. */ static const uint8_t swd_seq_dormant_to_swd[] = { + /* At least 8 SWCLK cycles with SWDIO high */ + 0xff, + /* Selection alert sequence */ + 0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86, + 0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19, + /* + * 4 SWCLK cycles with SWDIO low ... + * + SWD activation code 0x1a ... + * + at least 8 SWCLK cycles with SWDIO high + */ + 0xa0, /* ((0x00) & GENMASK(3, 0)) | ((0x1a << 4) & GENMASK(7, 4)) */ + 0xf1, /* ((0x1a >> 4) & GENMASK(3, 0)) | ((0xff << 4) & GENMASK(7, 4)) */ + 0xff, + /* At least 50 SWCLK cycles with SWDIO high */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + /* At least 2 idle (low) cycles */ + 0x00, +}; +static const unsigned swd_seq_dormant_to_swd_len = 224; + +/** + * JTAG-to-dormant sequence. + * + * This is at least 5 TCK cycles with TMS high to put the interface + * in test-logic-reset state, followed by a specific 31-bit sequence. + * Bits are stored (and transmitted) LSB-first. + */ +static const uint8_t swd_seq_jtag_to_dormant[] = { + /* At least 5 TCK cycles with TMS high */ + 0xff, + /* + * Still one TCK cycle with TMS high followed by 31 bits JTAG-to-DS + * select sequence 0xba, 0xbb, 0xbb, 0x33, + */ + 0x75, /* ((0xff >> 7) & GENMASK(0, 0)) | ((0xba << 1) & GENMASK(7, 1)) */ + 0x77, /* ((0xba >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */ + 0x77, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */ + 0x67, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0x33 << 1) & GENMASK(7, 1)) */ +}; +static const unsigned swd_seq_jtag_to_dormant_len = 40; + +/** + * Dormant-to-JTAG sequence. + * + * This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing + * selection alert sequence, followed by a specific 128-bit selection alert + * sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by + * a specific protocol-dependent activation code. For JTAG there are two + * possible activation codes: + * - "JTAG-Serial": 12 bits 0x00, 0x00 + * - "Arm CoreSight JTAG-DP": 8 bits 0x0a + * We use "JTAG-Serial" only, which seams more generic. + * Since the target TAP can be either in Run/Test Idle or in Test-Logic-Reset + * states, Arm recommends to put the TAP in Run/Test Idle using one TCK cycle + * with TMS low. To keep the sequence length multiple of 8, 8 TCK cycle with + * TMS low are sent (allowed by JTAG state machine). + * Bits are stored (and transmitted) LSB-first. + */ +static const uint8_t swd_seq_dormant_to_jtag[] = { + /* At least 8 TCK/SWCLK cycles with TMS/SWDIO high */ 0xff, + /* Selection alert sequence */ 0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86, 0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19, - 0x10, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f + /* + * 4 TCK/SWCLK cycles with TMS/SWDIO low ... + * + 12 bits JTAG-serial activation code 0x00, 0x00 + */ + 0x00, 0x00, + /* put the TAP in Run/Test Idle */ + 0x00, }; -static const unsigned swd_seq_dormant_to_swd_len = 199; +static const unsigned swd_seq_dormant_to_jtag_len = 160; enum swd_special_seq { LINE_RESET, |