diff options
Diffstat (limited to 'contrib/loaders/flash')
41 files changed, 11407 insertions, 21 deletions
diff --git a/contrib/loaders/flash/at91sam7x/dcc.c b/contrib/loaders/flash/at91sam7x/dcc.c index 6ab2417..04a7f7a 100644 --- a/contrib/loaders/flash/at91sam7x/dcc.c +++ b/contrib/loaders/flash/at91sam7x/dcc.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #include "dcc.h" diff --git a/contrib/loaders/flash/at91sam7x/dcc.h b/contrib/loaders/flash/at91sam7x/dcc.h index a3c1393..428bf49 100644 --- a/contrib/loaders/flash/at91sam7x/dcc.h +++ b/contrib/loaders/flash/at91sam7x/dcc.h @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifndef dccH #define dccH diff --git a/contrib/loaders/flash/at91sam7x/main.c b/contrib/loaders/flash/at91sam7x/main.c index c4b4dcf..831e03f 100644 --- a/contrib/loaders/flash/at91sam7x/main.c +++ b/contrib/loaders/flash/at91sam7x/main.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #include "platform.h" diff --git a/contrib/loaders/flash/at91sam7x/ocl.h b/contrib/loaders/flash/at91sam7x/ocl.h index 1fe4596..ef30c33 100644 --- a/contrib/loaders/flash/at91sam7x/ocl.h +++ b/contrib/loaders/flash/at91sam7x/ocl.h @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifndef OCL_H #define OCL_H diff --git a/contrib/loaders/flash/at91sam7x/platform.h b/contrib/loaders/flash/at91sam7x/platform.h index 2b26e4b..3dfa4dc 100644 --- a/contrib/loaders/flash/at91sam7x/platform.h +++ b/contrib/loaders/flash/at91sam7x/platform.h @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifndef platformH #define platformH diff --git a/contrib/loaders/flash/at91sam7x/samflash.c b/contrib/loaders/flash/at91sam7x/samflash.c index 49c84c8..3095394 100644 --- a/contrib/loaders/flash/at91sam7x/samflash.c +++ b/contrib/loaders/flash/at91sam7x/samflash.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #include "samflash.h" diff --git a/contrib/loaders/flash/at91sam7x/samflash.h b/contrib/loaders/flash/at91sam7x/samflash.h index 1de02ae..18973a7 100644 --- a/contrib/loaders/flash/at91sam7x/samflash.h +++ b/contrib/loaders/flash/at91sam7x/samflash.h @@ -13,9 +13,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * ***************************************************************************/ #ifndef samflashH #define samflashH diff --git a/contrib/loaders/flash/cc26xx/Makefile b/contrib/loaders/flash/cc26xx/Makefile new file mode 100644 index 0000000..7cc1fb3 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/Makefile @@ -0,0 +1,83 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- +GCC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +FLAGS = -mthumb -Os -ffunction-sections -fdata-sections -g -gdwarf-3 +FLAGS += -gstrict-dwarf -Wall -fno-strict-aliasing --asm + +CFLAGS = -c -I. + +CC26X0_CFLAGS = -mcpu=cortex-m3 -DDEVICE_CC26X0 + +CC26X2_CFLAGS = -mcpu=cortex-m4 -DDEVICE_CC26X2 + +CC26X0_OBJS := \ +cc26x0/flashloader.o \ +cc26x0/main.o \ +cc26x0/startup.o \ +cc26x0/flash.o + +CC26X2_OBJS := \ +cc26x2/flashloader.o \ +cc26x2/main.o \ +cc26x2/startup.o \ +cc26x2/flash.o + +all: cc26x0_algo.inc cc26x2_algo.inc + +cc26x0/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) $(FLAGS) $(CFLAGS) $(CC26X0_CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +cc26x2/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) $(FLAGS) $(CFLAGS) $(CC26X2_CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +cc26x0_algo.out: $(CC26X0_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) -o$@ $(CC26X0_OBJS) -Wl,-T"cc26x0/cc26x0r2f.lds" + @echo 'Finished building target: $@' + @echo ' ' + +cc26x2_algo.out: $(CC26X2_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) -o$@ $(CC26X2_OBJS) -Wl,-T"cc26x2/cc26x2r1f.lds" + @echo 'Finished building target: $@' + @echo ' ' + +%.bin: %.out + @echo 'Building target: $@' + @echo 'Invoking: GNU Objcopy Utility' + $(OBJCOPY) -Obinary $< $@ + @echo 'Finished building target: $@' + @echo ' ' + +%.inc: %.bin + @echo 'Building target: $@' + @echo 'Invoking Bin2Char Script' + $(BIN2C) < $< > $@ + rm $< $*.out + @echo 'Finished building target: $@' + @echo ' ' + +clean: + @echo 'Cleaning Targets and Build Artifacts' + rm -rf *.inc *.bin *.out *.map + rm -rf cc26x0/*.o cc26x0/*.d + rm -rf cc26x2/*.o cc26x2/*.d + @echo 'Finished clean' + @echo ' ' + +.PRECIOUS: %.bin + +.PHONY: all clean diff --git a/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds new file mode 100644 index 0000000..9a126fc --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x0/cc26x0r2f.lds @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* Entry Point */ +ENTRY( entry ) + +/* System memory map */ +MEMORY +{ + /* Application is stored in and executes from SRAM */ + PROGRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x1BD8 + BUFFERS (RWX) : ORIGIN = 0x20001BD8, LENGTH = 0x3028 +} + +/* Section allocation in memory */ +SECTIONS +{ + .text : + { + _text = .; + *(.entry*) + *(.text*) + _etext = .; + } > PROGRAM + + .data : + { _data = .; + *(.rodata*) + *(.data*) + _edata = .; + } + + .bss : + { + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + __bss_end__ = .; + } > PROGRAM + + .stack : + { + _stack = .; + *(.stack*) + _estack = .; + } > PROGRAM + + .buffers : + { + _buffers = .; + *(.buffers.g_cfg) + *(.buffers.g_buf1) + *(.buffers.g_buf2) + *(.buffers*) + _ebuffers = .; + } > BUFFERS +} diff --git a/contrib/loaders/flash/cc26xx/cc26x0_algo.inc b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc new file mode 100644 index 0000000..2246a36 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x0_algo.inc @@ -0,0 +1,1217 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48, +0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, +0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds new file mode 100644 index 0000000..fb7cc56 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x2/cc26x2r1f.lds @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +/* Entry Point */ +ENTRY( entry ) + +/* System memory map */ +MEMORY +{ + /* Application is stored in and executes from SRAM */ + PROGRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x1FD8 + BUFFERS (RWX) : ORIGIN = 0x20001FD8, LENGTH = 0x6028 +} + +/* Section allocation in memory */ +SECTIONS +{ + .text : + { + _text = .; + *(.entry*) + *(.text*) + _etext = .; + } > PROGRAM + + .data : + { _data = .; + *(.rodata*) + *(.data*) + _edata = .; + } + + .bss : + { + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + _ebss = .; + __bss_end__ = .; + } > PROGRAM + + .stack : + { + _stack = .; + *(.stack*) + _estack = .; + } > PROGRAM + + .buffers : + { + _buffers = .; + *(.buffers.g_cfg) + *(.buffers.g_buf1) + *(.buffers.g_buf2) + *(.buffers*) + _ebuffers = .; + } > BUFFERS +} diff --git a/contrib/loaders/flash/cc26xx/cc26x2_algo.inc b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc new file mode 100644 index 0000000..9adb919 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/cc26x2_algo.inc @@ -0,0 +1,2049 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x08,0xb5,0x00,0xbf,0x00,0xbf,0x00,0xbf,0x00,0xbf,0xdf,0xf8,0x1c,0xd0,0x07,0x48, +0x07,0x49,0x4f,0xf0,0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb, +0x00,0xf0,0xa8,0xf9,0xfe,0xe7,0x00,0x00,0xf0,0x0e,0x00,0x20,0x54,0x13,0x00,0x20, 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copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "flash.h" + +/****************************************************************************** +* +* Defines for accesses to the security control in the customer configuration +* area in flash top sector. +* +******************************************************************************/ +#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG +#define CCFG_SIZE_SECURITY 0x00000014 + +/****************************************************************************** +* +* Default values for security control in customer configuration area in flash +* top sector. +* +******************************************************************************/ +const uint8_t g_ccfg_default_sec[] = { + 0xFF, 0xFF, 0xFF, 0xC5, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xC5, 0xFF, 0xFF, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF, + 0xC5, 0xC5, 0xC5, 0xFF +}; + +typedef uint32_t (*flash_prg_pntr_t) (uint8_t *, uint32_t, uint32_t); +typedef uint32_t (*flash_sector_erase_pntr_t) (uint32_t); + +/****************************************************************************** +* +* Function prototypes for static functions +* +******************************************************************************/ +static void issue_fsm_command(flash_state_command_t command); +static void enable_sectors_for_write(void); +static uint32_t scale_cycle_values(uint32_t specified_timing, + uint32_t scale_value); +static void set_write_mode(void); +static void trim_for_write(void); +static void set_read_mode(void); + +/****************************************************************************** +* +* Erase a flash sector +* +******************************************************************************/ +uint32_t flash_sector_erase(uint32_t sector_address) +{ + uint32_t error_return; + flash_sector_erase_pntr_t func_pntr; + + /* Call ROM function */ + func_pntr = (uint32_t (*)(uint32_t))(ROM_API_FLASH_TABLE[5]); + error_return = func_pntr(sector_address); + + /* Enable standby because ROM function might have disabled it */ + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0; + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Erase all unprotected sectors in the flash main bank +* +******************************************************************************/ +uint32_t flash_bank_erase(bool force_precondition) +{ + uint32_t error_return; + uint32_t sector_address; + uint32_t reg_val; + + /* Enable all sectors for erase. */ + enable_sectors_for_write(); + + /* Clear the Status register. */ + issue_fsm_command(FAPI_CLEAR_STATUS); + + /* Enable erase of all sectors and enable precondition if required. */ + reg_val = HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE); + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0x00000000; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0x00000000; + if (force_precondition) + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + /* Issue the bank erase command to the FSM. */ + issue_fsm_command(FAPI_ERASE_BANK); + + /* Wait for erase to finish. */ + while (flash_check_fsm_for_ready() == FAPI_STATUS_FSM_BUSY) + ; + + /* Update status. */ + error_return = flash_check_fsm_for_error(); + + /* Disable sectors for erase. */ + flash_disable_sectors_for_write(); + + /* Set configured precondition mode since it may have been forced on. */ + if (!(reg_val & FLASH_FSM_ST_MACHINE_DO_PRECOND)) { + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= + ~FLASH_FSM_ST_MACHINE_DO_PRECOND; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + } + + /* Program security data to default values in the customer configuration */ + /* area within the flash top sector if erase was successful. */ + if (error_return == FAPI_STATUS_SUCCESS) { + sector_address = FLASHMEM_BASE + flash_size_get() - + flash_sector_size_get(); + error_return = flash_program((uint8_t *)g_ccfg_default_sec, + (sector_address + CCFG_OFFSET_SECURITY), + CCFG_SIZE_SECURITY); + } + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Programs unprotected main bank flash sectors +* +******************************************************************************/ +uint32_t flash_program(uint8_t *data_buffer, uint32_t address, uint32_t count) +{ + uint32_t error_return; + flash_prg_pntr_t func_pntr; + + /* Call ROM function */ + func_pntr = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) + (ROM_API_FLASH_TABLE[6]); + error_return = func_pntr(data_buffer, address, count); + + /* Enable standby because ROM function might have disabled it */ + HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN) = 0; + + /* Return status of operation. */ + return error_return; +} + +/****************************************************************************** +* +* Disables all sectors for erase and programming on the active bank +* +******************************************************************************/ +void flash_disable_sectors_for_write(void) +{ + /* Configure flash back to read mode */ + set_read_mode(); + + /* Disable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + /* Disable all sectors for erase and programming. */ + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; + + /* Enable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; + + /* Protect sectors from sector erase. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +/****************************************************************************** +* +* Issues a command to the Flash State Machine. +* +******************************************************************************/ +static void issue_fsm_command(flash_state_command_t command) +{ + /* Enable write to FSM register. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + /* Issue FSM command. */ + HWREG(FLASH_BASE + FLASH_O_FSM_CMD) = command; + + /* Start command execute. */ + HWREG(FLASH_BASE + FLASH_O_FSM_EXECUTE) = FLASH_CMD_EXEC; + + /* Disable write to FSM register. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; +} + +/****************************************************************************** +* +* Enables all sectors for erase and programming on the active bank. +* +* This function disables the idle reading power reduction mode, selects the +* flash bank and enables all sectors for erase and programming on the active +* bank. +* Sectors may be protected from programming depending on the value of the +* FLASH_O_FSM_BSLPx registers. +* Sectors may be protected from erase depending on the value of the +* FLASH_O_FSM_BSLEx registers. Additional sector erase protection is set by +* the FLASH_O_FSM_SECTOR1 register. +* +******************************************************************************/ +static void enable_sectors_for_write(void) +{ + /* Trim flash module for program/erase operation. */ + trim_for_write(); + + /* Configure flash to write mode */ + set_write_mode(); + + /* Select flash bank. */ + HWREG(FLASH_BASE + FLASH_O_FMAC) = 0x00; + + /* Disable Level 1 Protection. */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; + + /* Enable all sectors for erase and programming. */ + HWREG(FLASH_BASE + FLASH_O_FBSE) = 0xFFFF; + + /* Enable Level 1 Protection */ + HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; +} + +/****************************************************************************** +* +* Trims the Flash Bank and Flash Pump for program/erase functionality +* +* This trimming will make it possible to perform erase and program operations +* of the flash. Trim values are loaded from factory configuration area +* (referred to as FCGF1). The trimming done by this function is valid until +* reset of the flash module. +* +* Some registers shall be written with a value that is a number of FCLK +* cycles. The trim values controlling these registers have a value of +* number of half us. FCLK = SysClk / ((RWAIT+1) x 2). +* +******************************************************************************/ +static void trim_for_write(void) +{ + uint32_t value; + uint32_t temp_val; + uint32_t fclk_scale; + uint32_t rwait; + + /* Return if flash is already trimmed for program/erase operations. */ + if (HWREG(FLASH_BASE + FLASH_O_FWFLAG) & FW_WRT_TRIMMED) + return; + + /* Configure the FSM registers */ + + /* Enable access to the FSM registers. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; + + /* Determine the scaling value to be used on timing related trim values. */ + /* The value is based on the flash module clock frequency and RWAIT */ + rwait = (HWREG(FLASH_BASE + FLASH_O_FRDCTL) & + FLASH_FRDCTL_RWAIT_M) >> FLASH_FRDCTL_RWAIT_S; + fclk_scale = (16 * FLASH_MODULE_CLK_FREQ) / (rwait + 1); + + /* Configure Program pulse width bits 15:0. */ + /* (FCFG1 offset 0x188 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_PROGRAM_PW_M) >> + FCFG1_FLASH_PROG_EP_PROGRAM_PW_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PW) & + ~FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M) | + ((value << FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S) & + FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M); + + /* Configure Erase pulse width bits 31:0. */ + /* (FCFG1 offset 0x18C bits 31:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_ERA_PW) & + FCFG1_FLASH_ERA_PW_ERASE_PW_M) >> + FCFG1_FLASH_ERA_PW_ERASE_PW_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PW) & + ~FLASH_FSM_ERA_PW_FSM_ERA_PW_M) | + ((value << FLASH_FSM_ERA_PW_FSM_ERA_PW_S) & + FLASH_FSM_ERA_PW_FSM_ERA_PW_M); + + /* Configure no of flash clock cycles from EXECUTEZ going low to the the + verify data can be read in the program verify mode bits 7:0. */ + /* (FCFG1 offset 0x174 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_PV_ACCESS_M) >> + FCFG1_FLASH_C_E_P_R_PV_ACCESS_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_EXE_VALD_M) | + ((value << FLASH_FSM_EX_VAL_EXE_VALD_S) & + FLASH_FSM_EX_VAL_EXE_VALD_M); + + /* Configure the number of flash clocks from the start of the Read mode at + the end of the operations until the FSM clears the BUSY bit in FMSTAT. */ + /* (FCFG1 offset 0x178 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_RH_M) >> + FCFG1_FLASH_P_R_PV_RH_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) = + (HWREG(FLASH_BASE + FLASH_O_FSM_RD_H) & + ~FLASH_FSM_RD_H_RD_H_M) | + ((value << FLASH_FSM_RD_H_RD_H_S) & + FLASH_FSM_RD_H_RD_H_M); + + /* Configure Program hold time */ + /* (FCFG1 offset 0x178 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PH_M) >> + FCFG1_FLASH_P_R_PV_PH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_P_OH) & + ~FLASH_FSM_P_OH_PGM_OH_M) | + ((value << FLASH_FSM_P_OH_PGM_OH_S) & + FLASH_FSM_P_OH_PGM_OH_M); + + /* Configure Erase hold time */ + /* (FCFG1 offset 0x17C bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_EH_M) >> + FCFG1_FLASH_EH_SEQ_EH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_OH) & + ~FLASH_FSM_ERA_OH_ERA_OH_M) | + ((value << FLASH_FSM_ERA_OH_ERA_OH_S) & + FLASH_FSM_ERA_OH_ERA_OH_M); + + /* Configure Program verify row switch time */ + /* (FCFG1 offset0x178 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_P_R_PV) & + FCFG1_FLASH_P_R_PV_PVH_M) >> + FCFG1_FLASH_P_R_PV_PVH_S; + + value = scale_cycle_values(value, fclk_scale); + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VH) & + ~FLASH_FSM_PE_VH_PGM_VH_M) | + ((value << FLASH_FSM_PE_VH_PGM_VH_S) & + FLASH_FSM_PE_VH_PGM_VH_M); + + /* Configure Program Operation Setup time */ + /* (FCFG1 offset 0x170 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PSU_M) >> + FCFG1_FLASH_E_P_PSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_PGM_OSU_M) | + ((value << FLASH_FSM_PE_OSU_PGM_OSU_S) & + FLASH_FSM_PE_OSU_PGM_OSU_M); + + /* Configure Erase Operation Setup time */ + /* (FCGF1 offset 0x170 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_ESU_M) >> + FCFG1_FLASH_E_P_ESU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_OSU) & + ~FLASH_FSM_PE_OSU_ERA_OSU_M) | + ((value << FLASH_FSM_PE_OSU_ERA_OSU_S) & + FLASH_FSM_PE_OSU_ERA_OSU_M); + + /* Confgure Program Verify Setup time */ + /* (FCFG1 offset 0x170 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_PVSU_M) >> + FCFG1_FLASH_E_P_PVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_PGM_VSU_M) | + ((value << FLASH_FSM_PE_VSU_PGM_VSU_S) & + FLASH_FSM_PE_VSU_PGM_VSU_M); + + /* Configure Erase Verify Setup time */ + /* (FCFG1 offset 0x170 bits 7:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_E_P) & + FCFG1_FLASH_E_P_EVSU_M) >> + FCFG1_FLASH_E_P_EVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PE_VSU) & + ~FLASH_FSM_PE_VSU_ERA_VSU_M) | + ((value << FLASH_FSM_PE_VSU_ERA_VSU_S) & + FLASH_FSM_PE_VSU_ERA_VSU_M); + + /* Configure Addr to EXECUTEZ low setup time */ + /* (FCFG1 offset 0x174 bits 15:12). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M) >> + FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) = + (HWREG(FLASH_BASE + FLASH_O_FSM_CMP_VSU) & + ~FLASH_FSM_CMP_VSU_ADD_EXZ_M) | + ((value << FLASH_FSM_CMP_VSU_ADD_EXZ_S) & + FLASH_FSM_CMP_VSU_ADD_EXZ_M); + + /* Configure Voltage Status Count */ + /* (FCFG1 offset 0x17C bits 15:12). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_EH_SEQ) & + FCFG1_FLASH_EH_SEQ_VSTAT_M) >> + FCFG1_FLASH_EH_SEQ_VSTAT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) = + (HWREG(FLASH_BASE + FLASH_O_FSM_VSTAT) & + ~FLASH_FSM_VSTAT_VSTAT_CNT_M) | + ((value << FLASH_FSM_VSTAT_VSTAT_CNT_S) & + FLASH_FSM_VSTAT_VSTAT_CNT_M); + + /* Configure Repeat Verify action setup */ + /* (FCFG1 offset 0x174 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_C_E_P_R) & + FCFG1_FLASH_C_E_P_R_RVSU_M) >> + FCFG1_FLASH_C_E_P_R_RVSU_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_EX_VAL) & + ~FLASH_FSM_EX_VAL_REP_VSU_M) | + ((value << FLASH_FSM_EX_VAL_REP_VSU_S) & + FLASH_FSM_EX_VAL_REP_VSU_M); + + /* Configure Maximum Programming Pulses */ + /* (FCFG1 offset 0x184 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PP) & + FCFG1_FLASH_PP_MAX_PP_M) >> + FCFG1_FLASH_PP_MAX_PP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M) | + ((value << FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S) & + FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M); + + /* Configure Beginning level for VHVCT used during erase modes */ + /* (FCFG1 offset 0x180 bits 31:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_START_M) >> + FCFG1_FLASH_VHV_E_VHV_E_START_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_PRG_PUL) & + ~FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M) | + ((value << FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S) & + FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M); + + /* Configure Maximum EC Level */ + /* (FCFG1 offset 0x2B0 bits 21:18). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M) >> + FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M) | + ((value << FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S) & + FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M); + + /* Configure Maximum Erase Pulses */ + /* (FCFG1 offset 0x188 bits 31:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_PROG_EP) & + FCFG1_FLASH_PROG_EP_MAX_EP_M) >> + FCFG1_FLASH_PROG_EP_MAX_EP_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ERA_PUL) & + ~FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M) | + ((value << FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S) & + FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M); + + /* Configure the VHVCT Step Size. This is the number of erase pulses that + must be completed for each level before the FSM increments the + CUR_EC_LEVEL to the next higher level. Actual erase pulses per level + equals (EC_STEP_SIZE +1). The stepping is only needed for the VHVCT + voltage. */ + /* (FCFG1 offset 0x2B0 bits 31:23). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M) >> + FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_STEP_SIZE) & + ~FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M) | + ((value << FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S) & + FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M); + + /* Configure the hight of each EC step. This is the number of counts that + the CUR_EC_LEVEL will increment when going to a new level. Actual count + size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the VHVCT + voltage. + The read trim value is decremented by 1 before written to the register + since actual counts equals (register value + 1). */ + /* (FCFG1 offset 0x180 bits 15:0). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_E) & + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M) >> + FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_EC_STEP_HEIGHT) = ((value - 1) & + FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M); + + /* Configure Precondition used in erase operations */ + /* (FCFG1 offset 0x2B0 bit 22). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M) >> + FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S; + + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) = + (HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) & + ~FLASH_FSM_ST_MACHINE_DO_PRECOND_M) | + ((value << FLASH_FSM_ST_MACHINE_DO_PRECOND_S) & + FLASH_FSM_ST_MACHINE_DO_PRECOND_M); + + /* Enable the recommended Good Time function. */ + HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= + FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD; + + /* Disable write access to FSM registers. */ + HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; + + /* Configure the voltage registers */ + + /* Unlock voltage registers (0x2080 - 0x2098). */ + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + + /* Configure voltage level for the specified pump voltage of high + voltage supply input during erase operation VHVCT_E and TRIM13_E */ + /* (FCFG1 offset 0x190 bits[3:0] and bits[11:8]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_E_M)>> + FCFG1_FLASH_VHV_TRIM13_E_S) << FLASH_FVHVCT1_TRIM13_E_S; + value |= ((temp_val & FCFG1_FLASH_VHV_VHV_E_M)>> + FCFG1_FLASH_VHV_VHV_E_S) << FLASH_FVHVCT1_VHVCT_E_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_E_M | FLASH_FVHVCT1_VHVCT_E_M)) | value; + + /* Configure voltage level for the specified pump voltage of high voltage + supply input during program verify operation VHVCT_PV and TRIM13_PV */ + /* (OTP offset 0x194 bits[19:16] and bits[27:24]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV); + + value = ((temp_val & FCFG1_FLASH_VHV_PV_TRIM13_PV_M) >> + FCFG1_FLASH_VHV_PV_TRIM13_PV_S) << FLASH_FVHVCT1_TRIM13_PV_S; + value |= ((temp_val & FCFG1_FLASH_VHV_PV_VHV_PV_M) >> + FCFG1_FLASH_VHV_PV_VHV_PV_S) << FLASH_FVHVCT1_VHVCT_PV_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT1) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT1) & + ~(FLASH_FVHVCT1_TRIM13_PV_M | FLASH_FVHVCT1_VHVCT_PV_M)) | value; + + /* Configure voltage level for the specified pump voltage of high voltage + supply input during program operation VHVCT_P and TRIM13_P */ + /* (FCFG1 offset 0x190 bits[19:16] and bits[27:24]). */ + temp_val = HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV); + + value = ((temp_val & FCFG1_FLASH_VHV_TRIM13_P_M) >> + FCFG1_FLASH_VHV_TRIM13_P_S) << FLASH_FVHVCT2_TRIM13_P_S; + value |= ((temp_val & FCFG1_FLASH_VHV_VHV_P_M) >> + FCFG1_FLASH_VHV_VHV_P_S) << FLASH_FVHVCT2_VHVCT_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVHVCT2) = (HWREG(FLASH_BASE + FLASH_O_FVHVCT2) & + ~(FLASH_FVHVCT2_TRIM13_P_M | FLASH_FVHVCT2_VHVCT_P_M)) | value; + + /* Configure voltage level for the specified pump voltage of wordline power + supply for read mode */ + /* (FCFG1 offset 0x198 Bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_V_READ_M) >> FCFG1_FLASH_V_V_READ_S; + + HWREG(FLASH_BASE + FLASH_O_FVREADCT) = + (HWREG(FLASH_BASE + FLASH_O_FVREADCT) & + ~FLASH_FVREADCT_VREADCT_M) | + ((value << FLASH_FVREADCT_VREADCT_S) & + FLASH_FVREADCT_VREADCT_M); + + /* Configure the voltage level for the VCG 2.5 CT pump voltage */ + /* (FCFG1 offset 0x194 bits 15:8). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_VHV_PV) & + FCFG1_FLASH_VHV_PV_VCG2P5_M) >> + FCFG1_FLASH_VHV_PV_VCG2P5_S; + + HWREG(FLASH_BASE + FLASH_O_FVNVCT) = + (HWREG(FLASH_BASE + FLASH_O_FVNVCT) & + ~FLASH_FVNVCT_VCG2P5CT_M) | + ((value << FLASH_FVNVCT_VCG2P5CT_S) & + FLASH_FVNVCT_VCG2P5CT_M); + + /* Configure the voltage level for the specified pump voltage of high + current power input during program operation */ + /* (FCFG1 offset 0x198 bits 31:24). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VSL_P_M) >> + FCFG1_FLASH_V_VSL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVSLP) = + (HWREG(FLASH_BASE + FLASH_O_FVSLP) & + ~FLASH_FVSLP_VSL_P_M) | + ((value << FLASH_FVSLP_VSL_P_S) & + FLASH_FVSLP_VSL_P_M); + + /* Configure the voltage level for the specified pump voltage of wordline + power supply during programming operations */ + /* (OTP offset 0x198 bits 23:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_V) & + FCFG1_FLASH_V_VWL_P_M) >> + FCFG1_FLASH_V_VWL_P_S; + + HWREG(FLASH_BASE + FLASH_O_FVWLCT) = + (HWREG(FLASH_BASE + FLASH_O_FVWLCT) & + ~FLASH_FVWLCT_VWLCT_P_M) | + ((value << FLASH_FVWLCT_VWLCT_P_S) & + FLASH_FVWLCT_VWLCT_P_M); + + /* Configure the pump's TRIM_1P7 port pins. */ + /* (FCFG1 offset 0x2B0 bits 17:16). */ + value = (HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA3) & + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M) >> + FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S; + + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~FLASH_FSEQPMP_TRIM_1P7_M) | + ((value << FLASH_FSEQPMP_TRIM_1P7_S) & + FLASH_FSEQPMP_TRIM_1P7_M); + + /* Lock the voltage registers. */ + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + + /* Set trimmed flag. */ + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 5; + HWREG(FLASH_BASE + FLASH_O_FWFLAG) |= FW_WRT_TRIMMED; + HWREG(FLASH_BASE + FLASH_O_FWLOCK) = 0; +} + +/****************************************************************************** +* +* Used to scale the TI OTP values based on the FClk scaling value. +* +******************************************************************************/ +static uint32_t scale_cycle_values(uint32_t specified_timing, + uint32_t scale_value) +{ + uint32_t scaled_value = (specified_timing * scale_value) >> 6; + return scaled_value; +} + +/****************************************************************************** +* +* Used to set flash in read mode. +* +* Flash is configured with values loaded from OTP dependent on the current +* regulator mode. +* +******************************************************************************/ +static void set_read_mode(void) +{ + uint32_t trim_value; + uint32_t value; + + /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + VIN_AT_X and VIN_BY_PASS for read mode */ + if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) { + + /* Select trim values for external regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) + Configure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 4). + Configure DIS_IDLE (OTP offset 0x308 bit 3). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE+FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 2:0) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } else { + + /* Select trim values for internal regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) + COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 12). + Configure DIS_IDLE (OTP offset 0x308 bit 11). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 10:8) */ + value = (((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << + FLASH_FSEQPMP_VIN_AT_X_S); + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} + +/****************************************************************************** +* +* Used to set flash in write mode. +* +* Flash is configured with values loaded from OTP dependent on the current +* regulator mode. +* +******************************************************************************/ +static void set_write_mode(void) +{ + uint32_t trim_value; + uint32_t value; + + /* Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, + VIN_AT_X and VIN_BY_PASS for program/erase mode */ + if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & + AON_PMCTL_PWRCTL_EXT_REG_MODE) { + + /* Select trim values for external regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 23) + Configure STANDBY_PW_SEL (OTP offset 0x308 bit 22:21) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 20). + Configure DIS_IDLE (OTP offset 0x308 bit 19). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 18:16) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } else { + /* Select trim values for internal regulator mode: + Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 31) + COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 30:29) + Must be done while the register bit field CONFIG.DIS_STANDBY = 1 */ + HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; + + trim_value = + HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); + + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_MODE_SEL_S; + + value |= ((trim_value & + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S) << + FLASH_CFG_STANDBY_PW_SEL_S; + + /* Configure DIS_STANDBY (OTP offset 0x308 bit 28). + Configure DIS_IDLE (OTP offset 0x308 bit 27). */ + value |= ((trim_value & + (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M | + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M)) >> + FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S) << + FLASH_CFG_DIS_IDLE_S; + + HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & + ~(FLASH_CFG_STANDBY_MODE_SEL_M | FLASH_CFG_STANDBY_PW_SEL_M | + FLASH_CFG_DIS_STANDBY_M | FLASH_CFG_DIS_IDLE_M)) | value; + + /* Check if sample and hold functionality is disabled. */ + if (HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) { + /* Wait for disabled sample and hold functionality to be stable. */ + while (!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) + ; + } + + /* Configure VIN_AT_X (OTP offset 0x308 bits 26:24) */ + value = ((trim_value & + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M) >> + FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S) << + FLASH_FSEQPMP_VIN_AT_X_S; + + /* Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. + If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise + VIN_BY_PASS should be 1 */ + if (((value & FLASH_FSEQPMP_VIN_AT_X_M) >> + FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) + value |= FLASH_FSEQPMP_VIN_BY_PASS; + + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; + HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = + (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & + ~(FLASH_FSEQPMP_VIN_BY_PASS_M | + FLASH_FSEQPMP_VIN_AT_X_M)) | value; + HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; + } +} diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h new file mode 100644 index 0000000..ec1c24f --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flash.h @@ -0,0 +1,378 @@ +/****************************************************************************** +* +* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H +#define OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include <stdint.h> +#include <stdbool.h> +#include "hw_regs.h" + +/* Location of flash in memory map */ +#define FLASHMEM_BASE 0 + +/* Defines to access flash API calls in ROM */ +#define ROM_API_TABLE ((uint32_t *) 0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) +#define ROM_API_FLASH_TABLE ((uint32_t *) (ROM_API_TABLE[10])) + +#if defined(DEVICE_CC26X2) + +/* Agama (CC26x2) specific definitions */ + +#define FLASH_ERASE_SIZE 8192 +/* Agama (and Agama 1M) has a maximum of 132 flash sectors (1056KB / 8KB) */ +#define FLASH_MAX_SECTOR_COUNT 132 +#define FLASH_SECTOR_BASE_M 0xFFFFE000 + +/* Bootloader Configuration */ +#define CCFG_O_BL_CONFIG 0x00001FD8 + +#elif defined(DEVICE_CC26X0) + +/* Chameleon (CC26x0) specific definitions */ + +#define FLASH_ERASE_SIZE 4096 +/* Chameleon has a maximum of 32 flash sectors (128KB / 4KB) */ +#define FLASH_MAX_SECTOR_COUNT 32 +#define FLASH_SECTOR_BASE_M 0xFFFFF000 + +/* Bootloader Configuration */ +#define CCFG_O_BL_CONFIG 0x00000FD8 + +#else +#error No DEVICE defined. +#endif + +/****************************************************************************** +* +* Values that can be returned from the API functions +* +******************************************************************************/ +#define FAPI_STATUS_SUCCESS 0x00000000 /* Function completed successfully */ +#define FAPI_STATUS_FSM_BUSY 0x00000001 /* FSM is Busy */ +#define FAPI_STATUS_FSM_READY 0x00000002 /* FSM is Ready */ +#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ + 0x00000003 /* Incorrect parameter value */ +#define FAPI_STATUS_FSM_ERROR 0x00000004 /* Operation failed */ + +/****************************************************************************** +* +* Define used by the flash programming and erase functions +* +******************************************************************************/ +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) + +/****************************************************************************** +* +* Define used for access to factory configuration area. +* +******************************************************************************/ +#define FCFG1_OFFSET 0x1000 + +/****************************************************************************** +* +* Define for the clock frequencey input to the flash module in number of MHz +* +******************************************************************************/ +#define FLASH_MODULE_CLK_FREQ 48 + +/****************************************************************************** +* +* Defined values for Flash State Machine commands +* +******************************************************************************/ +typedef enum { + FAPI_PROGRAM_DATA = 0x0002, /* Program data. */ + FAPI_ERASE_SECTOR = 0x0006, /* Erase sector. */ + FAPI_ERASE_BANK = 0x0008, /* Erase bank. */ + FAPI_VALIDATE_SECTOR = 0x000E, /* Validate sector. */ + FAPI_CLEAR_STATUS = 0x0010, /* Clear status. */ + FAPI_PROGRAM_RESUME = 0x0014, /* Program resume. */ + FAPI_ERASE_RESUME = 0x0016, /* Erase resume. */ + FAPI_CLEAR_MORE = 0x0018, /* Clear more. */ + FAPI_PROGRAM_SECTOR = 0x0020, /* Program sector. */ + FAPI_ERASE_OTP = 0x0030 /* Erase OTP. */ +} flash_state_command_t; + +/****************************************************************************** +* +* Defines for values written to the FLASH_O_FSM_WR_ENA register +* +******************************************************************************/ +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 + +/****************************************************************************** +* +* Defines for the bank power mode field the FLASH_O_FBFALLBACK register +* +******************************************************************************/ +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 + +/****************************************************************************** +* +* Defines for the bank grace period and pump grace period +* +******************************************************************************/ +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 + +/****************************************************************************** +* +* Defines for the FW flag bits in the FLASH_O_FWFLAG register +* +******************************************************************************/ +#define FW_WRT_TRIMMED 0x00000001 + +/****************************************************************************** +* +* Defines used by the flash programming functions +* +******************************************************************************/ +typedef volatile uint8_t fwp_write_byte; +#define FWPWRITE_BYTE_ADDRESS \ + ((fwp_write_byte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) + +/****************************************************************************** +* +* Define for FSM command execution +* +******************************************************************************/ +#define FLASH_CMD_EXEC 0x15 + +/****************************************************************************** +* +* Get size of a flash sector in number of bytes. +* +* This function will return the size of a flash sector in number of bytes. +* +* Returns size of a flash sector in number of bytes. +* +******************************************************************************/ +static inline uint32_t flash_sector_size_get(void) +{ + uint32_t sector_size_in_kbyte; + + sector_size_in_kbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> + FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; + + /* Return flash sector size in number of bytes. */ + return sector_size_in_kbyte * 1024; +} + +/****************************************************************************** +* +* Get the size of the flash. +* +* This function returns the size of the flash main bank in number of bytes. +* +* Returns the flash size in number of bytes. +* +******************************************************************************/ +static inline uint32_t flash_size_get(void) +{ + uint32_t num_of_sectors; + + /* Get number of flash sectors */ + num_of_sectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & + FLASH_FLASH_SIZE_SECTORS_M) >> + FLASH_FLASH_SIZE_SECTORS_S; + + /* Return flash size in number of bytes */ + return num_of_sectors * flash_sector_size_get(); +} + +/****************************************************************************** +* +* Checks if the Flash state machine has detected an error. +* +* This function returns the status of the Flash State Machine indicating if +* an error is detected or not. Primary use is to check if an Erase or +* Program operation has failed. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must be called from ROM or +* SRAM while any part of the flash is being programmed or erased. +* +* Returns status of Flash state machine: +* FAPI_STATUS_FSM_ERROR +* FAPI_STATUS_SUCCESS +* +******************************************************************************/ +static inline uint32_t flash_check_fsm_for_error(void) +{ + if (HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) + return FAPI_STATUS_FSM_ERROR; + else + return FAPI_STATUS_SUCCESS; +} + +/****************************************************************************** +* +* Checks if the Flash state machine is ready. +* +* This function returns the status of the Flash State Machine indicating if +* it is ready to accept a new command or not. Primary use is to check if an +* Erase or Program operation has finished. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must be called from ROM or +* SRAM while any part of the flash is being programmed or erased. +* +* Returns readiness status of Flash state machine: +* FAPI_STATUS_FSM_READY +* FAPI_STATUS_FSM_BUSY +* +******************************************************************************/ +static inline uint32_t flash_check_fsm_for_ready(void) +{ + if (HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) + return FAPI_STATUS_FSM_BUSY; + else + return FAPI_STATUS_FSM_READY; +} + +/****************************************************************************** +* +* Erase a flash sector. +* +* This function will erase the specified flash sector. The function will +* not return until the flash sector has been erased or an error condition +* occurred. If flash top sector is erased the function will program the +* the device security data bytes with default values. The device security +* data located in the customer configuration area of the flash top sector, +* must have valid values at all times. These values affect the configuration +* of the device during boot. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must only be executed from ROM +* or SRAM. +* +* sector_address is the starting address in flash of the sector to be +* erased. +* +* Returns the status of the sector erase: +* FAPI_STATUS_SUCCESS : Success. +* FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. +* FAPI_STATUS_FSM_ERROR : Programming error was encountered. +* +******************************************************************************/ +extern uint32_t flash_sector_erase(uint32_t sector_address); + +/****************************************************************************** +* +* Erase all unprotected sectors in the flash main bank. +* +* This function will erase all unprotected flash sectors. The function will +* not return until the flash sectors has been erased or an error condition +* occurred. Since the flash top sector is erased the function will program the +* the device security data bytes with default values. The device security +* data located in the customer configuration area of the flash top sector, +* must have valid values at all times. These values affect the configuration +* of the device during boot. The execution time of the operation increases if +* erase precondition is forced. This will cause the flash module to first +* program all 1 bits in the bank to 0 before the actual erase is started. +* +* force_precondition controls if erase precondition should be forced. +* +* Returns the status of the sector erase: +* FAPI_STATUS_SUCCESS : Success +* FAPI_STATUS_FSM_ERROR : Erase error was encountered. +* +******************************************************************************/ +extern uint32_t flash_bank_erase(bool force_precondition); + +/****************************************************************************** +* +* Programs unprotected main bank flash sectors. +* +* This function will program a sequence of bytes into the on-chip flash. +* Programming each location consists of the result of an AND operation +* of the new data and the existing data; in other words bits that contain +* 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed +* to 1. Therefore, a byte can be programmed multiple times as long as these +* rules are followed; if a program operation attempts to change a 0 bit to +* a 1 bit, that bit will not have its value changed. +* +* This function will not return until the data has been programmed or an +* programming error has occurred. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. This function must only be executed from ROM +* or SRAM. +* +* The data_buffer pointer cannot point to flash. +* +* data_buffer is a pointer to the data to be programmed. +* address is the starting address in flash to be programmed. +* count is the number of bytes to be programmed. +* +* Returns status of the flash programming: +* FAPI_STATUS_SUCCESS : Success. +* FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. +* FAPI_STATUS_FSM_ERROR : Programming error was encountered. +* +******************************************************************************/ +extern uint32_t flash_program(uint8_t *data_buffer, uint32_t address, + uint32_t count); + +/****************************************************************************** +* +* Disables all sectors for erase and programming on the active bank. +* +* This function disables all sectors for erase and programming on the active +* bank and enables the Idle Reading Power reduction mode if no low power +* mode is configured. Furthermore, an additional level of protection from +* erase is enabled. +* +* Please note that code can not execute in flash while any part of the flash +* is being programmed or erased. +* +******************************************************************************/ +extern void flash_disable_sectors_for_write(void); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASH_H */ diff --git a/contrib/loaders/flash/cc26xx/flashloader.c b/contrib/loaders/flash/cc26xx/flashloader.c new file mode 100644 index 0000000..2eaf618 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flashloader.c @@ -0,0 +1,177 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "flashloader.h" +#include "flash.h" + +/* Array holding erased state of the flash sectors. */ +static bool g_is_erased[FLASH_MAX_SECTOR_COUNT]; + +extern uint8_t g_retain_buf[]; + +uint32_t flashloader_init(struct flash_params *params, uint8_t *buf1, + uint8_t *buf2) +{ + /* Initialize params buffers */ + memset((void *)params, 0, 2 * sizeof(struct flash_params)); + params[0].buf_addr = (uint32_t)buf1; + params[1].buf_addr = (uint32_t)buf2; + + /* Mark all sectors at "not erased" */ + memset(g_is_erased, false, sizeof(g_is_erased)); + + return STATUS_OK; +} + +uint32_t flashloader_erase_and_program(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ + if (byte_count > BUFFER_LEN) + return STATUS_FAILED_INVALID_ARGUMENTS; + + /* Erase affected sectors */ + uint32_t status = flashloader_erase_sectors(address, byte_count); + + if (status != STATUS_OK) + return status; + + /* Program data */ + status = flashloader_program(src, address, byte_count); + + return status; +} + +uint32_t flashloader_program_with_retain(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ +#if (BUFFER_LEN > FLASH_ERASE_SIZE) +#error Buffer size cannot be larger than the flash sector size! +#endif + + uint32_t first_sector_idx; + uint32_t last_sector_idx; + uint32_t status = STATUS_OK; + uint32_t i; + + first_sector_idx = flashloader_address_to_sector(address); + last_sector_idx = flashloader_address_to_sector(address + byte_count - 1); + + /* Mark all sectors as "not erased" before starting */ + memset(g_is_erased, false, sizeof(g_is_erased)); + + uint32_t sec_offset = address % FLASH_ERASE_SIZE; + uint32_t curr_count; + uint32_t src_offset = 0; + + for (i = first_sector_idx; i <= last_sector_idx; i++) { + + /* Chop off at sector boundary if data goes into the next sector. */ + curr_count = byte_count; + if ((address + byte_count) > ((i+1) * FLASH_ERASE_SIZE)) + curr_count -= (address + byte_count) % FLASH_ERASE_SIZE; + + /* Copy flash sector to retain buffer */ + memcpy(g_retain_buf, (void *)(i * FLASH_ERASE_SIZE), FLASH_ERASE_SIZE); + + /* Copy data buffer to retain buffer */ + memcpy(&g_retain_buf[sec_offset], &src[src_offset], curr_count); + + /* Erase and program from retain buffer */ + status = flashloader_erase_and_program(g_retain_buf, + (i * FLASH_ERASE_SIZE), FLASH_ERASE_SIZE); + if (status != STATUS_OK) + return status; + + address += curr_count; + sec_offset = address % FLASH_ERASE_SIZE; + byte_count -= curr_count; + src_offset += curr_count; + } + + return status; +} + +uint32_t flashloader_erase_all(void) +{ + if (flash_bank_erase(true) != FAPI_STATUS_SUCCESS) + return STATUS_FAILED_ERASE_ALL; + + memset(g_is_erased, true, sizeof(g_is_erased)); + + return STATUS_OK; +} + +uint32_t flashloader_erase_sectors(uint32_t address, uint32_t byte_count) +{ + uint32_t first_sector_idx; + uint32_t last_sector_idx; + uint32_t status; + uint32_t idx; + + /* Floor address to the start of the sector and convert to sector number */ + first_sector_idx = flashloader_address_to_sector(address); + last_sector_idx = flashloader_address_to_sector(address + byte_count - 1); + + /* Erase given sector(s) */ + for (idx = first_sector_idx; idx <= last_sector_idx; idx++) { + + /* Only erase sectors that haven't already been erased */ + if (g_is_erased[idx] == false) { + status = flash_sector_erase(idx * FLASH_ERASE_SIZE); + if (status != FAPI_STATUS_SUCCESS) { + status = (STATUS_FAILED_SECTOR_ERASE | + ((idx << STATUS_EXT_INFO_S) & STATUS_EXT_INFO_M) | + ((status << STATUS_ROM_CODE_S) & STATUS_ROM_CODE_M)); + return status; + } + g_is_erased[idx] = true; + } + } + + return STATUS_OK; +} + +uint32_t flashloader_program(uint8_t *src, uint32_t address, + uint32_t byte_count) +{ + uint32_t status = flash_program(src, address, byte_count); + if (status != FAPI_STATUS_SUCCESS) { + status = (STATUS_FAILED_PROGRAM | + ((status << STATUS_ROM_CODE_S) & STATUS_ROM_CODE_M)); + } + + return STATUS_OK; +} diff --git a/contrib/loaders/flash/cc26xx/flashloader.h b/contrib/loaders/flash/cc26xx/flashloader.h new file mode 100644 index 0000000..aec74aa --- /dev/null +++ b/contrib/loaders/flash/cc26xx/flashloader.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H +#define OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H + +#include <stdint.h> +#include <stdbool.h> +#include <string.h> +#include "flash.h" + +/* Number of elements in an array */ +#define NELEMS(a) (sizeof(a) / sizeof(a[0])) + +struct __attribute__((__packed__)) flash_params { + uint32_t dest; /* Destination address in flash */ + uint32_t len; /* Number of bytes */ + uint32_t cmd; /* Command */ + uint32_t full; /* Handshake signal. Is buffer ready? */ + uint32_t buf_addr; /* Address of data buffer. */ +}; + +typedef enum { + CMD_NO_ACTION = 0, /* No action, default value */ + CMD_ERASE_ALL = 1, /* Erase all unprotected sectors */ + CMD_PROGRAM = 2, /* Program data */ + CMD_ERASE_AND_PROGRAM = 3, /* Erase and program data */ + CMD_ERASE_AND_PROGRAM_WITH_RETAIN = 4, /* Erase and program, but retain */ + /* sector data outside given range */ + CMD_ERASE_SECTORS = 5 /* Erase unprotected sectors */ +} flash_commands_t; + +typedef enum { + BUFFER_EMPTY = 0x0, /* No data in buffer, flags last task complete */ + BUFFER_FULL = 0xFFFFFFFF /* Buffer has data, flags next task to start */ +} flash_handshake_t; + +#define STATUS_FLASHLOADER_STATUS_M 0x0000FFFF +#define STATUS_FLASHLOADER_STATUS_S 0 +#define STATUS_ROM_CODE_M 0x00FF0000 +#define STATUS_ROM_CODE_S 16 +#define STATUS_EXT_INFO_M 0xFF000000 +#define STATUS_EXT_INFO_S 24 + +typedef enum { + STATUS_OK = 0, + STATUS_FAILED_ERASE_ALL = 0x101, + STATUS_FAILED_SECTOR_ERASE = 0x102, + STATUS_FAILED_PROGRAM = 0x103, + STATUS_FAILED_INVALID_ARGUMENTS = 0x104, + STATUS_FAILED_UNKNOWN_COMMAND = 0x105, +} flash_status_t; + +/* The buffer size used by the flashloader. The size of 1 flash sector. */ +#define BUFFER_LEN FLASH_ERASE_SIZE + +/* +* This function initializes the flashloader. The application must +* allocate memory for the two data buffers and the flash_params structures. +* +* params Pointer an flash_params array with 2 elements. +* buf1 Pointer to data buffer 1 +* buf2 Pointer to data buffer 2 +* +* Returns STATUS_OK +* +*/ +extern uint32_t flashloader_init(struct flash_params *params, uint8_t *buf1, + uint8_t *buf2); + +/* +* Erase and program the necessary sectors. Data outside the given +* range will be deleted. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. For status on failure: +* See flashloader_program() and flashloader_erase_sectors(). +* +*/ +extern uint32_t flashloader_erase_and_program(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Erase and program the device sectors. Data outside the given +* data range will be kept unchanged. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. For status on failure: +* See flashloader_program() and flashloader_erase_sectors(). +* +*/ +extern uint32_t flashloader_program_with_retain(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Erases all flash sectors (that are not write-protected). +* +* Returns STATUS_OK on success. +* +*/ +extern uint32_t flashloader_erase_all(void); + +/* +* Erases the flash sectors affected by the given range. +* +* This function only erases sectors that are not already erased. +* +* start_addr The first address in the range. +* byte_count The number of bytes in the range. +* +* Returns STATUS_OK on success. Returns a combined status on failure: +* [31:24] The sector that failed. +* [23:16] ROM function status code. 0 means success. +* [16: 0] STATUS_FAILED_SECTOR_ERASE +* +*/ +extern uint32_t flashloader_erase_sectors(uint32_t start_addr, + uint32_t byte_count); + +/* +* Program the given range. +* +* This function does not erase anything, it assumes the sectors are ready to +* be programmed. +* +* src Pointer to buffer containing the data. +* address Start address in device flash +* byte_count The number of bytes to program +* +* Returns STATUS_OK on success. Returns a combined status value on failure: +* [31:16] ROM function status code. 0 means success. +* [15:0 ] STATUS_FAILED_PROGRAM +* +*/ +extern uint32_t flashloader_program(uint8_t *src, uint32_t address, + uint32_t byte_count); + +/* +* Convert the input address into a sector number. +* +* address The address. +* +* Returns the flash sector which the address resides in. The first sector +* is sector 0. +* +*/ +static inline uint32_t flashloader_address_to_sector(uint32_t address) + { return (address / FLASH_ERASE_SIZE); }; + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_FLASHLOADER_H */ diff --git a/contrib/loaders/flash/cc26xx/hw_regs.h b/contrib/loaders/flash/cc26xx/hw_regs.h new file mode 100644 index 0000000..830d3af --- /dev/null +++ b/contrib/loaders/flash/cc26xx/hw_regs.h @@ -0,0 +1,1382 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H +#define OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H + +/****************************************************************************** +* +* Macros for direct hardware access. +* +* If using these macros the programmer should be aware of any limitations to +* the address accessed i.e. if it supports word and/or byte access. +* +******************************************************************************/ +/* Word (32 bit) access to address x */ +/* Read example : my32BitVar = HWREG(base_addr + offset) ; */ +/* Write example : HWREG(base_addr + offset) = my32BitVar ; */ +#define HWREG(x) (*((volatile unsigned long *)(x))) + +/* Half word (16 bit) access to address x */ +/* Read example : my16BitVar = HWREGH(base_addr + offset) ; */ +/* Write example : HWREGH(base_addr + offset) = my16BitVar ; */ +#define HWREGH(x) (*((volatile unsigned short *)(x))) + +/* Byte (8 bit) access to address x */ +/* Read example : my8BitVar = HWREGB(base_addr + offset) ; */ +/* Write example : HWREGB(base_addr + offset) = my8BitVar ; */ +#define HWREGB(x) (*((volatile unsigned char *)(x))) + +/****************************************************************************** +* +* Macro for access to bit-band supported addresses via the bit-band region. +* +* Macro calculates the corresponding address to access in the bit-band region +* based on the actual address of the memory/register and the bit number. +* +* Do NOT use this macro to access the bit-band region directly! +* +******************************************************************************/ +/* Bit-band access to address x bit number b using word access (32 bit) */ +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + +/****************************************************************************** +* +* Memory mapped components base address definitions +* +******************************************************************************/ +#define FLASH_BASE 0x40030000 +#define FLASH_CFG_BASE 0x50000000 +#define AON_PMCTL_BASE 0x40090000 + +/****************************************************************************** +* +* This section defines the register offsets of FLASH component +* +******************************************************************************/ + +/* FMC and Efuse Status */ +#define FLASH_O_STAT 0x0000001C + +/* Configuration */ +#define FLASH_O_CFG 0x00000024 + +/* Flash Size Configuration */ +#define FLASH_O_FLASH_SIZE 0x0000002C + +/* Firmware Lock */ +#define FLASH_O_FWLOCK 0x0000003C + +/* Firmware Flags */ +#define FLASH_O_FWFLAG 0x00000040 + +/* FMC Read Control */ +#define FLASH_O_FRDCTL 0x00002000 + +/* FMC Bank Protection */ +#define FLASH_O_FBPROT 0x00002030 + +/* FMC Bank Sector Enable */ +#define FLASH_O_FBSE 0x00002034 + +/* FMC Module Access Control */ +#define FLASH_O_FMAC 0x00002050 + +/* FMC Module Status */ +#define FLASH_O_FMSTAT 0x00002054 + +/* FMC Flash Lock */ +#define FLASH_O_FLOCK 0x00002064 + +/* FMC VREADCT Trim */ +#define FLASH_O_FVREADCT 0x00002080 + +/* FMC VHVCT1 Trim */ +#define FLASH_O_FVHVCT1 0x00002084 + +/* FMC VHVCT2 Trim */ +#define FLASH_O_FVHVCT2 0x00002088 + +/* FMC VNVCT Trim */ +#define FLASH_O_FVNVCT 0x00002090 + +/* FMC VSL_P Trim */ +#define FLASH_O_FVSLP 0x00002094 + +/* FMC VWLCT Trim */ +#define FLASH_O_FVWLCT 0x00002098 + +/* FMC Sequential Pump Information */ +#define FLASH_O_FSEQPMP 0x000020A8 + +/* FMC FSM Command */ +#define FLASH_O_FSM_CMD 0x0000220C + +/* FMC FSM Program/Erase Operation Setup */ +#define FLASH_O_FSM_PE_OSU 0x00002210 + +/* FMC FSM Voltage Status Setup */ +#define FLASH_O_FSM_VSTAT 0x00002214 + +/* FMC FSM Program/Erase Verify Setup */ +#define FLASH_O_FSM_PE_VSU 0x00002218 + +/* FMC FSM Compare Verify Setup */ +#define FLASH_O_FSM_CMP_VSU 0x0000221C + +/* FMC FSM EXECUTEZ to Valid Data */ +#define FLASH_O_FSM_EX_VAL 0x00002220 + +/* FMC FSM Read Mode Hold */ +#define FLASH_O_FSM_RD_H 0x00002224 + +/* FMC FSM Program Hold */ +#define FLASH_O_FSM_P_OH 0x00002228 + +/* FMC FSM Erase Operation Hold */ +#define FLASH_O_FSM_ERA_OH 0x0000222C + +/* FMC FSM Program/Erase Verify Hold */ +#define FLASH_O_FSM_PE_VH 0x00002234 + +/* FMC FSM Program Pulse Width */ +#define FLASH_O_FSM_PRG_PW 0x00002240 + +/* FMC FSM Erase Pulse Width */ +#define FLASH_O_FSM_ERA_PW 0x00002244 + +/* FMC FSM Maximum Programming Pulses */ +#define FLASH_O_FSM_PRG_PUL 0x00002268 + +/* FMC FSM Maximum Erase Pulses */ +#define FLASH_O_FSM_ERA_PUL 0x0000226C + +/* FMC FSM EC Step Size */ +#define FLASH_O_FSM_STEP_SIZE 0x00002270 + +/* FMC FSM EC Step Height */ +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 + +/* FMC FSM_ST_MACHINE */ +#define FLASH_O_FSM_ST_MACHINE 0x0000227C + +/* FMC FSM Register Write Enable */ +#define FLASH_O_FSM_WR_ENA 0x00002288 + +/* FMC FSM Command Execute */ +#define FLASH_O_FSM_EXECUTE 0x000022B4 + +/* FMC FSM Sector Erased 1 */ +#define FLASH_O_FSM_SECTOR1 0x000022C0 + +/* FMC FSM Sector Erased 2 */ +#define FLASH_O_FSM_SECTOR2 0x000022C4 + +/* FMC Flash Bank 0 Starting Address */ +#define FLASH_O_FCFG_B0_START 0x00002410 + +/* FMC Flash Bank 0 Sector Size 0 */ +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 + +/****************************************************************************** +* +* Register: FLASH_O_STAT +* +******************************************************************************/ +/* Field: [2] SAMHOLD_DIS +* +* Status indicator of flash sample and hold sequencing logic. This bit will go +* to 1 some delay after CFG.DIS_IDLE is set to 1. +* 0: Not disabled +* 1: Sample and hold disabled and stable */ +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 + +/* Field: [1] BUSY +* +* Fast version of the FMC FMSTAT.BUSY bit. +* This flag is valid immediately after the operation setting it (FMSTAT.BUSY +* is delayed some cycles) +* 0 : Not busy +* 1 : Busy */ +#define FLASH_STAT_BUSY 0x00000002 + +/****************************************************************************** +* +* Register: FLASH_O_CFG +* +******************************************************************************/ +/* Field: [8] STANDBY_MODE_SEL +* +* [Configured by boot firmware] +* STANDBY mode selection control. This bit, in conjunction with +* STANDBY_PW_SEL, determine which 1 of 4 sub-modes is selected for control of +* the behavior and timing of the STANDBY input to the pump. +* +* 0 : Legacy PG1 behavior is selected when STANDBY_PW_SEL = 00. This is +* referred to as sub-mode 1. When STANDBY_PW_SEL != 00, then sub-mode 2 +* behavior is selected. STANDBY will be glitchy in these modes. +* 1 : STANDBY pulse-width counter modes selected. In these two modes (referred +* to as sub-mode 3 and sub-mode 4), the low time pulse width of the STANDBY +* signal to the pump, is controlled by a programmable timer. STANDBY will not +* be glitchy in these modes. */ +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 + +/* Field: [7:6] STANDBY_PW_SEL +* +* [Configured by boot firmware] +* STANDBY pulse width counter selection control. These bits, in conjunction +* with STANDBY_MODE_SEL, determine which 1 of 4 sub-modes is selected for +* control of the behavior and timing of the STANDBY input to the pump. +* +* 00 : Legacy PG1 behavior is selected when STANDBY_MODE_SEL=0. Sub-mode 4 is +* selected when STANDBY_MODE_SEL=1. In sub-mode 4, STANDBY will be low for at +* least 9 pump clock cycles. +* 01 : Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 9 +* pump clock cycles. +* 10: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 5 pump +* clock cycles. +* 11: Sub-mode 2 or 3 is selected, and STANDBY will be low for at least 13 +* pump clock cycles. */ +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 + +/* Field: [1] DIS_STANDBY +* +* [Configured by boot firmware] +* Disable standby functionality in read idle state */ +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 + +/* Field: [0] DIS_IDLE +* +* [Configured by boot firmware] +* Disable sample and hold functionality in read idle state */ +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FLASH_SIZE +* +******************************************************************************/ +/* Field: [7:0] SECTORS +* +* [Configured by boot firmware] +* Flash size. The number of flash sectors in the configured device. Read +* access to sectors equal to this number or higher will result in an error. +* The CCFG area is the sector (SECTORS - 1) Writing to this register is +* disabled by the CFG.CONFIGURED bit. */ +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FRDCTL +* +******************************************************************************/ +/* Field: [11:8] RWAIT +* +* [Configured by boot firmware] +* FMC Wait State. This field determines the FLCLK period during FMC controlled +* flash accesses: +* - During power up/ power down / low power mode +* - During FSM operations like program, erase +* - During software interface mode (see FLOCK , FBSTROBES registers) +* FLCLK_period = HCLK_period X (RWAIT + 1), +* FSM state machine operations are usually twice this amount. This value +* should never be set less than 2. */ +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FBPROT +* +******************************************************************************/ +/* Field: [0] PROTL1DIS +* +* Level 1 Protection Disable bit. Setting this bit disables protection from +* writing to the FBAC.OTPPROTDIS bits as well as the Sector Enable registers +* FBSE for all banks. Clearing this bit enables protection and disables write +* access to the FBAC.OTPPROTDIS register bits and FBSE register. */ +#define FLASH_FBPROT_PROTL1DIS 0x00000001 + +/****************************************************************************** +* +* Register: FLASH_O_FMSTAT +* +******************************************************************************/ +/* Field: [4] CSTAT +* +* Command Status. Once the FSM starts any failure will set this bit. When set, +* this bit informs the host that the program, erase, or validate sector +* command failed and the command was stopped. This bit is cleared by the +* Clear_Status command. For some errors, this will be the only indication of +* an FSM error because the cause does not fall within the other error bit +* types. */ +#define FLASH_FMSTAT_CSTAT 0x00000010 + +/****************************************************************************** +* +* Register: FLASH_O_FVREADCT +* +******************************************************************************/ +/* Field: [3:0] VREADCT +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of +* wordline power supply for read mode. */ +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FVHVCT1 +* +******************************************************************************/ +/* Field: [23:20] TRIM13_E +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during erase operation. */ +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 + +/* Field: [19:16] VHVCT_E +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during erase operation. */ +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 + +/* Field: [7:4] TRIM13_PV +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program verify operation. */ +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 + +/* Field: [3:0] VHVCT_PV +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program verify operation. */ +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FVHVCT2 +* +******************************************************************************/ +/* Field: [23:20] TRIM13_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program operation. */ +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 + +/* Field: [19:16] VHVCT_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* voltage supply input during program operation. */ +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 + +/****************************************************************************** +* +* Register: FLASH_O_FVNVCT +* +******************************************************************************/ +/* Field: [12:8] VCG2P5CT +* +* [Configured by boot firmware] +* These bits control the voltage level for the VCG 2.5 CT pump voltage. */ +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FVSLP +* +******************************************************************************/ +/* Field: [15:12] VSL_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of high +* current power input during program operation. */ +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FVWLCT +* +******************************************************************************/ +/* Field: [4:0] VWLCT_P +* +* [Configured by boot firmware] +* These bits control the voltage level for the specified pump voltage of +* wordline power supply during programming operations. */ +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSEQPMP +* +******************************************************************************/ +/* Field: [21:20] TRIM_1P7 +* +* [Configured by boot firmware] +* This register goes directly to the pump's TRIM_1P7 port pins. */ +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 + +/* Field: [14:12] VIN_AT_X +* +* This register controls to the pump's VIN_AT_XPX port pins with the following +* encoding; +* +* If VIN_BY_PASS=0 then pump VIN_AT_XPX is equal to VIN_AT_XIN input ports +* from the BATMON logic after clocking through synchronizers and the sequence +* checker FSM logic contained in the flash wrapper. +* +* If VIN_BY_PASS=1 and VIN_AT_X=??? +* +* 0: then all pump VIN_AT_XPX signals are 0. +* 1: then pump VIN_AT_1P7 is set. +* 2: then pump VIN_AT_2P1 is also set. +* 3: then pump VIN_AT_2P4 is also set. +* 4-7: then pump VIN_AT_3P0 is also set (ie all VIN_AT_XPX signals are 1). */ +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 + +/* Field: [8] VIN_BY_PASS +* +* [Configured by boot firmware] +* +* When this bit is a zero, the pump's VIN_AT_XPX ports comes from the FMC +* input port VIN_AT_XIN. +* +* When this bit is a one, the pump's VIN_AT_XPX ports comes from the VIN_AT_X +* bits in 14:12. */ +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_OSU +* +******************************************************************************/ +/* Field: [15:8] PGM_OSU +* +* [Configured by boot firmware] +* Program Operation Setup time. This determines the flash clocks from the mode +* change to program, to the start of the program pulse. */ +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 + +/* Field: [7:0] ERA_OSU +* +* [Configured by boot firmware] +* Erase Operation Setup time. This determines the flash clocks from the mode +* change to erase, to the start of the erase pulse. */ +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_VSTAT +* +******************************************************************************/ +/* Field: [15:12] VSTAT_CNT +* +* [Configured by boot firmware] +* Voltage Status Count. Gives the number of consecutive HCLK pulses that must +* be out of range before a voltage-out-of-range status error is given in +* FMSTAT.VOLSTAT. One pulse in range will reset the counter. This is mainly a +* glitch filter on the voltage status pump signal. */ +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_VSU +* +******************************************************************************/ +/* Field: [15:8] PGM_VSU +* +* [Configured by boot firmware] +* Program Verify Setup time. This determines the flash clocks from the mode +* change to program verify, to the change of address and the beginning of the +* address setup time. */ +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 + +/* Field: [7:0] ERA_VSU +* +* [Configured by boot firmware] +* Erase Verify Setup time. This determines the flash clocks from the mode +* change to erase verify, to the change of address and the beginning of the +* address setup time. */ +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_CMP_VSU +* +******************************************************************************/ +/* Field: [15:12] ADD_EXZ +* +* [Configured by boot firmware] +* Address to EXECUTEZ low setup time. This determines the flash clocks from +* the row address change to the time EXECUTEZ goes low. All operations use +* this value. */ +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_EX_VAL +* +******************************************************************************/ +/* Field: [15:8] REP_VSU +* +* [Configured by boot firmware] +* Repeat Verify action setup. If a program or erase operation advances to the +* program_verify or erase_verify then this special shorter mode transition +* time will be used in place of FSM_PE_VSU.PGM_VSU or FSM_PE_VSU.ERA_VSU +* times. */ +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 + +/* Field: [7:0] EXE_VALD +* +* [Configured by boot firmware] +* EXECUTEZ low to valid Data. Determines the number of Flash clock cycles from +* EXECUTEZ going low to the time the verify data can be read in the program +* verify mode. Erase and compact verify is always a constant value which is +* currently set at one flash clock. This value must be greater than 0. */ +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_RD_H +* +******************************************************************************/ +/* Field: [7:0] RD_H +* +* [Configured by boot firmware] +* Read mode hold. This determines the number of flash clocks from the start of +* the Read mode at the end of the operations until the FSM clears the +* FMSTAT.BUSY. Writing a zero to this register will result in a value of 1. +* The reset value of this register is 0x3Ah before FMC version 3.0.10.0 and +* 0x5Ah after this version. */ +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_P_OH +* +******************************************************************************/ +/* Field: [15:8] PGM_OH +* +* [Configured by boot firmware] +* EXECUTEZ high to mode change. This value determines the flash clocks from +* the EXECUTEZ going high at the end of a program operation to the time the +* mode can change. This value must be greater than or equal to one. */ +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_OH +* +******************************************************************************/ +/* Field: [15:0] ERA_OH +* +* [Configured by boot firmware] +* EXECUTEZ high to mode change. Determines the flash clocks from EXECUTEZ +* going high at the end of an erase operation to the time the mode can change. +* If a bank erase is happening, then this is the time to when the TEZ and TCR +* values for bank erase are released. The mode changes 10 flash clocks after +* they are released. This value must be greater than or equal to one. */ +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PE_VH +* +******************************************************************************/ +/* Field: [15:8] PGM_VH +* +* [Configured by boot firmware] +* Program Verify Hold. This register determines the flash clocks from EXECUTEZ +* going high after a program verify to a mode change. This value must be +* greater than or equal to one */ +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PRG_PW +* +******************************************************************************/ +/* Field: [15:0] PROG_PUL_WIDTH +* +* [Configured by boot firmware] +* Program Pulse width.This register gives the number of flash clocks that the +* EXECUTEZ signal is low in a program operation. */ +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_PW +* +******************************************************************************/ +/* Field: [31:0] FSM_ERA_PW +* +* [Configured by boot firmware] +* Erase Pulse width. This register gives the number flash clocks that the +* EXECUTEZ signal is low in an erase operation. */ +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_PRG_PUL +* +******************************************************************************/ +/* Field: [19:16] BEG_EC_LEVEL +* +* [Configured by boot firmware] +* Beginning level for VHVCT. This determines the beginning level for VHVCT +* that is used during erase modes. The pump voltage control registers supply +* the other values that do not change during FSM operations. The reset value +* is the same as FVHVCT1.VHVCT_E. */ +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 + +/* Field: [11:0] MAX_PRG_PUL +* +* [Configured by boot firmware] +* Maximum Programming Pulses. This register contains the maximum number of +* programming pulses allowed at one address. If it takes any more than this +* amount during a programming operation then the FSM will exit with an error +* and with the program violation, FMSTAT.PGV set, and the general error set, +* FMSTAT.CSTAT. Setting FSM_ST_MACHINE.OVERRIDE to 0 will allow more than this +* maximum value to occur without an error. During pre-conditioning for an +* erase operation the FSM programs all the bits to zero. If the maximum number +* of programming pulses is reached for an address, the FSM will continue with +* the next address and set the FMSTAT.PCV and the general error FMSTAT.CSTAT. +* If the FSM_ST_MACHINE.PREC_STOP_EN is set then the FSM will stop with errors +* when more than the maximum number of pulses is needed. The +* FSM_ST_MACHINE.OVERRIDE bit will take priority over the +* FSM_ST_MACHINE.PREC_STOP_EN and continue doing pulses without setting the +* error bits. Suspend operations will count a pulse if the program operation +* began no matter how long the pulse lasted before is was suspended. Frequent +* suspend or auto-suspend operations could result in max_pulse count error. */ +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ERA_PUL +* +******************************************************************************/ +/* Field: [19:16] MAX_EC_LEVEL +* +* [Configured by boot firmware] +* Maximum VHVCT Level. This determines the maximum level for VHVCT that is +* used during erase modes. The FSM will stop advancing VHVCT once it counts up +* to the MAX_EC_LEVEL level from the beginning level. The MAX_EC_LEVEL + +* FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT must be less than 0x200. The reset value +* is the same as FVHVCT1.VHVCT_E. */ +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 + +/* Field: [11:0] MAX_ERA_PUL +* +* [Configured by boot firmware] +* Maximum Erase Pulses. This register contains the maximum number of erase +* pulses allowed at one address. If it takes any more than this amount the FSM +* will exit with an error and with both the FMSTAT.EV and FMSTAT.CSTAT bits +* set. Setting FSM_ST_MACHINE.OVERRIDE to 1 will allow more than this maximum +* value to occur without an error. Suspend operations will count a pulse if +* the erase operation began no matter how long the pulse lasted before is was +* suspended. Frequent suspend or auto-suspend operations could result in +* max_pulse count error. */ +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_STEP_SIZE +* +******************************************************************************/ +/* Field: [24:16] EC_STEP_SIZE +* +* [Configured by boot firmware] +* VHVCT Step Size. This is the number of erase pulses that must be completed +* for each level before the FSM increments the FSM_PUL_CNTR.CUR_EC_LEVEL to +* the next higher level. Actual erase pulses per level equals (EC_STEP_SIZE +* +1). The stepping is only needed for the VHVCT voltage. */ +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 + +/****************************************************************************** +* +* Register: FLASH_O_FSM_EC_STEP_HEIGHT +* +******************************************************************************/ +/* Field: [3:0] EC_STEP_HEIGHT +* +* [Configured by boot firmware] +* Height of each EC step. This is the number of counts that the +* FSM_PUL_CNTR.CUR_EC_LEVEL will increment when going to a new level. Actual +* count size equals (EC_STEP_HEIGHT + 1). The stepping applies only to the +* VHVCT voltage. If adding the height to the FSM_PUL_CNTR.CUR_EC_LEVEL results +* in a value higher than the FSM_ERA_PUL.MAX_EC_LEVEL then the +* FSM_PUL_CNTR.CUR_EC_LEVEL will be lowered to the MAX LEVEL before it is used +* in the next erase pulse. */ +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F + +/****************************************************************************** +* +* Register: FLASH_O_FSM_ST_MACHINE +* +******************************************************************************/ +/* Field: [23] DO_PRECOND +* +* [Configured by boot firmware] +* Do preconditioning. When this bit is a one, the FSM will precondition the +* sector or bank before doing an erase operation. When zero, the FSM will just +* begin with the erase verify and skip the preconditioning. */ +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 + +/* Field: [14] ONE_TIME_GOOD +* +* [Configured by boot firmware] +* One Time Good function. If this bit is a one then the 'One Time Good' +* function is enabled for all program operations. This includes operations +* inside the erase functions and other functions. When zero, this function is +* disabled for all modes. When doing the One Time Good function, the FSM will +* attempt to program a location with data. If a desired zero bit reads back +* from the flash one time as good then that bit is blocked from writing a zero +* to the flash array again for this address. When the address changes, all +* bits are unblocked. This prevents a bit from reading 0 in one programming +* pulse and then 1 in the next programming pulse. On the second time the bit +* would get a programming pulse even though it read 0 in an earlier read. If +* this bit is a zero then the zero bits will be masked for each program verify +* operation. It is recommended for this bit to be set to 1. */ +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 + +/****************************************************************************** +* +* Register: FLASH_O_FCFG_B0_SSIZE0 +* +******************************************************************************/ +/* Field: [3:0] B0_SECT_SIZE +* +* Size of sectors in Bank 0. Common sector size for all sectors in the bank in +* 1K bytes multiples. +* 0x0: 0K bytes +* 0x1: 1K bytes(FLES) +* 0x2: 2K bytes +* 0x4: 4K bytes (FLEE) +* ... +* 0xF: 15K bytes */ +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 + +/****************************************************************************** +* +* This section defines the register offsets of FCFG1 component +* +******************************************************************************/ + +/* Flash Erase and Program Setup Time */ +#define FCFG1_O_FLASH_E_P 0x00000170 + +/* Flash Compaction, Execute, Program and Read */ +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 + +/* Flash Program, Read, and Program Verify */ +#define FCFG1_O_FLASH_P_R_PV 0x00000178 + +/* Flash Erase Hold and Sequence */ +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C + +/* Flash VHV Erase */ +#define FCFG1_O_FLASH_VHV_E 0x00000180 + +/* Flash Program Pulse */ +#define FCFG1_O_FLASH_PP 0x00000184 + +/* Flash Program and Erase Pulse */ +#define FCFG1_O_FLASH_PROG_EP 0x00000188 + +/* Flash Erase Pulse Width */ +#define FCFG1_O_FLASH_ERA_PW 0x0000018C + +/* Flash VHV */ +#define FCFG1_O_FLASH_VHV 0x00000190 + +/* Flash VHV Program Verify */ +#define FCFG1_O_FLASH_VHV_PV 0x00000194 + +/* Flash Voltages */ +#define FCFG1_O_FLASH_V 0x00000198 + +/* Flash OTP Data 3 */ +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 + +/* Flash OTP Data 4 */ +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_E_P +* +******************************************************************************/ +/* Field: [31:24] PSU +* +* Program setup time in cycles. Value will be written to +* FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 + +/* Field: [23:16] ESU +* +* Erase setup time in cycles. Value will be written to +* FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 + +/* Field: [15:8] PVSU +* +* Program verify setup time in cycles. Value will be written to +* FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 + +/* Field: [7:0] EVSU +* +* Erase verify setup time in cycles. Value will be written to +* FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_C_E_P_R +* +******************************************************************************/ +/* Field: [31:24] RVSU +* +* Repeat verify setup time in cycles. Used for repeated verifies during +* program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the +* flash device driver when an erase/program operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 + +/* Field: [23:16] PV_ACCESS +* +* Program verify EXECUTEZ->data valid time in half-microseconds. Value +* will be converted to number of FCLK cycles by by flash device driver and the +* converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 + +/* Field: [15:12] A_EXEZ_SETUP +* +* Address->EXECUTEZ setup time in cycles. Value will be written to +* FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_P_R_PV +* +******************************************************************************/ +/* Field: [31:24] PH +* +* Program hold time in half-microseconds after SAFELV goes high. Value will be +* converted to number of FCLK cycles by the flash device driver and the +* converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 + +/* Field: [23:16] RH +* +* Read hold/mode transition time in cycles. Value will be written to the RD_H +* field bits[7:0] of the FSM_RD_H register in the flash module by the flash +* device driver when an erase/program operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 + +/* Field: [15:8] PVH +* +* Program verify hold time in half-microseconds after SAFELV goes high. Value +* will be converted to number of FCLK cycles by the flash device driver and +* the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_EH_SEQ +* +******************************************************************************/ +/* Field: [31:24] EH +* +* Erase hold time in half-microseconds after SAFELV goes high. Value will be +* converted to number of FCLK cycles by the flash device driver and the +* converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program +* operation is initiated. */ +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 + +/* Field: [15:12] VSTAT +* +* Max number of HCLK cycles allowed for pump brown-out. Value will be written +* to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. */ +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV_E +* +******************************************************************************/ +/* Field: [31:16] VHV_E_START +* +* Starting VHV-Erase CT for stairstep erase. Value will be written to +* FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 + +/* Field: [15:0] VHV_E_STEP_HIGHT +* +* Number of VHV CTs to step after each erase pulse (up to the max). The actual +* FMC register value should be one less than this since the FMC starts +* counting from zero. Value will be written to +* FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is +* initiated. */ +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_PP +* +******************************************************************************/ +/* Field: [15:0] MAX_PP +* +* Max program pulse limit per program operation. Value will be written to +* FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. */ +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_PROG_EP +* +******************************************************************************/ +/* Field: [31:16] MAX_EP +* +* Max erase pulse limit per erase operation. Value will be written to +* FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated. */ +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 + +/* Field: [15:0] PROGRAM_PW +* +* Program pulse width in half-microseconds. Value will be converted to number +* of FCLK cycles by the flash device driver and the converted value is written +* to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is +* initiated. */ +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_ERA_PW +* +******************************************************************************/ +/* Field: [31:0] ERASE_PW +* +* Erase pulse width in half-microseconds. Value will be converted to number of +* FCLK cycles by the flash device driver and the converted value is written to +* FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. */ +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV +* +******************************************************************************/ +/* Field: [27:24] TRIM13_P +* +* Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 + +/* Field: [19:16] VHV_P +* +* Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 + +/* Field: [11:8] TRIM13_E +* +* Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 + +/* Field: [3:0] VHV_E +* +* Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver +* when an erase/program operation is initiated */ +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_VHV_PV +* +******************************************************************************/ +/* Field: [27:24] TRIM13_PV +* +* Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 + +/* Field: [19:16] VHV_PV +* +* Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 + +/* Field: [15:8] VCG2P5 +* +* Control gate voltage during read, read margin, and erase verify. Value will +* be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_V +* +******************************************************************************/ +/* Field: [31:24] VSL_P +* +* Sourceline voltage applied to the selected block during programming. Value +* will be written to FLASH:FVSLP.VSL_P by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 + +/* Field: [23:16] VWL_P +* +* Wordline voltage applied to the selected half-row during programming. Value +* will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an +* erase/program operation is initiated. */ +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 + +/* Field: [15:8] V_READ +* +* Wordline voltage applied to the selected block during reads and verifies. +* Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver +* when an erase/program operation is initiated. */ +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_OTP_DATA3 +* +******************************************************************************/ +/* Field: [31:23] EC_STEP_SIZE +* +* Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash +* device driver when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 + +/* Field: [22] DO_PRECOND +* +* Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device +* driver when a erase/program operation is initiated. +* +* Note that during a Total Erase operation the flash bank will always be +* erased with Precondition enabled independent of the value of this FCFG1 bit +* field. */ +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 + +/* Field: [21:18] MAX_EC_LEVEL +* +* Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device +* driver when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 + +/* Field: [17:16] TRIM_1P7 +* +* Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver +* when a erase/program operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 + +/****************************************************************************** +* +* Register: FCFG1_O_FLASH_OTP_DATA4 +* +******************************************************************************/ +/* Field: [31] STANDBY_MODE_SEL_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 + +/* Field: [30:29] STANDBY_PW_SEL_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 + +/* Field: [28] DIS_STANDBY_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation +* is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 + +/* Field: [27] DIS_IDLE_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is +* initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 + +/* Field: [26:24] VIN_AT_X_INT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 + +/* Field: [23] STANDBY_MODE_SEL_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 + +/* Field: [22:21] STANDBY_PW_SEL_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 + +/* Field: [20] DIS_STANDBY_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation +* is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 + +/* Field: [19] DIS_IDLE_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is +* initiated. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 + +/* Field: [18:16] VIN_AT_X_EXT_WRT +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write +* operation is initiated. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 + +/* Field: [15] STANDBY_MODE_SEL_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 + +/* Field: [14:13] STANDBY_PW_SEL_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 + +/* Field: [12] DIS_STANDBY_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 + +/* Field: [11] DIS_IDLE_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 + +/* Field: [10:8] VIN_AT_X_INT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 + +/* Field: [7] STANDBY_MODE_SEL_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 + +/* Field: [6:5] STANDBY_PW_SEL_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 + +/* Field: [4] DIS_STANDBY_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 + +/* Field: [3] DIS_IDLE_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device +* driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 + +/* Field: [2:0] VIN_AT_X_EXT_RD +* +* If AON_PMCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to +* FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash +* device driver FW after completion of a flash write operation. */ +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 + +/****************************************************************************** +* +* This section defines the register offsets of AON_PMCTL component +* +******************************************************************************/ + +/* Power Management Control */ +#if defined(DEVICE_CC26X2) +/* Agama (CC26x2) specific definition */ +#define AON_PMCTL_O_PWRCTL 0x00000010 +#elif defined(DEVICE_CC26X0) +/* Chameleon (CC26x0) specific definition */ +#define AON_PMCTL_O_PWRCTL 0x00000000 +#endif + +/* Field: [1] EXT_REG_MODE +* +* Status of source for VDDRsupply: +* +* 0: DCDC or GLDO are generating VDDR +* 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR */ +#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 + +#endif /* #ifndef OPENOCD_LOADERS_FLASH_CC26XX_HW_REGS_H */ diff --git a/contrib/loaders/flash/cc26xx/main.c b/contrib/loaders/flash/cc26xx/main.c new file mode 100644 index 0000000..13204b4 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/main.c @@ -0,0 +1,179 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "flashloader.h" + +/* Data buffers used by host to communicate with flashloader */ + +/* Flashloader parameter structure. */ +__attribute__ ((section(".buffers.g_cfg"))) +volatile struct flash_params g_cfg[2]; +/* Data buffer 1. */ +__attribute__ ((section(".buffers.g_buf1"))) +uint8_t g_buf1[BUFFER_LEN]; +/* Data buffer 2. */ +__attribute__ ((section(".buffers.g_buf2"))) +uint8_t g_buf2[BUFFER_LEN]; + +/* Buffer used for program with retain feature */ +__attribute__ ((section(".buffers.g_retain_buf"))) +uint8_t g_retain_buf[BUFFER_LEN]; + +uint32_t g_curr_buf; /* Current buffer used. */ +uint32_t g_vims_ctl; /* Saved flash cache state. */ + +/****************************************************************************** +* +* This function stores the current VIMS configuration before +* - disabling VIMS flash cache +* - flushing the flash line buffers. +* +* Note Not using driverlib calls because it requires using "NO_ROM" define in +* order to work for both Cha. R1 and R2 using the same code. Manually +* doing the steps to minimize code footprint. +* +******************************************************************************/ +static void disable_flash_cache() +{ + /* 1. Make sure VIMS is not currently changing mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; + + /* Save current VIMS:CTL state */ + g_vims_ctl = HWREG(0x40034004); + + /* 2. Set VIMS mode to OFF and disable flash line buffers */ + uint32_t new_vims_ctl = g_vims_ctl | 0x33; + HWREG(0x40034004) = new_vims_ctl; + + /* 3. Wait for VIMS to have changed mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; +} + +/****************************************************************************** +* +* This function restores the VIMS configuration saved off by +* disable_flash_cache(). +* +* Note Not using driverlib calls because it requires using "NO_ROM" define in +* order to work for both Cha. R1 and R2 using the same code. Manually +* doing the steps to minimize code footprint. +* +******************************************************************************/ +static void restore_cache_state() +{ + HWREG(0x40034004) = g_vims_ctl; + + /* Wait for VIMS to have changed mode (VIMS:STAT register) */ + while ((HWREG(0x40034000) & 0x00000008) == 0x8) + ; +} + +/****************************************************************************** +* +* CC13xx/CC26xx flashloader main function. +* +******************************************************************************/ +int main(void) +{ + flashloader_init((struct flash_params *)g_cfg, g_buf1, g_buf2); + + g_curr_buf = 0; /* start with the first buffer */ + uint32_t status; + + while (1) { + /* Wait for host to signal buffer is ready */ + while (g_cfg[g_curr_buf].full == BUFFER_EMPTY) + ; + + disable_flash_cache(); + + /* Perform requested task */ + switch (g_cfg[g_curr_buf].cmd) { + case CMD_ERASE_ALL: + status = flashloader_erase_all(); + break; + case CMD_PROGRAM: + status = + flashloader_program( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_AND_PROGRAM: + status = + flashloader_erase_and_program( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_AND_PROGRAM_WITH_RETAIN: + status = + flashloader_program_with_retain( + (uint8_t *)g_cfg[g_curr_buf].buf_addr, + g_cfg[g_curr_buf].dest, g_cfg[g_curr_buf].len); + break; + case CMD_ERASE_SECTORS: + status = + flashloader_erase_sectors(g_cfg[g_curr_buf].dest, + g_cfg[g_curr_buf].len); + break; + default: + status = STATUS_FAILED_UNKNOWN_COMMAND; + break; + } + + restore_cache_state(); + + /* Enter infinite loop on error condition */ + if (status != STATUS_OK) { + g_cfg[g_curr_buf].full = status; + while (1) + ; + } + + /* Mark current task complete, and begin looking at next buffer */ + g_cfg[g_curr_buf].full = BUFFER_EMPTY; + g_curr_buf ^= 1; + } +} + +void _exit(int status) +{ + /* Enter infinite loop on hitting an exit condition */ + (void)status; /* Unused parameter */ + while (1) + ; +} diff --git a/contrib/loaders/flash/cc26xx/startup.c b/contrib/loaders/flash/cc26xx/startup.c new file mode 100644 index 0000000..70fd836 --- /dev/null +++ b/contrib/loaders/flash/cc26xx/startup.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> + +/****************************************************************************** +* +* The entry point for the application startup code. +* +******************************************************************************/ +extern int main(void); + +/****************************************************************************** +* +* Reserve space for the system stack. +* +******************************************************************************/ +__attribute__ ((section(".stack"))) +static uint32_t stack[100]; +const uint32_t stack_pntr = (uint32_t)stack + sizeof(stack); + +/****************************************************************************** +* +* The following are constructs created by the linker indicating where the +* the "bss" and "ebss" segments reside in memory. +* +******************************************************************************/ +extern uint32_t _bss; +extern uint32_t _ebss; + +/****************************************************************************** +* +* This is the entry point that handles setting the stack within the allowed +* workspace, initializing the .bss segment, and then jumping to main. +* +******************************************************************************/ +__attribute__ ((section(".entry"))) +void entry(void) +{ + /* Workaround for ITT instructions. */ + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + __asm(" NOP"); + + /* Initialize stack pointer */ + __asm(" ldr sp, =stack_pntr"); + + /* Zero fill the bss segment. */ + __asm(" ldr r0, =_bss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + " .thumb_func\n" + " zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + /* Call the application's entry point. */ + main(); + + /* If we ever return, enter an infinite loop */ + while (1) + ; +} diff --git a/contrib/loaders/flash/cc3220sf/Makefile b/contrib/loaders/flash/cc3220sf/Makefile new file mode 100644 index 0000000..d1dcc25 --- /dev/null +++ b/contrib/loaders/flash/cc3220sf/Makefile @@ -0,0 +1,19 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- +AS = $(CROSS_COMPILE)as +OBJCOPY = $(CROSS_COMPILE)objcopy + +all: cc3220sf.inc + +%.elf: %.s + $(AS) $< -o $@ + +%.bin: %.elf + $(OBJCOPY) -Obinary $< $@ + +%.inc: %.bin + $(BIN2C) < $< > $@ + +clean: + -rm -f *.elf *.bin *.inc diff --git a/contrib/loaders/flash/cc3220sf/cc3220sf.inc b/contrib/loaders/flash/cc3220sf/cc3220sf.inc new file mode 100644 index 0000000..29c54c6 --- /dev/null +++ b/contrib/loaders/flash/cc3220sf/cc3220sf.inc @@ -0,0 +1,10 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0xdf,0xf8,0x7c,0xa0,0xdf,0xf8,0x7c,0xb0,0xdf,0xf8,0x7c,0xc0,0x01,0xf0,0x7f,0x03, +0x00,0x2b,0x1e,0xd1,0x4f,0xf0,0x00,0x04,0xcc,0xf8,0x00,0x10,0x03,0x68,0xcb,0xf8, +0x00,0x30,0x0b,0xf1,0x04,0x0b,0x00,0xf1,0x04,0x00,0xa2,0xf1,0x01,0x02,0x04,0xf1, +0x01,0x04,0x01,0xf1,0x04,0x01,0x00,0x2a,0x01,0xd0,0x20,0x2c,0xee,0xd1,0xcc,0xf8, +0x20,0xa0,0xdc,0xf8,0x20,0x30,0x13,0xf0,0x01,0x0f,0xfa,0xd1,0x00,0x2a,0xd7,0xd1, +0x13,0xe0,0xcc,0xf8,0x00,0x10,0x03,0x68,0xcc,0xf8,0x04,0x30,0xcc,0xf8,0x08,0xa0, +0xdc,0xf8,0x08,0x30,0x13,0xf0,0x01,0x0f,0xfa,0xd1,0xa2,0xf1,0x01,0x02,0x00,0xf1, +0x04,0x00,0x01,0xf1,0x04,0x01,0x00,0x2a,0xc2,0xd1,0x00,0xbe,0x01,0xbe,0xfc,0xe7, +0x01,0x00,0x42,0xa4,0x00,0xd1,0x0f,0x40,0x00,0xd0,0x0f,0x40, diff --git a/contrib/loaders/flash/cc3220sf/cc3220sf.s b/contrib/loaders/flash/cc3220sf/cc3220sf.s new file mode 100644 index 0000000..cffcfa0 --- /dev/null +++ b/contrib/loaders/flash/cc3220sf/cc3220sf.s @@ -0,0 +1,93 @@ +/*************************************************************************** + * Copyright (C) 2017 by Texas Instruments, Inc. * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * + ***************************************************************************/ + + /* Params: + * r0 = buffer start address (in) + * r1 = flash destination address (in) + * r2 = number of words to write (in/out) + */ + + .text + .cpu cortex-m4 + .code 16 + .thumb + .syntax unified + + .align 2 + + /* r3 = scratchpad + * r4 = buffer word counter + * r10 = flash programming key + * r11 = base FWB address + * r12 = base flash regs address + */ + +start: + ldr r10, =0xa4420001 /* flash programming key */ + ldr r11, =0x400fd100 /* base of FWB */ + ldr r12, =0x400fd000 /* base of flash regs */ + and r3, r1, #0x7f /* is the dest address 32 word aligned? */ + cmp r3, #0 + bne program_word /* if not aligned do one word at a time */ + + /* program using the write buffers */ +program_buffer: + mov r4, #0 /* start the buffer word counter at 0 */ + str r1, [r12] /* store the dest addr in FMA */ +fill_buffer: + ldr r3, [r0] /* get the word to write to FWB */ + str r3, [r11] /* store the word in the FWB */ + add r11, r11, #4 /* increment the FWB pointer */ + add r0, r0, #4 /* increment the source pointer */ + sub r2, r2, #1 /* decrement the total word counter */ + add r4, r4, #1 /* increment the buffer word counter */ + add r1, r1, #4 /* increment the dest pointer */ + cmp r2, #0 /* is the total word counter now 0? */ + beq buffer_ready /* go to end if total word counter is 0 */ + cmp r4, #32 /* is the buffer word counter now 32? */ + bne fill_buffer /* go to continue to fill buffer */ +buffer_ready: + str r10, [r12, #0x20] /* store the key and write bit to FMC2 */ +wait_buffer_done: + ldr r3, [r12, #0x20] /* read FMC2 */ + tst r3, #1 /* see if the write bit is cleared */ + bne wait_buffer_done /* go to read FMC2 if bit not cleared */ + cmp r2, #0 /* is the total word counter now 0? */ + bne start /* go if there is more to program */ + b exit + + /* program just one word */ +program_word: + str r1, [r12] /* store the dest addr in FMA */ + ldr r3, [r0] /* get the word to write to FMD */ + str r3, [r12, #0x4] /* store the word in FMD */ + str r10, [r12, #0x8] /* store the key and write bit to FMC */ +wait_word_done: + ldr r3, [r12, #0x8] /* read FMC */ + tst r3, #1 /* see if the write bit is cleared */ + bne wait_word_done /* go to read FMC if bit not cleared */ + sub r2, r2, #1 /* decrement the total word counter */ + add r0, r0, #4 /* increment the source pointer */ + add r1, r1, #4 /* increment the dest pointer */ + cmp r2, #0 /* is the total word counter now 0 */ + bne start /* go if there is more to program */ + + /* end */ +exit: + bkpt #0 + bkpt #1 + b exit diff --git a/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h new file mode 100644 index 0000000..d406d60 --- /dev/null +++ b/contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* +* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H +#define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H + +#include <stddef.h> +#include <stdint.h> + +/* RAM loader */ +static const uint32_t RAM_LOADER_START = 0x20000000u; /* Code space */ +static const uint32_t RAM_LOADER_MAIN = 0x20000110u; /* Code space */ +static const uint32_t RAM_LOADER_BUFFER1 = 0x20002000u; /* SBUS data space */ +static const uint32_t RAM_LOADER_BUFFER2 = 0x20003000u; /* SBUS data space */ +static const uint32_t RAM_LOADER_STACK = 0x20002000u; /* SBUS data space */ + +/* Address for flash function to be executed */ +static const uint32_t FLASH_FUNCTION_ADDRESS = 0x20000150u; + +enum flash_command { + FLASH_NO_COMMAND = 0, + FLASH_MASS_ERASE = 1, + FLASH_SECTOR_ERASE = 2, + FLASH_PROGRAM = 4, + FLASH_INIT = 8, + FLASH_EXIT = 16, + FLASH_CONTINUOUS_PROGRAM = 32 +}; + +/* Address for algorithm program and flash buffer */ +static const uint32_t DST_ADDRESS = 0x2000015Cu; +static const uint32_t SRC_LENGTH_ADDRESS = 0x20000160u; +static const uint32_t BUFFER1_STATUS_REGISTER = 0x20000164u; +static const uint32_t BUFFER2_STATUS_REGISTER = 0x20000168u; +static const uint32_t BUFFER_INACTIVE = 0x00000000u; +static const uint32_t BUFFER_ACTIVE = 0x00000001u; +static const uint32_t BUFFER_DATA_READY = 0x00000010u; +static const size_t SRC_LENGTH_MAX = 4096u; + +/* Erase options */ +static const uint32_t ERASE_PARAM_ADDRESS = 0x2000016Cu; +static const uint32_t ERASE_MAIN = 0x00000001u; +static const uint32_t ERASE_INFO = 0x00000002u; + +/* Unlock BSL */ +static const uint32_t UNLOCK_BSL_ADDRESS = 0x20000170u; +static const uint32_t LOCK_BSL_KEY = 0x00000000u; +static const uint32_t UNLOCK_BSL_KEY = 0x0000000Bu; + +/* Address for return code */ +static const uint32_t RETURN_CODE_ADDRESS = 0x20000154u; + +/* Return codes */ +static const uint32_t FLASH_BUSY = 0x00000001u; +static const uint32_t FLASH_SUCCESS = 0x00000ACEu; +static const uint32_t FLASH_ERROR = 0x0000DEADu; +static const uint32_t FLASH_TIMEOUT_ERROR = 0xDEAD0000u; +static const uint32_t FLASH_VERIFY_ERROR = 0xDEADDEADu; +static const uint32_t FLASH_WRONG_COMMAND = 0x00000BADu; +static const uint32_t FLASH_POWER_ERROR = 0x00DEAD00u; + +/* Device ID address */ +static const uint32_t DEVICE_ID_ADDRESS = 0x0020100Cu; +static const uint32_t PC_REGISTER = 15u; +static const uint32_t SP_REGISTER = 13u; + +/* CS silicon and boot code revisions */ +static const uint32_t SILICON_REV_ADDRESS = 0x00201010u; +static const uint32_t SILICON_REV_A = 0x00000041u; +static const uint32_t SILICON_REV_B = 0x00000042u; +static const uint32_t SILICON_REV_C = 0x00000043u; +static const uint32_t SILICON_REV_D = 0x00000044u; +static const uint32_t SILICON_REV_E = 0x00000045u; +static const uint32_t SILICON_REV_F = 0x00000046u; +static const uint32_t SILICON_REV_G = 0x00000047u; +static const uint32_t SILICON_REV_H = 0x00000048u; +static const uint32_t SILICON_REV_I = 0x00000049u; +static const uint32_t SILICON_REV_B_WRONG = 0x00004100u; + +struct flash_interface { + volatile uint32_t FLASH_FUNCTION; + volatile uint32_t RETURN_CODE; + volatile uint32_t _RESERVED0; + volatile uint32_t DST_ADDRESS; + volatile uint32_t SRC_LENGTH; + volatile uint32_t BUFFER1_STATUS_REGISTER; + volatile uint32_t BUFFER2_STATUS_REGISTER; + volatile uint32_t ERASE_PARAM; + volatile uint32_t UNLOCK_BSL; +}; + +#define FLASH_LOADER_BASE ((uint32_t)0x20000150u) +#define FLASH_LOADER ((struct flash_interface *) FLASH_LOADER_BASE) + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H */ diff --git a/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h new file mode 100644 index 0000000..c438097 --- /dev/null +++ b/contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* +* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H +#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H + +#include <stddef.h> +#include <stdint.h> + +/* RAM loader */ +static const uint32_t RAM_LOADER_START = 0x01000000u; /* Code space */ +static const uint32_t RAM_LOADER_MAIN = 0x01000110u; /* Code space */ +static const uint32_t RAM_LOADER_BUFFER1 = 0x20002000u; /* SBUS data space */ +static const uint32_t RAM_LOADER_BUFFER2 = 0x20003000u; /* SBUS data space */ +static const uint32_t RAM_LOADER_STACK = 0x20002000u; /* SBUS data space */ + +/* Address for flash function to be executed */ +static const uint32_t FLASH_FUNCTION_ADDRESS = 0x20000150u; + +enum flash_command { + FLASH_NO_COMMAND = 0, + FLASH_MASS_ERASE = 1, + FLASH_SECTOR_ERASE = 2, + FLASH_PROGRAM = 4, + FLASH_INIT = 8, + FLASH_EXIT = 16, + FLASH_CONTINUOUS_PROGRAM = 32 +}; + +/* Address for algorithm program and flash buffer */ +static const uint32_t DST_ADDRESS = 0x2000015Cu; +static const uint32_t SRC_LENGTH_ADDRESS = 0x20000160u; +static const uint32_t BUFFER1_STATUS_REGISTER = 0x20000164u; +static const uint32_t BUFFER2_STATUS_REGISTER = 0x20000168u; +static const uint32_t BUFFER_INACTIVE = 0x00000000u; +static const uint32_t BUFFER_ACTIVE = 0x00000001u; +static const uint32_t BUFFER_DATA_READY = 0x00000010u; +static const size_t SRC_LENGTH_MAX = 4096u; + +/* erase options */ +static const uint32_t ERASE_PARAM_ADDRESS = 0x2000016Cu; +static const uint32_t ERASE_MAIN = 0x00000001u; +static const uint32_t ERASE_INFO = 0x00000002u; + +/* Unlock BSL */ +static const uint32_t UNLOCK_BSL_ADDRESS = 0x20000170u; +static const uint32_t LOCK_BSL_KEY = 0x00000000u; +static const uint32_t UNLOCK_BSL_KEY = 0x0000000Bu; + +/* Address for return code */ +static const uint32_t RETURN_CODE_ADDRESS = 0x20000154u; + +/* Return codes */ +static const uint32_t FLASH_BUSY = 0x00000001u; +static const uint32_t FLASH_SUCCESS = 0x00000ACEu; +static const uint32_t FLASH_ERROR = 0x0000DEADu; +static const uint32_t FLASH_TIMEOUT_ERROR = 0xDEAD0000u; +static const uint32_t FLASH_VERIFY_ERROR = 0xDEADDEADu; +static const uint32_t FLASH_WRONG_COMMAND = 0x00000BADu; +static const uint32_t FLASH_POWER_ERROR = 0x00DEAD00u; + +/* Device ID address */ +static const uint32_t DEVICE_ID_ADDRESS = 0x0020100Cu; +static const uint32_t PC_REGISTER = 15u; +static const uint32_t SP_REGISTER = 13u; + +/* CS silicon and boot code revisions */ +static const uint32_t SILICON_REV_ADDRESS = 0x00201010u; +static const uint32_t SILICON_REV_A = 0x00000041u; +static const uint32_t SILICON_REV_B = 0x00000042u; +static const uint32_t SILICON_REV_C = 0x00000043u; +static const uint32_t SILICON_REV_D = 0x00000044u; +static const uint32_t SILICON_REV_E = 0x00000045u; +static const uint32_t SILICON_REV_F = 0x00000046u; +static const uint32_t SILICON_REV_G = 0x00000047u; +static const uint32_t SILICON_REV_H = 0x00000048u; +static const uint32_t SILICON_REV_I = 0x00000049u; +static const uint32_t SILICON_REV_B_WRONG = 0x00004100u; + +struct flash_interface { + volatile uint32_t FLASH_FUNCTION; + volatile uint32_t RETURN_CODE; + volatile uint32_t _RESERVED0; + volatile uint32_t DST_ADDRESS; + volatile uint32_t SRC_LENGTH; + volatile uint32_t BUFFER1_STATUS_REGISTER; + volatile uint32_t BUFFER2_STATUS_REGISTER; + volatile uint32_t ERASE_PARAM; + volatile uint32_t UNLOCK_BSL; +}; + +#define FLASH_LOADER_BASE ((uint32_t)0x20000150u) +#define FLASH_LOADER ((struct flash_interface *) FLASH_LOADER_BASE) + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H */ diff --git a/contrib/loaders/flash/msp432/Makefile b/contrib/loaders/flash/msp432/Makefile new file mode 100644 index 0000000..6083331 --- /dev/null +++ b/contrib/loaders/flash/msp432/Makefile @@ -0,0 +1,99 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- +GCC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +FLAGS = -mcpu=cortex-m4 -march=armv7e-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mthumb + +CFLAGS = -c -DNO_MSP_CLASSIC_DEFINES -Dgcc -Wall -ffunction-sections +CFLAGS += -fdata-sections -std=c99 -O4 + +LDFLAGS = -lc -lnosys -Wl,--gc-sections + +MSP432E4X_OBJS := \ +msp432e4x/driverlib.o \ +msp432e4x/main_msp432e4x.o \ +msp432e4x/startup_msp432e4.o + +MSP432P401X_OBJS := \ +msp432p401x/driverlib.o \ +msp432p401x/main_msp432p401x.o \ +msp432p401x/startup_msp432p4.o + +MSP432P411X_OBJS := \ +msp432p411x/driverlib.o \ +msp432p411x/main_msp432p411x.o \ +msp432p411x/startup_msp432p4.o + +all: msp432e4x_algo.inc msp432p401x_algo.inc msp432p411x_algo.inc + +msp432e4x/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) -D__MSP432E4X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +msp432p401x/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) -D__MSP432P401X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +msp432p411x/%.o: %.c + @echo 'Building file: $<' + @echo 'Invoking: GNU Compiler' + $(GCC) -D__MSP432P411X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)" + @echo 'Finished building: $<' + @echo ' ' + +msp432e4x_algo.out: $(MSP432E4X_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432E4X_OBJS) -Tmsp432e4x/msp432e4x.lds + @echo 'Finished building target: $@' + @echo ' ' + +msp432p401x_algo.out: $(MSP432P401X_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432P401X_OBJS) -Tmsp432p401x/msp432p401x.lds + @echo 'Finished building target: $@' + @echo ' ' + +msp432p411x_algo.out: $(MSP432P411X_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: GNU Linker' + $(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432P411X_OBJS) -Tmsp432p411x/msp432p411x.lds + @echo 'Finished building target: $@' + @echo ' ' + +%.bin: %.out + @echo 'Building target: $@' + @echo 'Invoking: GNU Objcopy Utility' + $(OBJCOPY) -Obinary $< $@ + @echo 'Finished building target: $@' + @echo ' ' + +%.inc: %.bin + @echo 'Building target: $@' + @echo 'Invoking Bin2Char Script' + $(BIN2C) < $< > $@ + rm $< $*.out + @echo 'Finished building target: $@' + @echo ' ' + +clean: + @echo 'Cleaning Targets and Build Artifacts' + rm -rf *.inc *.bin *.out *.map + rm -rf msp432e4x/*.o msp432e4x/*.d + rm -rf msp432p401x/*.o msp432p401x/*.d + rm -rf msp432p411x/*.o msp432p411x/*.d + @echo 'Finished clean' + @echo ' ' + +.PRECIOUS: %.bin + +.PHONY: all clean diff --git a/contrib/loaders/flash/msp432/driverlib.c b/contrib/loaders/flash/msp432/driverlib.c new file mode 100644 index 0000000..a4f5416 --- /dev/null +++ b/contrib/loaders/flash/msp432/driverlib.c @@ -0,0 +1,472 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "driverlib.h" + +/* + * Wrapper function for the CPSID instruction. + * Returns the state of PRIMASK on entry. + */ +uint32_t __attribute__((naked)) cpu_cpsid(void) +{ + uint32_t ret; + + /* Read PRIMASK and disable interrupts. */ + __asm(" mrs r0, PRIMASK\n" + " cpsid i\n" + " bx lr\n" + : "=r" (ret)); + + /* + * The return is handled in the inline assembly, but the compiler will + * still complain if there is not an explicit return here (despite the fact + * that this does not result in any code being produced because of the + * naked attribute). + */ + return ret; +} + +/* Wrapper function for the CPUWFI instruction. */ +void __attribute__((naked)) cpu_wfi(void) +{ + /* Wait for the next interrupt. */ + __asm(" wfi\n" + " bx lr\n"); +} + +/* Power Control Module APIs */ +#if defined(PCM) + +static bool __pcm_set_core_voltage_level_advanced(uint_fast8_t voltage_level, + uint32_t time_out, bool blocking) +{ + uint8_t power_mode; + uint8_t current_voltage_level; + uint32_t reg_value; + bool bool_timeout; + + /* Getting current power mode and level */ + power_mode = pcm_get_power_mode(); + current_voltage_level = pcm_get_core_voltage_level(); + + bool_timeout = time_out > 0 ? true : false; + + /* If we are already at the power mode they requested, return */ + if (current_voltage_level == voltage_level) + return true; + + while (current_voltage_level != voltage_level) { + + reg_value = PCM->CTL0; + + switch (pcm_get_power_state()) { + case PCM_AM_LF_VCORE1: + case PCM_AM_DCDC_VCORE1: + case PCM_AM_LDO_VCORE0: + PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1) + | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); + break; + case PCM_AM_LF_VCORE0: + case PCM_AM_DCDC_VCORE0: + case PCM_AM_LDO_VCORE1: + PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0) + | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); + break; + default: + break; + } + + if (blocking) { + while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) { + if (bool_timeout && !(--time_out)) + return false; + } + } else + return true; + + current_voltage_level = pcm_get_core_voltage_level(); + } + + /* Changing the power mode if we are stuck in LDO mode */ + if (power_mode != pcm_get_power_mode()) { + if (power_mode == PCM_DCDC_MODE) + return pcm_set_power_mode(PCM_DCDC_MODE); + else + return pcm_set_power_mode(PCM_LF_MODE); + } + + return true; +} + +bool pcm_set_core_voltage_level(uint_fast8_t voltage_level) +{ + return __pcm_set_core_voltage_level_advanced(voltage_level, 0, true); +} + +uint8_t pcm_get_power_mode(void) +{ + uint8_t current_power_state; + + current_power_state = pcm_get_power_state(); + + switch (current_power_state) { + case PCM_AM_LDO_VCORE0: + case PCM_AM_LDO_VCORE1: + case PCM_LPM0_LDO_VCORE0: + case PCM_LPM0_LDO_VCORE1: + default: + return PCM_LDO_MODE; + case PCM_AM_DCDC_VCORE0: + case PCM_AM_DCDC_VCORE1: + case PCM_LPM0_DCDC_VCORE0: + case PCM_LPM0_DCDC_VCORE1: + return PCM_DCDC_MODE; + case PCM_LPM0_LF_VCORE0: + case PCM_LPM0_LF_VCORE1: + case PCM_AM_LF_VCORE1: + case PCM_AM_LF_VCORE0: + return PCM_LF_MODE; + } +} + +uint8_t pcm_get_core_voltage_level(void) +{ + uint8_t current_power_state = pcm_get_power_state(); + + switch (current_power_state) { + case PCM_AM_LDO_VCORE0: + case PCM_AM_DCDC_VCORE0: + case PCM_AM_LF_VCORE0: + case PCM_LPM0_LDO_VCORE0: + case PCM_LPM0_DCDC_VCORE0: + case PCM_LPM0_LF_VCORE0: + default: + return PCM_VCORE0; + case PCM_AM_LDO_VCORE1: + case PCM_AM_DCDC_VCORE1: + case PCM_AM_LF_VCORE1: + case PCM_LPM0_LDO_VCORE1: + case PCM_LPM0_DCDC_VCORE1: + case PCM_LPM0_LF_VCORE1: + return PCM_VCORE1; + case PCM_LPM3: + return PCM_VCORELPM3; + } +} + +static bool __pcm_set_power_mode_advanced(uint_fast8_t power_mode, + uint32_t time_out, bool blocking) +{ + uint8_t current_power_mode; + uint8_t current_power_state; + uint32_t reg_value; + bool bool_timeout; + + /* Getting Current Power Mode */ + current_power_mode = pcm_get_power_mode(); + + /* If the power mode being set it the same as the current mode, return */ + if (power_mode == current_power_mode) + return true; + + current_power_state = pcm_get_power_state(); + + bool_timeout = time_out > 0 ? true : false; + + /* Go through the while loop while we haven't achieved the power mode */ + while (current_power_mode != power_mode) { + + reg_value = PCM->CTL0; + + switch (current_power_state) { + case PCM_AM_DCDC_VCORE0: + case PCM_AM_LF_VCORE0: + PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0 + | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); + break; + case PCM_AM_LF_VCORE1: + case PCM_AM_DCDC_VCORE1: + PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1 + | (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); + break; + case PCM_AM_LDO_VCORE1: { + if (power_mode == PCM_DCDC_MODE) { + PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1 + | (reg_value & ~(PCM_CTL0_KEY_MASK + | PCM_CTL0_AMR_MASK))); + } else if (power_mode == PCM_LF_MODE) { + PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1 + | (reg_value & ~(PCM_CTL0_KEY_MASK + | PCM_CTL0_AMR_MASK))); + } else + return false; + break; + } + case PCM_AM_LDO_VCORE0: { + if (power_mode == PCM_DCDC_MODE) { + PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0 + | (reg_value & ~(PCM_CTL0_KEY_MASK + | PCM_CTL0_AMR_MASK))); + } else if (power_mode == PCM_LF_MODE) { + PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0 + | (reg_value & ~(PCM_CTL0_KEY_MASK + | PCM_CTL0_AMR_MASK))); + } else + return false; + break; + } + default: + break; + } + + if (blocking) { + while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) { + if (bool_timeout && !(--time_out)) + return false; + } + } else + return true; + + current_power_mode = pcm_get_power_mode(); + current_power_state = pcm_get_power_state(); + } + + return true; +} + +bool pcm_set_power_mode(uint_fast8_t power_mode) +{ + return __pcm_set_power_mode_advanced(power_mode, 0, true); +} + +static bool __pcm_set_power_state_advanced(uint_fast8_t power_state, + uint32_t timeout, bool blocking) +{ + uint8_t current_power_state; + current_power_state = pcm_get_power_state(); + + if (current_power_state == power_state) + return true; + + switch (power_state) { + case PCM_AM_LDO_VCORE0: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE, + timeout, blocking); + case PCM_AM_LDO_VCORE1: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE, + timeout, blocking); + case PCM_AM_DCDC_VCORE0: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE, + timeout, blocking); + case PCM_AM_DCDC_VCORE1: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE, + timeout, blocking); + case PCM_AM_LF_VCORE0: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE, + timeout, blocking); + case PCM_AM_LF_VCORE1: + return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE, + timeout, blocking); + case PCM_LPM0_LDO_VCORE0: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM0_LDO_VCORE1: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM0_DCDC_VCORE0: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM0_DCDC_VCORE1: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM0_LF_VCORE0: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM0_LF_VCORE1: + if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout, + blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE, + timeout, blocking)) + break; + return pcm_goto_lpm0(); + case PCM_LPM3: + return pcm_goto_lpm3(); + case PCM_LPM4: + return pcm_goto_lpm4(); + case PCM_LPM45: + return pcm_shutdown_device(PCM_LPM45); + case PCM_LPM35_VCORE0: + return pcm_shutdown_device(PCM_LPM35_VCORE0); + default: + return false; + } + + return false; +} + +bool pcm_set_power_state(uint_fast8_t power_state) +{ + return __pcm_set_power_state_advanced(power_state, 0, true); +} + +bool pcm_shutdown_device(uint32_t shutdown_mode) +{ + uint32_t shutdown_mode_bits = (shutdown_mode == PCM_LPM45) ? + PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10; + + /* If a power transition is occuring, return false */ + if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) + return false; + + /* Initiating the shutdown */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK; + + PCM->CTL0 = (PCM_KEY | shutdown_mode_bits + | (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK))); + + cpu_wfi(); + + return true; +} + +bool pcm_goto_lpm4(void) +{ + /* Disabling RTC_C and WDT_A */ + wdt_a_hold_timer(); + rtc_c_hold_clock(); + + /* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */ + return pcm_goto_lpm3(); +} + +bool pcm_goto_lpm0(void) +{ + /* If we are in the middle of a state transition, return false */ + if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) + return false; + + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK; + + cpu_wfi(); + + return true; +} + +bool pcm_goto_lpm3(void) +{ + uint_fast8_t current_power_state; + uint_fast8_t current_power_mode; + + /* If we are in the middle of a state transition, return false */ + if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) + return false; + + /* If we are in the middle of a shutdown, return false */ + if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10 + || (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12) + return false; + + current_power_mode = pcm_get_power_mode(); + current_power_state = pcm_get_power_state(); + + if (current_power_mode == PCM_DCDC_MODE) + pcm_set_power_mode(PCM_LDO_MODE); + + /* Clearing the SDR */ + PCM->CTL0 = + (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY; + + /* Setting the sleep deep bit */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK; + + cpu_wfi(); + + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK; + + return pcm_set_power_state(current_power_state); +} + +uint8_t pcm_get_power_state(void) +{ + return (PCM->CTL0 & PCM_CTL0_CPM_MASK) >> PCM_CTL0_CPM_OFS; +} + +#endif + +/* Real Time Clock APIs */ +#if defined(RTC_C) + +void rtc_c_hold_clock(void) +{ + RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; + BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1; + BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; +} + +#endif + +/* Watch Dog Timer APIs */ +#if defined(WDT_A) + +void wdt_a_hold_timer(void) +{ + /* Set Hold bit */ + uint8_t new_wdt_status = (WDT_A->CTL | WDT_A_CTL_HOLD); + + WDT_A->CTL = WDT_A_CTL_PW + new_wdt_status; +} + +#endif diff --git a/contrib/loaders/flash/msp432/driverlib.h b/contrib/loaders/flash/msp432/driverlib.h new file mode 100644 index 0000000..23ba7b5 --- /dev/null +++ b/contrib/loaders/flash/msp432/driverlib.h @@ -0,0 +1,384 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H +#define OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H + +#include <stdint.h> +#include <stdbool.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__MSP432E4X__) +#include "msp432e4x.h" +#elif defined(__MSP432P401X__) +#include "msp432p401x.h" +#elif defined(__MSP432P411X__) +#include "msp432p411x.h" +#else +#error "Failed to match a device specific include file" +#endif + +/* Structure type to access the System Control Block (SCB). */ +struct SCB_Type { + volatile uint32_t CPUID; /* CPUID Base Register */ + volatile uint32_t ICSR; /* Interrupt Control and State Register */ + volatile uint32_t VTOR; /* Vector Table Offset Register */ + volatile uint32_t AIRCR; /* Application Interrupt and Reset Control */ + volatile uint32_t SCR; /* System Control Register */ + volatile uint32_t CCR; /* Configuration Control Register */ + volatile uint8_t SHP[12U]; /* System Handlers Priority Registers */ + volatile uint32_t SHCSR; /* System Handler Control and State */ + volatile uint32_t CFSR; /* Configurable Fault Status Register */ + volatile uint32_t HFSR; /* HardFault Status Register */ + volatile uint32_t DFSR; /* Debug Fault Status Register */ + volatile uint32_t MMFAR; /* MemManage Fault Address Register */ + volatile uint32_t BFAR; /* BusFault Address Register */ + volatile uint32_t AFSR; /* Auxiliary Fault Status Register */ + volatile uint32_t PFR[2U]; /* Processor Feature Register */ + volatile uint32_t DFR; /* Debug Feature Register */ + volatile uint32_t ADR; /* Auxiliary Feature Register */ + volatile uint32_t MMFR[4U]; /* Memory Model Feature Register */ + volatile uint32_t ISAR[5U]; /* Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + volatile uint32_t CPACR; /* Coprocessor Access Control Register */ +}; + +/* SCB:SCR register bits */ +#define SCB_SCR_SLEEPDEEP_POS 2U +#define SCB_SCR_SLEEPDEEP_MSK (1UL << SCB_SCR_SLEEPDEEP_POS) + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /* System Control Space Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /* System Control Block Base Address */ +#define SCB ((struct SCB_Type *)SCB_BASE) /* SCB configuration struct */ + +/* Definitions of standard bits */ +#define BIT0 (uint16_t)(0x0001) +#define BIT1 (uint16_t)(0x0002) +#define BIT2 (uint16_t)(0x0004) +#define BIT3 (uint16_t)(0x0008) +#define BIT4 (uint16_t)(0x0010) +#define BIT5 (uint16_t)(0x0020) +#define BIT6 (uint16_t)(0x0040) +#define BIT7 (uint16_t)(0x0080) +#define BIT8 (uint16_t)(0x0100) +#define BIT9 (uint16_t)(0x0200) +#define BITA (uint16_t)(0x0400) +#define BITB (uint16_t)(0x0800) +#define BITC (uint16_t)(0x1000) +#define BITD (uint16_t)(0x2000) +#define BITE (uint16_t)(0x4000) +#define BITF (uint16_t)(0x8000) +#define BIT(x) ((uint16_t)1 << (x)) + +/* CPU Module prototypes */ +extern uint32_t cpu_cpsid(void); +extern void cpu_wfi(void); + +/* Clock Signal Module constants */ +#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1 +#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4 + +/* Power Control Module constants */ +#define PCM_KEY 0x695A0000 +#define PCM_AM_LDO_VCORE0 0x00 +#define PCM_AM_LDO_VCORE1 0x01 +#define PCM_AM_DCDC_VCORE0 0x04 +#define PCM_AM_DCDC_VCORE1 0x05 +#define PCM_AM_LF_VCORE0 0x08 +#define PCM_AM_LF_VCORE1 0x09 +#define PCM_LPM0_LDO_VCORE0 0x10 +#define PCM_LPM0_LDO_VCORE1 0x11 +#define PCM_LPM0_DCDC_VCORE0 0x14 +#define PCM_LPM0_DCDC_VCORE1 0x15 +#define PCM_LPM0_LF_VCORE0 0x18 +#define PCM_LPM0_LF_VCORE1 0x19 +#define PCM_LPM3 0x20 +#define PCM_LPM4 0x21 +#define PCM_LPM35_VCORE0 0xC0 +#define PCM_LPM45 0xA0 +#define PCM_VCORE0 0x00 +#define PCM_VCORE1 0x01 +#define PCM_VCORELPM3 0x02 +#define PCM_LDO_MODE 0x00 +#define PCM_DCDC_MODE 0x01 +#define PCM_LF_MODE 0x02 + +/* Power Control Module prototypes */ +extern bool pcm_set_core_voltage_level(uint_fast8_t voltage_level); +extern uint8_t pcm_get_core_voltage_level(void); +extern bool pcm_set_power_mode(uint_fast8_t power_mode); +extern uint8_t pcm_get_power_mode(void); +extern bool pcm_set_power_state(uint_fast8_t power_state); +extern uint8_t pcm_get_power_state(void); +extern bool pcm_shutdown_device(uint32_t shutdown_mode); +extern bool pcm_goto_lpm0(void); +extern bool pcm_goto_lpm3(void); +extern bool pcm_goto_lpm4(void); + +/* ROM API Function Pointers */ +#define ROM_API_TABLE ((unsigned long *)0x02000800) +#define ROM_FLASH_CTL_TABLE ((unsigned long *)(ROM_API_TABLE[7])) +#define ROM_PCM_TABLE ((unsigned long *)(ROM_API_TABLE[13])) +#define ROM_WDT_TABLE ((unsigned long *)(ROM_API_TABLE[25])) +#define ROM_SYS_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[26])) +#define ROM_FLASH_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[27])) + +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_UNPROTECT_SECTOR \ + ((bool (*)(uint_fast8_t memory_space, \ + uint32_t sector_mask))ROM_FLASH_CTL_TABLE[4]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_PROTECT_SECTOR \ + ((bool (*)(uint_fast8_t memory_space, \ + uint32_t sector_mask))ROM_FLASH_CTL_TABLE[5]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_PERFORM_MASS_ERASE \ + ((bool (*)(void))ROM_FLASH_CTL_TABLE[8]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_ERASE_SECTOR \ + ((bool (*)(uint32_t addr))ROM_FLASH_CTL_TABLE[9]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_PROGRAM_MEMORY \ + ((bool (*)(void *src, void *dest, uint32_t length))ROM_FLASH_CTL_TABLE[10]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_SET_WAIT_STATE \ + ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_TABLE[21]) +#endif +#if defined(__MSP432P401X__) +#define ROM_FLASH_CTL_GET_WAIT_STATE \ + ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_TABLE[22]) +#endif +#if defined(__MSP432P401X__) +#define ROM_PCM_SET_CORE_VOLTAGE_LEVEL \ + ((bool (*)(uint_fast8_t voltage_level))ROM_PCM_TABLE[0]) +#endif +#if defined(__MSP432P401X__) +#define ROM_PCM_GET_CORE_VOLTAGE_LEVEL \ + ((uint8_t (*)(void))ROM_PCM_TABLE[1]) +#endif +#if defined(__MSP432P401X__) +#define ROM_PCM_SET_POWER_STATE \ + ((bool (*)(uint_fast8_t power_state))ROM_PCM_TABLE[6]) +#endif +#if defined(__MSP432P401X__) +#define ROM_PCM_GET_POWER_STATE \ + ((uint8_t (*)(void))ROM_PCM_TABLE[8]) +#endif +#if defined(__MSP432P401X__) || defined(__MSP432P411X__) +#define ROM_WDT_A_HOLD_TIMER \ + ((void (*)(void))ROM_WDT_TABLE[0]) +#endif +#if defined(__MSP432P411X__) +#define ROM_SYS_CTL_A_GET_FLASH_SIZE \ + ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[1]) +#endif +#if defined(__MSP432P411X__) +#define ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE \ + ((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[18]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_UNPROTECT_MEMORY \ + ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[4]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_PROTECT_MEMORY \ + ((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[5]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_PERFORM_MASS_ERASE \ + ((bool (*)(void))ROM_FLASH_CTL_A_TABLE[8]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_ERASE_SECTOR \ + ((bool (*)(uint32_t addr))ROM_FLASH_CTL_A_TABLE[9]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_PROGRAM_MEMORY \ + ((bool (*)(void *src, void *dest, uint32_t length)) \ + ROM_FLASH_CTL_A_TABLE[10]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_SET_WAIT_STATE \ + ((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_A_TABLE[21]) +#endif +#if defined(__MSP432P411X__) +#define ROM_FLASH_CTL_A_GET_WAIT_STATE \ + ((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_A_TABLE[22]) +#endif + +/* Map API functions to ROM or locally built functions */ +#ifdef ROM_FLASH_CTL_UNPROTECT_SECTOR +#define MAP_FLASH_CTL_UNPROTECT_SECTOR ROM_FLASH_CTL_UNPROTECT_SECTOR +#else +#define MAP_FLASH_CTL_UNPROTECT_SECTOR flash_ctl_unprotect_sector +#endif +#ifdef ROM_FLASH_CTL_PROTECT_SECTOR +#define MAP_FLASH_CTL_PROTECT_SECTOR ROM_FLASH_CTL_PROTECT_SECTOR +#else +#define MAP_FLASH_CTL_PROTECT_SECTOR flash_ctl_protect_sector +#endif +#ifdef ROM_FLASH_CTL_PERFORM_MASS_ERASE +#define MAP_FLASH_CTL_PERFORM_MASS_ERASE ROM_FLASH_CTL_PERFORM_MASS_ERASE +#else +#define MAP_FLASH_CTL_PERFORM_MASS_ERASE flash_ctl_perform_mass_erase +#endif +#ifdef ROM_FLASH_CTL_ERASE_SECTOR +#define MAP_FLASH_CTL_ERASE_SECTOR ROM_FLASH_CTL_ERASE_SECTOR +#else +#define MAP_FLASH_CTL_ERASE_SECTOR flash_ctl_erase_sector +#endif +#ifdef ROM_FLASH_CTL_PROGRAM_MEMORY +#define MAP_FLASH_CTL_PROGRAM_MEMORY ROM_FLASH_CTL_PROGRAM_MEMORY +#else +#define MAP_FLASH_CTL_PROGRAM_MEMORY flash_ctl_program_memory +#endif +#ifdef ROM_FLASH_CTL_SET_WAIT_STATE +#define MAP_FLASH_CTL_SET_WAIT_STATE ROM_FLASH_CTL_SET_WAIT_STATE +#else +#define MAP_FLASH_CTL_SET_WAIT_STATE flash_ctl_set_wait_state +#endif +#ifdef ROM_FLASH_CTL_GET_WAIT_STATE +#define MAP_FLASH_CTL_GET_WAIT_STATE ROM_FLASH_CTL_GET_WAIT_STATE +#else +#define MAP_FLASH_CTL_GET_WAIT_STATE flash_ctl_get_wait_state +#endif +#ifdef ROM_PCM_SET_CORE_VOLTAGE_LEVEL +#define MAP_PCM_SET_CORE_VOLTAGE_LEVEL ROM_PCM_SET_CORE_VOLTAGE_LEVEL +#else +#define MAP_PCM_SET_CORE_VOLTAGE_LEVEL pcm_set_core_voltage_level +#endif +#ifdef ROM_PCM_GET_CORE_VOLTAGE_LEVEL +#define MAP_PCM_GET_CORE_VOLTAGE_LEVEL ROM_PCM_GET_CORE_VOLTAGE_LEVEL +#else +#define MAP_PCM_GET_CORE_VOLTAGE_LEVEL pcm_get_core_voltage_level +#endif +#ifdef ROM_PCM_SET_POWER_STATE +#define MAP_PCM_SET_POWER_STATE ROM_PCM_SET_POWER_STATE +#else +#define MAP_PCM_SET_POWER_STATE pcm_set_power_state +#endif +#ifdef ROM_PCM_GET_POWER_STATE +#define MAP_PCM_GET_POWER_STATE ROM_PCM_GET_POWER_STATE +#else +#define MAP_PCM_GET_POWER_STATE pcm_get_power_state +#endif +#ifdef ROM_WDT_A_HOLD_TIMER +#define MAP_WDT_A_HOLD_TIMER ROM_WDT_A_HOLD_TIMER +#else +#define MAP_WDT_A_HOLD_TIMER wdt_a_hold_timer +#endif +#ifdef ROM_SYS_CTL_A_GET_FLASH_SIZE +#define MAP_SYS_CTL_A_GET_FLASH_SIZE ROM_SYS_CTL_A_GET_FLASH_SIZE +#else +#define MAP_SYS_CTL_A_GET_FLASH_SIZE sys_ctl_a_get_flash_size +#endif +#ifdef ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE +#define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE +#else +#define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE sys_ctl_a_get_info_flash_size +#endif +#ifdef ROM_FLASH_CTL_A_UNPROTECT_MEMORY +#define MAP_FLASH_CTL_A_UNPROTECT_MEMORY ROM_FLASH_CTL_A_UNPROTECT_MEMORY +#else +#define MAP_FLASH_CTL_A_UNPROTECT_MEMORY flash_ctl_a_unprotect_memory +#endif +#ifdef ROM_FLASH_CTL_A_PROTECT_MEMORY +#define MAP_FLASH_CTL_A_PROTECT_MEMORY ROM_FLASH_CTL_A_PROTECT_MEMORY +#else +#define MAP_FLASH_CTL_A_PROTECT_MEMORY flash_ctl_a_protect_memory +#endif +#ifdef ROM_FLASH_CTL_A_PERFORM_MASS_ERASE +#define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE ROM_FLASH_CTL_A_PERFORM_MASS_ERASE +#else +#define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE flash_ctl_a_perform_mass_erase +#endif +#ifdef ROM_FLASH_CTL_A_ERASE_SECTOR +#define MAP_FLASH_CTL_A_ERASE_SECTOR ROM_FLASH_CTL_A_ERASE_SECTOR +#else +#define MAP_FLASH_CTL_A_ERASE_SECTOR flash_ctl_a_erase_sector +#endif +#ifdef ROM_FLASH_CTL_A_PROGRAM_MEMORY +#define MAP_FLASH_CTL_A_PROGRAM_MEMORY ROM_FLASH_CTL_A_PROGRAM_MEMORY +#else +#define MAP_FLASH_CTL_A_PROGRAM_MEMORY flash_ctl_a_program_memory +#endif +#ifdef ROM_FLASH_CTL_A_SET_WAIT_STATE +#define MAP_FLASH_CTL_A_SET_WAIT_STATE ROM_FLASH_CTL_A_SET_WAIT_STATE +#else +#define MAP_FLASH_CTL_A_SET_WAIT_STATE flash_ctl_a_set_wait_state +#endif +#ifdef ROM_FLASH_CTL_A_GET_WAIT_STATE +#define MAP_FLASH_CTL_A_GET_WAIT_STATE ROM_FLASH_CTL_A_GET_WAIT_STATE +#else +#define MAP_FLASH_CTL_A_GET_WAIT_STATE flash_ctl_a_get_wait_state +#endif + +/* Real Time Clock Module prototypes */ +extern void rtc_c_hold_clock(void); + +/* Watchdog Timer Module prototypes */ +extern void wdt_a_hold_timer(void); + +#if defined(__MCU_HAS_FLCTL_A__) +#define FLASH_A_BANK0 0x00 +#define FLASH_A_BANK1 0x01 +#define __INFO_FLASH_A_TECH_START__ 0x00200000 +#define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000 +#endif + +#if defined(__MCU_HAS_FLCTL__) +#define FLASH_BANK0 0x00 +#define FLASH_BANK1 0x01 +#define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01 +#define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02 +#define FLASH_INFO_MEMORY_SPACE_BANK0 0x03 +#define FLASH_INFO_MEMORY_SPACE_BANK1 0x04 +#define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0 +#define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H */ diff --git a/contrib/loaders/flash/msp432/main_msp432e4x.c b/contrib/loaders/flash/msp432/main_msp432e4x.c new file mode 100644 index 0000000..23540ac --- /dev/null +++ b/contrib/loaders/flash/msp432/main_msp432e4x.c @@ -0,0 +1,351 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "driverlib.h" + +#include "MSP432E4_FlashLibIf.h" + +/* Local prototypes */ +void msp432_flash_init(void); +void msp432_flash_mass_erase(void); +void msp432_flash_sector_erase(void); +void msp432_flash_write(void); +void msp432_flash_continous_write(void); +void msp432_flash_exit(void); + +int main(void) +{ + /* Disable interrupts */ + __asm(" cpsid i"); + + /* Halt watchdog */ + SYSCTL->RCGCWD &= ~(SYSCTL_RCGCWD_R1 + SYSCTL_RCGCWD_R0); + + while (1) { + switch (FLASH_LOADER->FLASH_FUNCTION) { + case FLASH_INIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_init(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_MASS_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_mass_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_SECTOR_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_sector_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_PROGRAM: + case FLASH_CONTINUOUS_PROGRAM: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_continous_write(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_EXIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_exit(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_NO_COMMAND: + break; + default: + FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND; + break; + } + } +} + +/* Initialize flash */ +void msp432_flash_init(void) +{ + SCB->VTOR = 0x20000000; + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Erase entire flash */ +void msp432_flash_mass_erase(void) +{ + bool success = false; + + /* Clear the flash access and error interrupts. */ + FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_ERMISC | FLASH_FCMISC_PMISC); + + /* Trigger mass erase */ + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_MERASE; + while (FLASH_CTRL->FMC & FLASH_FMC_MERASE) + ; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_ERRIS)); + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Erase one flash sector */ +void msp432_flash_sector_erase(void) +{ + bool success = false; + + /* Clear the flash access and error interrupts. */ + FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_ERMISC | FLASH_FCMISC_PMISC); + + /* Set 16kB aligned flash page address to be erased (16kB block) */ + FLASH_CTRL->FMA = FLASH_LOADER->DST_ADDRESS; + /* Trigger sector erase (erase flash page) */ + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_ERASE; + while (FLASH_CTRL->FMC & FLASH_FMC_ERASE) + ; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS | + FLASH_FCRIS_ERRIS)); + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Write data to flash */ +void msp432_flash_continous_write(void) +{ + bool buffer1_in_use = false; + bool buffer2_in_use = false; + uint32_t *src_address = NULL; + bool success = true; + uint32_t i = 0; + uint32_t address = FLASH_LOADER->DST_ADDRESS; + uint32_t data_to_write = FLASH_LOADER->SRC_LENGTH; + int32_t write_package = 0; + + /* Clear the flash access and error interrupts. */ + FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC | + FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC | FLASH_FCMISC_PMISC); + do { + if (data_to_write > SRC_LENGTH_MAX) { + write_package = SRC_LENGTH_MAX; + data_to_write -= write_package; + } else { + write_package = data_to_write; + data_to_write -= write_package; + } + while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) && + !(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY)) + ; + + if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *) RAM_LOADER_BUFFER1; + buffer1_in_use = true; + } else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *) RAM_LOADER_BUFFER2; + buffer2_in_use = true; + } + + /* + * The flash hardware can only write complete words to flash. If + * an unaligned address is passed in, we must do a read-modify-write + * on a word with enough bytes to align the rest of the buffer. And + * if less than a whole word remains at the end, we must also do a + * read-modify-write on a final word to finish up. + */ + if (0 != (address & 0x3)) { + uint32_t head; + uint8_t *ui8head = (uint8_t *)&head; + uint8_t *buffer = (uint8_t *)src_address; + + /* Get starting offset for data to write (will be 1 to 3) */ + uint32_t head_offset = address & 0x03; + + /* Get the aligned address to write this first word to */ + uint32_t head_address = address & 0xfffffffc; + + /* Retrieve what is already in flash at the head address */ + head = *(uint32_t *)head_address; + + /* Substitute in the new data to write */ + while ((write_package > 0) && (head_offset < 4)) { + ui8head[head_offset] = *buffer; + head_offset++; + address++; + buffer++; + write_package--; + } + src_address = (uint32_t *)buffer; + + FLASH_CTRL->FMD = head; + FLASH_CTRL->FMA = head_address; + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + /* Wait until the word has been programmed. */ + while (FLASH_CTRL->FMC & FLASH_FMC_WRITE) + ; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | + FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)); + } + + /* Program a word at a time until aligned on 32-word boundary */ + while ((write_package >= 4) && ((address & 0x7f) != 0) && success) { + FLASH_CTRL->FMD = *src_address++; + FLASH_CTRL->FMA = address; + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + /* Wait until the word has been programmed. */ + while (FLASH_CTRL->FMC & FLASH_FMC_WRITE) + ; + + /* Prepare for next word to write */ + write_package -= 4; + address += 4; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | + FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)); + } + + /* Program data in 32-word blocks */ + while ((write_package >= 32) && success) { + /* Loop over the words in this 32-word block. */ + i = 0; + do { + FLASH_CTRL->FWBN[i] = *src_address++; + write_package -= 4; + i++; + } while ((write_package > 0) && (i < 32)); + FLASH_CTRL->FMA = address; + FLASH_CTRL->FMC2 = FLASH_FMC_WRKEY | FLASH_FMC2_WRBUF; + + /* Wait until the write buffer has been programmed. */ + while (FLASH_CTRL->FMC2 & FLASH_FMC2_WRBUF) + ; + + /* Increment destination address by words written */ + address += 128; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | + FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)); + } + + /* Program a word at a time on left over data */ + while ((write_package >= 4) && success) { + FLASH_CTRL->FMD = *src_address++; + FLASH_CTRL->FMA = address; + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + /* Wait until the word has been programmed. */ + while (FLASH_CTRL->FMC & FLASH_FMC_WRITE) + ; + + /* Prepare for next word to write */ + write_package -= 4; + address += 4; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | + FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)); + } + + if ((write_package > 0) && success) { + uint32_t tail; + uint8_t *ui8tail = (uint8_t *)&tail; + uint8_t *buffer = (uint8_t *)src_address; + + /* Set starting offset for data to write */ + uint32_t tail_offset = 0; + + /* Get the address to write this last word to */ + uint32_t tail_address = address; + + /* Retrieve what is already in flash at the tail address */ + tail = *(uint32_t *)address; + + /* Substitute in the new data to write */ + while (write_package > 0) { + ui8tail[tail_offset] = *buffer; + tail_offset++; + address++; + buffer++; + write_package--; + } + + FLASH_CTRL->FMD = tail; + FLASH_CTRL->FMA = tail_address; + FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE; + + /* Wait until the word has been programmed. */ + while (FLASH_CTRL->FMC & FLASH_FMC_WRITE) + ; + + /* Return an error if an access violation occurred. */ + success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | + FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS)); + } + + if (buffer1_in_use) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer1_in_use = false; + } else if (buffer2_in_use) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer2_in_use = false; + } + } while (success && data_to_write); + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Exit flash programming */ +void msp432_flash_exit(void) +{ + SCB->VTOR = 0x00000000; + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} diff --git a/contrib/loaders/flash/msp432/main_msp432p401x.c b/contrib/loaders/flash/msp432/main_msp432p401x.c new file mode 100644 index 0000000..7992f11 --- /dev/null +++ b/contrib/loaders/flash/msp432/main_msp432p401x.c @@ -0,0 +1,385 @@ +/****************************************************************************** +* +* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "driverlib.h" + +#include "MSP432P4_FlashLibIf.h" + +/* Number of erase repeats until timeout */ +#define FLASH_MAX_REPEATS 5 + +/* Local prototypes */ +void msp432_flash_init(void); +void msp432_flash_mass_erase(void); +void msp432_flash_sector_erase(void); +void msp432_flash_write(void); +void msp432_flash_continous_write(void); +void msp432_flash_exit(void); +void unlock_flash_sectors(void); +void unlock_all_flash_sectors(void); +void lock_all_flash_sectors(void); +void __cs_set_dco_frequency_range(uint32_t dco_freq); +static bool program_device(void *src, void *dest, uint32_t length); + +struct backup_params { + uint32_t BANK0_WAIT_RESTORE; + uint32_t BANK1_WAIT_RESTORE; + uint32_t CS_DC0_FREQ_RESTORE; + uint8_t VCORE_LEVEL_RESTORE; + uint8_t PCM_VCORE_LEVEL_RESTORE; +}; + +#define BACKUP_PARAMS ((struct backup_params *) 0x20000180) + +/* Main with trampoline */ +int main(void) +{ + /* Halt watchdog */ + MAP_WDT_A_HOLD_TIMER(); + + /* Disable interrupts */ + cpu_cpsid(); + + while (1) { + switch (FLASH_LOADER->FLASH_FUNCTION) { + case FLASH_INIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_init(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_MASS_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_mass_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_SECTOR_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_sector_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_PROGRAM: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_write(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_CONTINUOUS_PROGRAM: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_continous_write(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_EXIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_exit(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_NO_COMMAND: + break; + default: + FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND; + break; + } + } +} + +/* Initialize flash */ +void msp432_flash_init(void) +{ + bool success = false; + + /* Point to vector table in RAM */ + SCB->VTOR = (uint32_t)0x01000000; + + /* backup system parameters */ + BACKUP_PARAMS->BANK0_WAIT_RESTORE = + MAP_FLASH_CTL_GET_WAIT_STATE(FLASH_BANK0); + BACKUP_PARAMS->BANK1_WAIT_RESTORE = + MAP_FLASH_CTL_GET_WAIT_STATE(FLASH_BANK1); + BACKUP_PARAMS->VCORE_LEVEL_RESTORE = MAP_PCM_GET_CORE_VOLTAGE_LEVEL(); + BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE = MAP_PCM_GET_POWER_STATE(); + BACKUP_PARAMS->CS_DC0_FREQ_RESTORE = CS->CTL0 & CS_CTL0_DCORSEL_MASK; + + /* set parameters for flashing */ + success = MAP_PCM_SET_POWER_STATE(PCM_AM_LDO_VCORE0); + + /* Set Flash wait states to 2 */ + MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK0, 2); + MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK1, 2); + + /* Set CPU speed to 24MHz */ + __cs_set_dco_frequency_range(CS_DCO_FREQUENCY_24); + + if (!success) { + /* Indicate failed power switch */ + FLASH_LOADER->RETURN_CODE = FLASH_POWER_ERROR; + } else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Erase entire flash */ +void msp432_flash_mass_erase(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_flash_sectors(); + + /* Allow some mass erase repeats before timeout with error */ + int erase_repeats = FLASH_MAX_REPEATS; + while (!success && (erase_repeats > 0)) { + /* Mass erase with post-verify */ + success = MAP_FLASH_CTL_PERFORM_MASS_ERASE(); + erase_repeats--; + } + + if (erase_repeats == 0) + FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; + + /* Block flash writes */ + lock_all_flash_sectors(); +} + +/* Erase one flash sector */ +void msp432_flash_sector_erase(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_all_flash_sectors(); + + /* Allow some sector erase repeats before timeout with error */ + int erase_repeats = FLASH_MAX_REPEATS; + while (!success && (erase_repeats > 0)) { + /* Sector erase with post-verify */ + success = MAP_FLASH_CTL_ERASE_SECTOR(FLASH_LOADER->DST_ADDRESS); + erase_repeats--; + } + + if (erase_repeats == 0) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; + + /* Block flash writes */ + lock_all_flash_sectors(); +} + +/* Write data to flash with the help of DriverLib */ +void msp432_flash_write(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_all_flash_sectors(); + + while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY)) + ; + + FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE; + + /* Program memory */ + success = program_device((uint32_t *)RAM_LOADER_BUFFER1, + (void *)FLASH_LOADER->DST_ADDRESS, FLASH_LOADER->SRC_LENGTH); + + FLASH_LOADER->BUFFER1_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + + /* Block flash writes */ + lock_all_flash_sectors(); + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Write data to flash with the help of DriverLib with auto-increment */ +void msp432_flash_continous_write(void) +{ + bool buffer1_in_use = false; + bool buffer2_in_use = false; + uint32_t *src_address = NULL; + bool success = false; + + uint32_t bytes_to_write = FLASH_LOADER->SRC_LENGTH; + uint32_t write_package = 0; + uint32_t start_addr = FLASH_LOADER->DST_ADDRESS; + + while (bytes_to_write > 0) { + if (bytes_to_write > SRC_LENGTH_MAX) { + write_package = SRC_LENGTH_MAX; + bytes_to_write -= write_package; + } else { + write_package = bytes_to_write; + bytes_to_write -= write_package; + } + unlock_all_flash_sectors(); + + while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) && + !(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY)) + ; + + if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *)RAM_LOADER_BUFFER1; + buffer1_in_use = true; + } else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *)RAM_LOADER_BUFFER2; + buffer2_in_use = true; + } + if (buffer1_in_use || buffer2_in_use) { + success = program_device(src_address, + (void *)start_addr, write_package); + + if (buffer1_in_use) + P6->OUT &= ~BIT4; /* Program from B1 */ + else if (buffer2_in_use) + P3->OUT &= ~BIT6; /* Program from B1 */ + + start_addr += write_package; + } + if (buffer1_in_use) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer1_in_use = false; + } else if (buffer2_in_use) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer2_in_use = false; + } + /* Block flash writes */ + lock_all_flash_sectors(); + + if (!success) { + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + break; + } + } + if (success) + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Unlock Main/Info Flash sectors */ +void unlock_flash_sectors(void) +{ + if (FLASH_LOADER->ERASE_PARAM & ERASE_MAIN) { + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0, + 0xFFFFFFFF); + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1, + 0xFFFFFFFF); + } + if (FLASH_LOADER->ERASE_PARAM & ERASE_INFO) { + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0, + FLASH_SECTOR0 | FLASH_SECTOR1); + if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY) + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1, + FLASH_SECTOR0 | FLASH_SECTOR1); + } +} + +/* Unlock All Flash sectors */ +void unlock_all_flash_sectors(void) +{ + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0, 0xFFFFFFFF); + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1, 0xFFFFFFFF); + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0, + FLASH_SECTOR0 | FLASH_SECTOR1); + if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY) + MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1, + FLASH_SECTOR0 | FLASH_SECTOR1); +} + + +/* Lock all Flash sectors */ +void lock_all_flash_sectors(void) +{ + MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0, 0xFFFFFFFF); + MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1, 0xFFFFFFFF); + MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0, + FLASH_SECTOR0 | FLASH_SECTOR1); + MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1, + FLASH_SECTOR0 | FLASH_SECTOR1); +} + + +/* Force DCO frequency range */ +void __cs_set_dco_frequency_range(uint32_t dco_freq) +{ + /* Unlocking the CS Module */ + CS->KEY = CS_KEY_VAL; + + /* Resetting Tuning Parameters and Setting the frequency */ + CS->CTL0 = (CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dco_freq; + + /* Locking the CS Module */ + CS->KEY = 0; +} + +/* Exit flash programming */ +void msp432_flash_exit(void) +{ + bool success = false; + + /* Restore modified registers, in reverse order */ + __cs_set_dco_frequency_range(CS_DCO_FREQUENCY_3); + + MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK0, + BACKUP_PARAMS->BANK0_WAIT_RESTORE); + MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK1, + BACKUP_PARAMS->BANK1_WAIT_RESTORE); + + success = MAP_PCM_SET_POWER_STATE(BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE); + + success &= MAP_PCM_SET_CORE_VOLTAGE_LEVEL( + BACKUP_PARAMS->VCORE_LEVEL_RESTORE); + + __cs_set_dco_frequency_range(BACKUP_PARAMS->CS_DC0_FREQ_RESTORE); + + /* Point to vector table in Flash */ + SCB->VTOR = (uint32_t)0x00000000; + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +static bool program_device(void *src, void *dest, uint32_t length) +{ + return MAP_FLASH_CTL_PROGRAM_MEMORY(src, dest, length); +} diff --git a/contrib/loaders/flash/msp432/main_msp432p411x.c b/contrib/loaders/flash/msp432/main_msp432p411x.c new file mode 100644 index 0000000..be1f709 --- /dev/null +++ b/contrib/loaders/flash/msp432/main_msp432p411x.c @@ -0,0 +1,391 @@ +/****************************************************************************** +* +* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> +#include <stdbool.h> +#include "driverlib.h" + +#include "MSP432P4_FlashLibIf.h" + +/* Number of erase repeats until timeout */ +#define FLASH_MAX_REPEATS 5 + +/* Local prototypes */ +void msp432_flash_init(void); +void msp432_flash_mass_erase(void); +void msp432_flash_sector_erase(void); +void msp432_flash_write(void); +void msp432_flash_continous_write(void); +void msp432_flash_exit(void); +void unlock_flash_sectors(void); +void unlock_all_flash_sectors(void); +void lock_all_flash_sectors(void); +void __cs_set_dco_frequency_range(uint32_t dco_freq); +static bool program_device(void *src, void *dest, uint32_t length); + +struct backup_params { + uint32_t BANK0_WAIT_RESTORE; + uint32_t BANK1_WAIT_RESTORE; + uint32_t CS_DC0_FREQ_RESTORE; + uint8_t VCORE_LEVEL_RESTORE; + uint8_t PCM_VCORE_LEVEL_RESTORE; +}; + +#define BACKUP_PARAMS ((struct backup_params *) 0x20000180) +#define INFO_FLASH_START __INFO_FLASH_A_TECH_START__ +#define INFO_FLASH_MIDDLE __INFO_FLASH_A_TECH_MIDDLE__ +#define BSL_FLASH_START BSL_API_TABLE_ADDR + +/* Main with trampoline */ +int main(void) +{ + /* Halt watchdog */ + MAP_WDT_A_HOLD_TIMER(); + + /* Disable interrupts */ + cpu_cpsid(); + + while (1) { + switch (FLASH_LOADER->FLASH_FUNCTION) { + case FLASH_INIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_init(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_MASS_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_mass_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_SECTOR_ERASE: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_sector_erase(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_PROGRAM: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_write(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_CONTINUOUS_PROGRAM: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_continous_write(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_EXIT: + FLASH_LOADER->RETURN_CODE = FLASH_BUSY; + msp432_flash_exit(); + FLASH_LOADER->FLASH_FUNCTION = 0; + break; + case FLASH_NO_COMMAND: + break; + default: + FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND; + break; + } + } +} + +/* Initialize flash */ +void msp432_flash_init(void) +{ + bool success = false; + + /* Point to vector table in RAM */ + SCB->VTOR = (uint32_t)0x01000000; + + /* backup system parameters */ + BACKUP_PARAMS->BANK0_WAIT_RESTORE = + MAP_FLASH_CTL_A_GET_WAIT_STATE(FLASH_A_BANK0); + BACKUP_PARAMS->BANK1_WAIT_RESTORE = + MAP_FLASH_CTL_A_GET_WAIT_STATE(FLASH_A_BANK1); + BACKUP_PARAMS->VCORE_LEVEL_RESTORE = MAP_PCM_GET_CORE_VOLTAGE_LEVEL(); + BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE = MAP_PCM_GET_POWER_STATE(); + BACKUP_PARAMS->CS_DC0_FREQ_RESTORE = CS->CTL0 & CS_CTL0_DCORSEL_MASK; + + /* set parameters for flashing */ + success = MAP_PCM_SET_POWER_STATE(PCM_AM_LDO_VCORE0); + + /* Set Flash wait states to 2 */ + MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK0, 2); + MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK1, 2); + + /* Set CPU speed to 24MHz */ + __cs_set_dco_frequency_range(CS_DCO_FREQUENCY_24); + + if (!success) { + /* Indicate failed power switch */ + FLASH_LOADER->RETURN_CODE = FLASH_POWER_ERROR; + } else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Erase entire flash */ +void msp432_flash_mass_erase(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_flash_sectors(); + + /* Allow some mass erase repeats before timeout with error */ + int erase_repeats = FLASH_MAX_REPEATS; + while (!success && (erase_repeats > 0)) { + /* Mass erase with post-verify */ + success = ROM_FLASH_CTL_A_PERFORM_MASS_ERASE(); + erase_repeats--; + } + + if (erase_repeats == 0) + FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; + + /* Block flash writes */ + lock_all_flash_sectors(); +} + +/* Erase one flash sector */ +void msp432_flash_sector_erase(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_all_flash_sectors(); + + /* Allow some sector erase repeats before timeout with error */ + int erase_repeats = FLASH_MAX_REPEATS; + while (!success && (erase_repeats > 0)) { + /* Sector erase with post-verify */ + success = MAP_FLASH_CTL_A_ERASE_SECTOR(FLASH_LOADER->DST_ADDRESS); + erase_repeats--; + } + + if (erase_repeats == 0) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; + + /* Block flash writes */ + lock_all_flash_sectors(); +} + +/* Write data to flash with the help of DriverLib */ +void msp432_flash_write(void) +{ + bool success = false; + + /* Allow flash writes */ + unlock_all_flash_sectors(); + + while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY)) + ; + + FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE; + + /* Program memory */ + success = program_device((uint32_t *)RAM_LOADER_BUFFER1, + (void *)FLASH_LOADER->DST_ADDRESS, FLASH_LOADER->SRC_LENGTH); + + FLASH_LOADER->BUFFER1_STATUS_REGISTER &= + ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + + /* Block flash writes */ + lock_all_flash_sectors(); + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Write data to flash with the help of DriverLib with auto-increment */ +void msp432_flash_continous_write(void) +{ + bool buffer1_in_use = false; + bool buffer2_in_use = false; + uint32_t *src_address = NULL; + bool success = false; + + uint32_t bytes_to_write = FLASH_LOADER->SRC_LENGTH; + uint32_t write_package = 0; + uint32_t start_addr = FLASH_LOADER->DST_ADDRESS; + + while (bytes_to_write > 0) { + if (bytes_to_write > SRC_LENGTH_MAX) { + write_package = SRC_LENGTH_MAX; + bytes_to_write -= write_package; + } else { + write_package = bytes_to_write; + bytes_to_write -= write_package; + } + unlock_all_flash_sectors(); + while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) && + !(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY)) + ; + + if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *) RAM_LOADER_BUFFER1; + buffer1_in_use = true; + } else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE; + src_address = (uint32_t *) RAM_LOADER_BUFFER2; + buffer2_in_use = true; + } + if (buffer1_in_use || buffer2_in_use) { + success = program_device(src_address, (void *) start_addr, write_package); + start_addr += write_package; + } + if (buffer1_in_use) { + FLASH_LOADER->BUFFER1_STATUS_REGISTER &= ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer1_in_use = false; + } else if (buffer2_in_use) { + FLASH_LOADER->BUFFER2_STATUS_REGISTER &= ~(BUFFER_ACTIVE | BUFFER_DATA_READY); + buffer2_in_use = false; + } + /* Block flash writes */ + lock_all_flash_sectors(); + + if (!success) { + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + break; + } + } + if (success) + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +/* Unlock Main/Info Flash sectors */ +void unlock_flash_sectors(void) +{ + if (FLASH_LOADER->ERASE_PARAM & ERASE_MAIN) + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(FLASH_BASE, FLASH_BASE + + MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1); + + if (FLASH_LOADER->ERASE_PARAM & ERASE_INFO) { + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_START, TLV_BASE - 1); + if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY) + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(BSL_FLASH_START, + INFO_FLASH_MIDDLE - 1); + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_MIDDLE, INFO_FLASH_MIDDLE + + MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1); + } +} + +/* Unlock All Flash sectors */ +void unlock_all_flash_sectors(void) +{ + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(FLASH_BASE, FLASH_BASE + + MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1); + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_START, TLV_BASE - 1); + if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY) + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(BSL_FLASH_START, + INFO_FLASH_MIDDLE - 1); + MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_MIDDLE, INFO_FLASH_MIDDLE + + MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1); +} + +/* Lock all Flash sectors */ +void lock_all_flash_sectors(void) +{ + MAP_FLASH_CTL_A_PROTECT_MEMORY(FLASH_BASE, FLASH_BASE + + MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1); + MAP_FLASH_CTL_A_PROTECT_MEMORY(INFO_FLASH_START, INFO_FLASH_START + + MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1); +} + +/* Force DCO frequency range */ +void __cs_set_dco_frequency_range(uint32_t dco_freq) +{ + /* Unlocking the CS Module */ + CS->KEY = CS_KEY_VAL; + + /* Resetting Tuning Parameters and Setting the frequency */ + CS->CTL0 = (CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dco_freq; + + /* Locking the CS Module */ + CS->KEY = 0; +} + +/* Exit flash programming */ +void msp432_flash_exit(void) +{ + bool success = false; + + /* Restore modified registers, in reverse order */ + __cs_set_dco_frequency_range(CS_DCO_FREQUENCY_3); + + MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK0, + BACKUP_PARAMS->BANK0_WAIT_RESTORE); + MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK1, + BACKUP_PARAMS->BANK1_WAIT_RESTORE); + + success = MAP_PCM_SET_POWER_STATE(BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE); + + success &= MAP_PCM_SET_CORE_VOLTAGE_LEVEL( + BACKUP_PARAMS->VCORE_LEVEL_RESTORE); + + __cs_set_dco_frequency_range(BACKUP_PARAMS->CS_DC0_FREQ_RESTORE); + + /* Point to vector table in Flash */ + SCB->VTOR = (uint32_t)0x00000000; + + if (!success) + FLASH_LOADER->RETURN_CODE = FLASH_ERROR; + else + FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS; +} + +static bool program_device(void *src, void *dest, uint32_t length) +{ + uint32_t dst_address = (uint32_t)dest; + + /* Flash main memory first, then information memory */ + if ((dst_address < INFO_FLASH_START) && ((dst_address + length) > + INFO_FLASH_START)) { + uint32_t block_length = INFO_FLASH_START - dst_address; + uint32_t src_address = (uint32_t)src; + /* Main memory block */ + bool success = MAP_FLASH_CTL_A_PROGRAM_MEMORY(src, dest, block_length); + + src_address = src_address + block_length; + block_length = length - block_length; + /* Information memory block */ + success &= MAP_FLASH_CTL_A_PROGRAM_MEMORY((void *)src_address, + (void *)INFO_FLASH_START, block_length); + return success; + } else + return MAP_FLASH_CTL_A_PROGRAM_MEMORY(src, dest, length); +} diff --git a/contrib/loaders/flash/msp432/msp432e4x.h b/contrib/loaders/flash/msp432/msp432e4x.h new file mode 100644 index 0000000..2a9d155 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432e4x.h @@ -0,0 +1,229 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H +#define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Register map for FLASH_CTRL peripheral (FLASH_CTRL) */ +struct flash_ctrl { + volatile uint32_t FMA; /* Flash Memory Address */ + volatile uint32_t FMD; /* Flash Memory Data */ + volatile uint32_t FMC; /* Flash Memory Control */ + volatile uint32_t FCRIS; /* Flash Controller Raw Interrupt Status */ + volatile uint32_t FCIM; /* Flash Controller Interrupt Mask */ + volatile uint32_t FCMISC; /* Flash Cont. Masked Int. Status and Clear */ + volatile uint32_t RESERVED0[2]; + volatile uint32_t FMC2; /* Flash Memory Control 2 */ + volatile uint32_t RESERVED1[3]; + volatile uint32_t FWBVAL; /* Flash Write Buffer Valid */ + volatile uint32_t RESERVED2[2]; + volatile uint32_t FLPEKEY; /* Flash Program/Erase Key */ + volatile uint32_t RESERVED3[48]; + volatile uint32_t FWBN[32]; /* Flash Write Buffer n */ +}; + +/* Register map for SYSCTL peripheral (SYSCTL) */ +struct sys_ctrl { + volatile uint32_t DID0; /* Device Identification 0 */ + volatile uint32_t DID1; /* Device Identification 1 */ + volatile uint32_t RESERVED0[12]; + volatile uint32_t PTBOCTL; /* Power-Temp Brown Out Control */ + volatile uint32_t RESERVED1[5]; + volatile uint32_t RIS; /* Raw Interrupt Status */ + volatile uint32_t IMC; /* Interrupt Mask Control */ + volatile uint32_t MISC; /* Masked Interrupt Status and Clear */ + volatile uint32_t RESC; /* Reset Cause */ + volatile uint32_t PWRTC; /* Power-Temperature Cause */ + volatile uint32_t NMIC; /* NMI Cause Register */ + volatile uint32_t RESERVED2[5]; + volatile uint32_t MOSCCTL; /* Main Oscillator Control */ + volatile uint32_t RESERVED3[12]; + volatile uint32_t RSCLKCFG; /* Run and Sleep Mode Configuration Register */ + volatile uint32_t RESERVED4[3]; + volatile uint32_t MEMTIM0; /* Memory Timing Register 0 for Main Flash */ + volatile uint32_t RESERVED5[29]; + volatile uint32_t ALTCLKCFG; /* Alternate Clock Configuration */ + volatile uint32_t RESERVED6[2]; + union { + volatile uint32_t DSLPCLKCFG; /* Deep Sleep Clock Configuration */ + volatile uint32_t DSCLKCFG; /* Deep Sleep Clock Register */ + }; + volatile uint32_t DIVSCLK; /* Divisor and Source Clock Configuration */ + volatile uint32_t SYSPROP; /* System Properties */ + volatile uint32_t PIOSCCAL; /* Precision Internal Oscillator Calibration */ + volatile uint32_t PIOSCSTAT; /* Precision Internal Oscillator Statistics */ + volatile uint32_t RESERVED7[2]; + volatile uint32_t PLLFREQ0; /* PLL Frequency 0 */ + volatile uint32_t PLLFREQ1; /* PLL Frequency 1 */ + volatile uint32_t PLLSTAT; /* PLL Status */ + volatile uint32_t RESERVED8[7]; + volatile uint32_t SLPPWRCFG; /* Sleep Power Configuration */ + volatile uint32_t DSLPPWRCFG; /* Deep-Sleep Power Configuration */ + volatile uint32_t RESERVED9[4]; + volatile uint32_t NVMSTAT; /* Non-Volatile Memory Information */ + volatile uint32_t RESERVED10[4]; + volatile uint32_t LDOSPCTL; /* LDO Sleep Power Control */ + volatile uint32_t RESERVED11; + volatile uint32_t LDODPCTL; /* LDO Deep-Sleep Power Control */ + volatile uint32_t RESERVED12[6]; + volatile uint32_t RESBEHAVCTL; /* Reset Behavior Control Register */ + volatile uint32_t RESERVED13[6]; + volatile uint32_t HSSR; /* Hardware System Service Request */ + volatile uint32_t RESERVED14[34]; + volatile uint32_t USBPDS; /* USB Power Domain Status */ + volatile uint32_t USBMPC; /* USB Memory Power Control */ + volatile uint32_t EMACPDS; /* Ethernet MAC Power Domain Status */ + volatile uint32_t EMACMPC; /* Ethernet MAC Memory Power Control */ + volatile uint32_t RESERVED15; + volatile uint32_t LCDMPC; /* LCD Memory Power Control */ + volatile uint32_t RESERVED16[26]; + volatile uint32_t PPWD; /* Watchdog Timer Peripheral Present */ + volatile uint32_t PPTIMER; /* General-Purpose Timer Peripheral Present */ + volatile uint32_t PPGPIO; /* General-Purpose I/O Peripheral Present */ + volatile uint32_t PPDMA; /* Micro DMA Peripheral Present */ + volatile uint32_t PPEPI; /* EPI Peripheral Present */ + volatile uint32_t PPHIB; /* Hibernation Peripheral Present */ + volatile uint32_t PPUART; /* UART Peripheral Present */ + volatile uint32_t PPSSI; /* Synchronous Serial Inter. Periph. Present */ + volatile uint32_t PPI2C; /* Inter-Integrated Circuit Periph. Present */ + volatile uint32_t RESERVED17; + volatile uint32_t PPUSB; /* Universal Serial Bus Peripheral Present */ + volatile uint32_t RESERVED18; + volatile uint32_t PPEPHY; /* Ethernet PHY Peripheral Present */ + volatile uint32_t PPCAN; /* Controller Area Network Periph. Present */ + volatile uint32_t PPADC; /* Analog-to-Dig. Converter Periph. Present */ + volatile uint32_t PPACMP; /* Analog Comparator Peripheral Present */ + volatile uint32_t PPPWM; /* Pulse Width Modulator Peripheral Present */ + volatile uint32_t PPQEI; /* Quadrature Encoder Inter. Periph. Present */ + volatile uint32_t RESERVED19[4]; + volatile uint32_t PPEEPROM; /* EEPROM Peripheral Present */ + volatile uint32_t RESERVED20[6]; + volatile uint32_t PPCCM; /* CRC/Cryptographic Modules Periph. Present */ + volatile uint32_t RESERVED21[6]; + volatile uint32_t PPLCD; /* LCD Peripheral Present */ + volatile uint32_t RESERVED22; + volatile uint32_t PPOWIRE; /* 1-Wire Peripheral Present */ + volatile uint32_t PPEMAC; /* Ethernet MAC Peripheral Present */ + volatile uint32_t RESERVED23[88]; + volatile uint32_t SRWD; /* Watchdog Timer Software Reset */ + volatile uint32_t SRTIMER; /* General-Purpose Timer Software Reset */ + volatile uint32_t SRGPIO; /* General-Purpose I/O Software Reset */ + volatile uint32_t SRDMA; /* Micro Direct Memory Access Software Reset */ + volatile uint32_t SREPI; /* EPI Software Reset */ + volatile uint32_t SRHIB; /* Hibernation Software Reset */ + volatile uint32_t SRUART; /* UART Software Reset */ + volatile uint32_t SRSSI; /* Synchronous Serial Inter. Software Reset */ + volatile uint32_t SRI2C; /* Inter-Integrated Circuit Software Reset */ + volatile uint32_t RESERVED24; + volatile uint32_t SRUSB; /* Universal Serial Bus Software Reset */ + volatile uint32_t RESERVED25; + volatile uint32_t SREPHY; /* Ethernet PHY Software Reset */ + volatile uint32_t SRCAN; /* Controller Area Network Software Reset */ + volatile uint32_t SRADC; /* Analog-to-Dig. Converter Software Reset */ + volatile uint32_t SRACMP; /* Analog Comparator Software Reset */ + volatile uint32_t SRPWM; /* Pulse Width Modulator Software Reset */ + volatile uint32_t SRQEI; /* Quadrature Encoder Inter. Software Reset */ + volatile uint32_t RESERVED26[4]; + volatile uint32_t SREEPROM; /* EEPROM Software Reset */ + volatile uint32_t RESERVED27[6]; + volatile uint32_t SRCCM; /* CRC/Cryptographic Modules Software Reset */ + volatile uint32_t RESERVED28[6]; + volatile uint32_t SRLCD; /* LCD Controller Software Reset */ + volatile uint32_t RESERVED29; + volatile uint32_t SROWIRE; /* 1-Wire Software Reset */ + volatile uint32_t SREMAC; /* Ethernet MAC Software Reset */ + volatile uint32_t RESERVED30[24]; + volatile uint32_t RCGCWD; /* Watchdog Run Mode Clock Gating Control */ +}; + +/* Peripheral Memory Map */ +#define FLASH_CTRL_BASE 0x400FD000UL +#define SYSCTL_BASE 0x400FE000UL + +/* Peripheral Declarations */ +#define FLASH_CTRL ((struct flash_ctrl *) FLASH_CTRL_BASE) +#define SYSCTL ((struct sys_ctrl *) SYSCTL_BASE) + +/* The following are defines for the bit fields in the FLASH_FMC register. */ +#define FLASH_FMC_WRKEY 0xA4420000 /* FLASH write key */ +#define FLASH_FMC_COMT 0x00000008 /* Commit Register Value */ +#define FLASH_FMC_MERASE 0x00000004 /* Mass Erase Flash Memory */ +#define FLASH_FMC_ERASE 0x00000002 /* Erase a Page of Flash Memory */ +#define FLASH_FMC_WRITE 0x00000001 /* Write a Word into Flash Memory */ + +/* The following are defines for the bit fields in the FLASH_FCRIS register. */ +#define FLASH_FCRIS_PROGRIS 0x00002000 /* Program Verify Raw Interrupt Status */ +#define FLASH_FCRIS_ERRIS 0x00000800 /* Erase Verify Raw Interrupt Status */ +#define FLASH_FCRIS_INVDRIS 0x00000400 /* Invalid Data Raw Interrupt Status */ +#define FLASH_FCRIS_VOLTRIS 0x00000200 /* Pump Voltage Raw Interrupt Status */ +#define FLASH_FCRIS_ERIS 0x00000004 /* EEPROM Raw Interrupt Status */ +#define FLASH_FCRIS_PRIS 0x00000002 /* Programming Raw Interrupt Status */ +#define FLASH_FCRIS_ARIS 0x00000001 /* Access Raw Interrupt Status */ + +/* The following are defines for the bit fields in the FLASH_FCIM register. */ +#define FLASH_FCIM_PROGMASK 0x00002000 /* PROGVER Interrupt Mask */ +#define FLASH_FCIM_ERMASK 0x00000800 /* ERVER Interrupt Mask */ +#define FLASH_FCIM_INVDMASK 0x00000400 /* Invalid Data Interrupt Mask */ +#define FLASH_FCIM_VOLTMASK 0x00000200 /* VOLT Interrupt Mask */ +#define FLASH_FCIM_EMASK 0x00000004 /* EEPROM Interrupt Mask */ +#define FLASH_FCIM_PMASK 0x00000002 /* Programming Interrupt Mask */ +#define FLASH_FCIM_AMASK 0x00000001 /* Access Interrupt Mask */ + +/* The following are defines for the bit fields in the FLASH_FCMISC register. */ +#define FLASH_FCMISC_PROGMISC 0x00002000 /* PROGVER Interrupt Status/Clear */ +#define FLASH_FCMISC_ERMISC 0x00000800 /* ERVER Interrupt Status/Clear */ +#define FLASH_FCMISC_INVDMISC 0x00000400 /* Invalid Data Int. Status/Clear */ +#define FLASH_FCMISC_VOLTMISC 0x00000200 /* VOLT Interrupt Status/Clear */ +#define FLASH_FCMISC_EMISC 0x00000004 /* EEPROM Interrupt Status/Clear */ +#define FLASH_FCMISC_PMISC 0x00000002 /* Programming Int. Status/Clear */ +#define FLASH_FCMISC_AMISC 0x00000001 /* Access Interrupt Status/Clear */ + +/* The following are defines for the bit fields in the FLASH_FMC2 register. */ +#define FLASH_FMC2_WRBUF 0x00000001 /* Buffered Flash Memory Write */ + +/* The following are defines for the bit fields in the SYSCTL_RCGCWD reg. */ +#define SYSCTL_RCGCWD_R1 0x00000002 /* Watchdog 1 Run Mode Clock Gating Cont. */ +#define SYSCTL_RCGCWD_R0 0x00000001 /* Watchdog 0 Run Mode Clock Gating Cont. */ + +#ifdef __cplusplus +} +#endif + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H */ diff --git a/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds new file mode 100644 index 0000000..af97458 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds @@ -0,0 +1,149 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +MEMORY { + MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + SRAM_CODE_0(RWX): ORIGIN = 0x20000000, LENGTH = 0x00000110 + SRAM_CODE_1(RWX): ORIGIN = 0x20000110, LENGTH = 0x00000030 + SRAM_CODE_2(RWX): ORIGIN = 0x20000150, LENGTH = 0x00000040 + SRAM_CODE_3(RWX): ORIGIN = 0x20000190, LENGTH = 0x00000F70 + SRAM_CODE_4(RWX): ORIGIN = 0x20001170, LENGTH = 0x00000200 + SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 +} + +REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0); +REGION_ALIAS("REGION_RESET", SRAM_CODE_1); +REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2); +REGION_ALIAS("REGION_TEXT", SRAM_CODE_3); +REGION_ALIAS("REGION_BSS", SRAM_CODE_3); +REGION_ALIAS("REGION_DATA", SRAM_DATA); +REGION_ALIAS("REGION_STACK", SRAM_CODE_4); +REGION_ALIAS("REGION_HEAP", SRAM_DATA); +REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3); +REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3); + +SECTIONS { + /* section for the interrupt vector area */ + .intvecs : { + KEEP (*(.intvecs)) + } > REGION_INTVECT + + PROVIDE (_vtable_base_address = + DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000); + + .vtable (_vtable_base_address) : AT (_vtable_base_address) { + KEEP (*(.vtable)) + } > REGION_DATA + + .descriptor :{ + FILL(0x00000000); + . = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1; + BYTE(0x00); + __ROM_AT = .; + } > REGION_DESCRIPTOR + + .reset : { + KEEP(*(.reset)) + } > REGION_RESET AT> REGION_RESET + + .text : { + CREATE_OBJECT_SYMBOLS + KEEP (*(.text)) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + KEEP (*(.init)) + KEEP (*(.fini*)) + } > REGION_TEXT AT> REGION_TEXT + + .rodata : { + *(.rodata) + *(.rodata.*) + } > REGION_TEXT AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*)) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + __etext = .; + + .data : { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + KEEP (*(.data)) + KEEP (*(.data*)) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .bss : { + __bss_start__ = .; + *(.shbss) + KEEP (*(.bss)) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP (*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + KEEP(*(.stack)) + } > REGION_STACK AT> REGION_STACK + + __stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK); + PROVIDE(__stack = __stack_top); +} diff --git a/contrib/loaders/flash/msp432/msp432e4x_algo.inc b/contrib/loaders/flash/msp432/msp432e4x_algo.inc new file mode 100644 index 0000000..1f36a21 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432e4x_algo.inc @@ -0,0 +1,245 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x70,0x13,0x00,0x20,0x11,0x01,0x00,0x20,0xc9,0x0a,0x00,0x20,0xc9,0x0a,0x00,0x20, +0xc9,0x0a,0x00,0x20,0xc9,0x0a,0x00,0x20,0xc9,0x0a,0x00,0x20,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x08,0x20,0x00,0x20, diff --git a/contrib/loaders/flash/msp432/msp432p401x.h b/contrib/loaders/flash/msp432/msp432p401x.h new file mode 100644 index 0000000..ca219fd --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p401x.h @@ -0,0 +1,102 @@ +/****************************************************************************** +* +* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H +#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define __MCU_HAS_FLCTL__ /* Module FLCTL is available */ + +/* Device and peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory start address */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM memory start address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals start address */ +#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of module CS regs. */ +#define DIO_BASE (PERIPH_BASE + 0x00004C00) /* Address of module DIO regs. */ + +/* Register map for Clock Signal peripheral (CS) */ +struct cs { + volatile uint32_t KEY; /* Key Register */ + volatile uint32_t CTL0; /* Control 0 Register */ + volatile uint32_t CTL1; /* Control 1 Register */ + volatile uint32_t CTL2; /* Control 2 Register */ + volatile uint32_t CTL3; /* Control 3 Register */ +}; + +/* Register map for DIO port (odd interrupt) */ +struct dio_port_odd_int { + volatile uint8_t IN; /* Port Input */ + uint8_t RESERVED0; + volatile uint8_t OUT; /* Port Output */ +}; + +/* Register map for DIO port (even interrupt) */ +struct dio_port_even_int { + uint8_t RESERVED0; + volatile uint8_t IN; /* Port Input */ + uint8_t RESERVED1; + volatile uint8_t OUT; /* Port Output */ +}; + +/* Peripheral declarations */ +#define CS ((struct cs *) CS_BASE) +#define P3 ((struct dio_port_odd_int *) (DIO_BASE + 0x0020)) +#define P6 ((struct dio_port_even_int *) (DIO_BASE + 0x0040)) + +/* Peripheral bit definitions */ + +/* DCORSEL Bit Mask */ +#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) +/* Nominal DCO Frequency Range (MHz): 2 to 4 */ +#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) +/* Nominal DCO Frequency Range (MHz): 16 to 32 */ +#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) +/* CS control key value */ +#define CS_KEY_VAL ((uint32_t)0x0000695A) + +/* Protects Sector 0 from program or erase */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) +/* Protects Sector 1 from program or erase */ +#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) + +#ifdef __cplusplus +} +#endif + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H */ diff --git a/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds new file mode 100644 index 0000000..f9d04ed --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds @@ -0,0 +1,151 @@ +/****************************************************************************** +* +* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +MEMORY { + MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + INFO_FLASH (RX) : ORIGIN = 0x00200000, LENGTH = 0x00004000 + SRAM_CODE_0(RWX): ORIGIN = 0x01000000, LENGTH = 0x00000110 + SRAM_CODE_1(RWX): ORIGIN = 0x01000110, LENGTH = 0x00000030 + SRAM_CODE_2(RWX): ORIGIN = 0x01000150, LENGTH = 0x00000040 + SRAM_CODE_3(RWX): ORIGIN = 0x01000190, LENGTH = 0x00000F70 + SRAM_CODE_4(RWX): ORIGIN = 0x01001170, LENGTH = 0x00000200 + SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 +} + +REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0); +REGION_ALIAS("REGION_RESET", SRAM_CODE_1); +REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2); +REGION_ALIAS("REGION_TEXT", SRAM_CODE_3); +REGION_ALIAS("REGION_BSS", SRAM_CODE_3); +REGION_ALIAS("REGION_DATA", SRAM_DATA); +REGION_ALIAS("REGION_STACK", SRAM_CODE_4); +REGION_ALIAS("REGION_HEAP", SRAM_DATA); +REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3); +REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3); + + +SECTIONS { + /* section for the interrupt vector area */ + .intvecs : { + KEEP (*(.intvecs)) + } > REGION_INTVECT + + PROVIDE (_vtable_base_address = + DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000); + + .vtable (_vtable_base_address) : AT (_vtable_base_address) { + KEEP (*(.vtable)) + } > REGION_DATA + + .descriptor :{ + FILL(0x00000000); + . = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1; + BYTE(0x00); + __ROM_AT = .; + } > REGION_DESCRIPTOR + + .reset : { + KEEP(*(.reset)) + } > REGION_RESET AT> REGION_RESET + + .text : { + CREATE_OBJECT_SYMBOLS + KEEP (*(.text)) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + KEEP (*(.init)) + KEEP (*(.fini*)) + } > REGION_TEXT AT> REGION_TEXT + + .rodata : { + *(.rodata) + *(.rodata.*) + } > REGION_TEXT AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*)) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + __etext = .; + + .data : { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + KEEP (*(.data)) + KEEP (*(.data*)) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .bss : { + __bss_start__ = .; + *(.shbss) + KEEP (*(.bss)) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP (*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + KEEP(*(.stack)) + } > REGION_STACK AT> REGION_STACK + + __stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK); + PROVIDE(__stack = __stack_top); +} diff --git a/contrib/loaders/flash/msp432/msp432p401x_algo.inc b/contrib/loaders/flash/msp432/msp432p401x_algo.inc new file mode 100644 index 0000000..c302342 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p401x_algo.inc @@ -0,0 +1,242 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x70,0x13,0x00,0x01,0x11,0x01,0x00,0x01,0xa1,0x0a,0x00,0x01,0xa1,0x0a,0x00,0x01, +0xa1,0x0a,0x00,0x01,0xa1,0x0a,0x00,0x01,0xa1,0x0a,0x00,0x01,0x00,0x00,0x00,0x00, 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100644 index 0000000..6482dd3 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p411x.h @@ -0,0 +1,164 @@ +/****************************************************************************** +* +* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H +#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Available Peripherals */ +#define __MCU_HAS_FLCTL_A__ /* Module FLCTL_A is available */ +#define __MCU_HAS_SYSCTL_A__ /* Module SYSCTL_A is available */ + +/* Device and Peripheral Memory Map */ +#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals address */ +#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of CS regs. */ +#define PCM_BASE (PERIPH_BASE + 0x00010000) /* Address of PCM regs. */ +#define RTC_C_BASE (PERIPH_BASE + 0x00004400) /* Address of RTC_C regs */ +#define TLV_BASE ((uint32_t)0x00201000) /* Address of TLV regs. */ +#define WDT_A_BASE (PERIPH_BASE + 0x00004800) /* Address of WDT_A regs */ +#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) + +/* + * Peripherals with 8-bit or 16-bit register access allow only 8-bit or + * 16-bit bit band access, so cast to 8 bit always + */ +#define BITBAND_PERI(x, b) (*((volatile uint8_t *) (BITBAND_PERI_BASE + \ + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) + +/* Register map for CLock Signal peripheral (CS) */ +struct cs { + volatile uint32_t KEY; /* Key Register */ + volatile uint32_t CTL0; /* Control 0 Register */ + volatile uint32_t CTL1; /* Control 1 Register */ + volatile uint32_t CTL2; /* Control 2 Register */ + volatile uint32_t CTL3; /* Control 3 Register */ +}; + +/* Register map for Power Control Module peripheral (PCM) */ +struct pcm { + volatile uint32_t CTL0; /* Control 0 Register */ + volatile uint32_t CTL1; /* Control 1 Register */ + volatile uint32_t IE; /* Interrupt Enable Register */ + volatile uint32_t IFG; /* Interrupt Flag Register */ + volatile uint32_t CLRIFG; /* Clear Interrupt Flag Register */ +}; + +/* Register map for Real-Time Clock peripheral (RTC_C) */ +struct rtc_c { + volatile uint16_t CTL0; /* RTCCTL0 Register */ + volatile uint16_t CTL13; /* RTCCTL13 Register */ + volatile uint16_t OCAL; /* RTCOCAL Register */ + volatile uint16_t TCMP; /* RTCTCMP Register */ + volatile uint16_t PS0CTL; /* RTC Prescale Timer 0 Control Register */ + volatile uint16_t PS1CTL; /* RTC Prescale Timer 1 Control Register */ + volatile uint16_t PS; /* Real-Time Clock Prescale Timer Register */ + volatile uint16_t IV; /* Real-Time Clock Interrupt Vector Register */ + volatile uint16_t TIM0; /* RTCTIM0 Register Hexadecimal Format */ + volatile uint16_t TIM1; /* Real-Time Clock Hour, Day of Week */ + volatile uint16_t DATE; /* RTCDATE - Hexadecimal Format */ + volatile uint16_t YEAR; /* RTCYEAR Register - Hexadecimal Format */ + volatile uint16_t AMINHR; /* RTCMINHR - Hexadecimal Format */ + volatile uint16_t ADOWDAY; /* RTCADOWDAY - Hexadecimal Format */ + volatile uint16_t BIN2BCD; /* Binary-to-BCD Conversion Register */ + volatile uint16_t BCD2BIN; /* BCD-to-Binary Conversion Register */ +}; + +/* Register map for Watchdog Timer peripheral (WDT_A) */ +struct wdt_a { + uint16_t RESERVED0[6]; + volatile uint16_t CTL; /* Watchdog Timer Control Register */ +}; + +/* Peripheral Declarations */ +#define CS ((struct cs *) CS_BASE) +#define PCM ((struct pcm *) PCM_BASE) +#define RTC_C ((struct rtc_c *) RTC_C_BASE) +#define WDT_A ((struct wdt_a *) WDT_A_BASE) + +/* Peripheral Register Bit Definitions */ + +/* DCORSEL Bit Mask */ +#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) +/* Nominal DCO Frequency Range (MHz): 2 to 4 */ +#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) +/* Nominal DCO Frequency Range (MHz): 16 to 32 */ +#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) +/* CS control key value */ +#define CS_KEY_VAL ((uint32_t)0x0000695A) + +/* AMR Bit Mask */ +#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) +/* LPMR Bit Mask */ +#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) +/* LPM3.5. Core voltage setting 0. */ +#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) +/* LPM4.5 */ +#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) +/* CPM Bit Offset */ +#define PCM_CTL0_CPM_OFS (8) +/* CPM Bit Mask */ +#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) +/* PCMKEY Bit Mask */ +#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) +/* PMR_BUSY Bit Offset */ +#define PCM_CTL1_PMR_BUSY_OFS (8) + +/* RTCKEY Bit Offset */ +#define RTC_C_CTL0_KEY_OFS (8) +/* RTCKEY Bit Mask */ +#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) +/* RTCHOLD Bit Offset */ +#define RTC_C_CTL13_HOLD_OFS (6) +/* RTC_C Key Value for RTC_C write access */ +#define RTC_C_KEY ((uint16_t)0xA500) + +/* Watchdog timer hold */ +#define WDT_A_CTL_HOLD ((uint16_t)0x0080) +/* WDT Key Value for WDT write access */ +#define WDT_A_CTL_PW ((uint16_t)0x5A00) + +/* Address of BSL API table */ +#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) + +#ifdef __cplusplus +} +#endif + +#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H */ diff --git a/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds new file mode 100644 index 0000000..7798b30 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p411x/msp432p411x.lds @@ -0,0 +1,151 @@ +/****************************************************************************** +* +* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +MEMORY { + MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00200000 + INFO_FLASH (RX) : ORIGIN = 0x00200000, LENGTH = 0x00008000 + SRAM_CODE_0(RWX): ORIGIN = 0x01000000, LENGTH = 0x00000110 + SRAM_CODE_1(RWX): ORIGIN = 0x01000110, LENGTH = 0x00000030 + SRAM_CODE_2(RWX): ORIGIN = 0x01000150, LENGTH = 0x00000040 + SRAM_CODE_3(RWX): ORIGIN = 0x01000190, LENGTH = 0x00001E70 + SRAM_CODE_4(RWX): ORIGIN = 0x01002000, LENGTH = 0x00000200 + SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000 +} + +REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0); +REGION_ALIAS("REGION_RESET", SRAM_CODE_1); +REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2); +REGION_ALIAS("REGION_TEXT", SRAM_CODE_3); +REGION_ALIAS("REGION_BSS", SRAM_CODE_3); +REGION_ALIAS("REGION_DATA", SRAM_DATA); +REGION_ALIAS("REGION_STACK", SRAM_CODE_4); +REGION_ALIAS("REGION_HEAP", SRAM_DATA); +REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3); +REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3); + +SECTIONS { + /* section for the interrupt vector area */ + .intvecs : { + KEEP (*(.intvecs)) + } > REGION_INTVECT + + PROVIDE (_vtable_base_address = + DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000); + + .vtable (_vtable_base_address) : AT (_vtable_base_address) { + KEEP (*(.vtable)) + } > REGION_DATA + + .descriptor :{ + FILL(0x00000000); + . = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1; + BYTE(0x00); + __ROM_AT = .; + } > REGION_DESCRIPTOR + + .reset : { + KEEP(*(.reset)) + } > REGION_RESET AT> REGION_RESET + + .text : { + CREATE_OBJECT_SYMBOLS + KEEP (*(.text)) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + KEEP (*(.init)) + KEEP (*(.fini*)) + } > REGION_TEXT AT> REGION_TEXT + + .rodata : { + *(.rodata) + *(.rodata.*) + } > REGION_TEXT AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*)) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + __etext = .; + + .data : { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + KEEP (*(.data)) + KEEP (*(.data*)) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .bss : { + __bss_start__ = .; + *(.shbss) + KEEP (*(.bss)) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP (*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + KEEP(*(.stack)) + } > REGION_STACK AT> REGION_STACK + + __stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK); + PROVIDE(__stack = __stack_top); +} + diff --git a/contrib/loaders/flash/msp432/msp432p411x_algo.inc b/contrib/loaders/flash/msp432/msp432p411x_algo.inc new file mode 100644 index 0000000..da41bb7 --- /dev/null +++ b/contrib/loaders/flash/msp432/msp432p411x_algo.inc @@ -0,0 +1,361 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x00,0x22,0x00,0x01,0x11,0x01,0x00,0x01,0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01, +0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,0x00,0x00,0x00,0x00, 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b/contrib/loaders/flash/msp432/startup_msp432e4.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> + +/* Entry point for the application. */ +extern int main(); + +/* Reserve space for the system stack. */ +extern uint32_t __stack_top; + +typedef void(*pFunc)(void); + +/* Interrupt handler prototypes */ +void default_handler(void); +void reset_handler(void); + +/* + * The vector table. Note that the proper constructs must be placed on this to + * ensure that it ends up at physical address 0x0000.0000 or at the start of + * the program if located at a start address other than 0. + */ +void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = { + (pFunc)&__stack_top, /* The initial stack pointer */ + reset_handler, /* The reset handler */ + default_handler, /* The NMI handler */ + default_handler, /* The hard fault handler */ + default_handler, /* The MPU fault handler */ + default_handler, /* The bus fault handler */ + default_handler, /* The usage fault handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + default_handler, /* SVCall handler */ + default_handler, /* Debug monitor handler */ + 0, /* Reserved */ + default_handler, /* The PendSV handler */ + default_handler /* The SysTick handler */ +}; + +/* + * The following are constructs created by the linker, indicating where the + * the "data" and "bss" segments reside in memory. The initializers for the + * for the "data" segment resides immediately following the "text" segment. + */ +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; + +/* + * This is the code that gets called when the processor first starts execution + * following a reset event. Only the absolutely necessary set is performed, + * after which the application supplied entry() routine is called. Any fancy + * actions (such as making decisions based on the reset cause register, and + * resetting the bits in that register) are left solely in the hands of the + * application. + */ +__attribute__((section(".reset"))) __attribute__((naked)) +void reset_handler(void) +{ + /* Set stack pointer */ + __asm(" MOVW.W r0, #0x1700\n" + " MOVT.W r0, #0x2000\n" + " mov sp, r0\n"); + + /* Zero fill the bss segment. */ + __asm(" ldr r0, =__bss_start__\n" + " ldr r1, =__bss_end__\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + /* Call the application's entry point. */ + main(); +} + +/* + * This is the code that gets called when the processor receives an unexpected + * interrupt. This simply enters an infinite loop, preserving the system state + * for examination by a debugger. + */ +void default_handler(void) +{ + /* Enter an infinite loop. */ + while (1) + ; +} diff --git a/contrib/loaders/flash/msp432/startup_msp432p4.c b/contrib/loaders/flash/msp432/startup_msp432p4.c new file mode 100644 index 0000000..ed7ea10 --- /dev/null +++ b/contrib/loaders/flash/msp432/startup_msp432p4.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* +* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +******************************************************************************/ + +#include <stdint.h> + +/* Entry point for the application. */ +extern int main(); + +/* Reserve space for the system stack. */ +extern uint32_t __stack_top; + +typedef void(*pFunc)(void); + +/* Interrupt handler prototypes */ +void default_handler(void); +void reset_handler(void); + +/* + * The vector table. Note that the proper constructs must be placed on this to + * ensure that it ends up at physical address 0x0000.0000 or at the start of + * the program if located at a start address other than 0. + */ +void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = { + (pFunc)&__stack_top, /* The initial stack pointer */ + reset_handler, /* The reset handler */ + default_handler, /* The NMI handler */ + default_handler, /* The hard fault handler */ + default_handler, /* The MPU fault handler */ + default_handler, /* The bus fault handler */ + default_handler, /* The usage fault handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + default_handler, /* SVCall handler */ + default_handler, /* Debug monitor handler */ + 0, /* Reserved */ + default_handler, /* The PendSV handler */ + default_handler /* The SysTick handler */ +}; + +/* + * The following are constructs created by the linker, indicating where the + * the "data" and "bss" segments reside in memory. The initializers for the + * for the "data" segment resides immediately following the "text" segment. + */ +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; + +/* + * This is the code that gets called when the processor first starts execution + * following a reset event. Only the absolutely necessary set is performed, + * after which the application supplied entry() routine is called. Any fancy + * actions (such as making decisions based on the reset cause register, and + * resetting the bits in that register) are left solely in the hands of the + * application. + */ +__attribute__((section(".reset"))) __attribute__((naked)) +void reset_handler(void) +{ + /* Set stack pointer */ + __asm(" MOVW.W r0, #0x1700\n" + " MOVT.W r0, #0x0100\n" + " mov sp, r0\n"); + + /* Zero fill the bss segment. */ + __asm(" ldr r0, =__bss_start__\n" + " ldr r1, =__bss_end__\n" + " mov r2, #0\n" + " .thumb_func\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + /* Call the application's entry point. */ + main(); +} + +/* + * This is the code that gets called when the processor receives an unexpected + * interrupt. This simply enters an infinite loop, preserving the system state + * for examination by a debugger. + */ +void default_handler(void) +{ + /* Enter an infinite loop. */ + while (1) + ; +} |