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-rw-r--r--src/target/arm.h2
-rw-r--r--src/target/cortex_m.c4
-rw-r--r--src/target/hla_target.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/target/arm.h b/src/target/arm.h
index e2d2646..c7c8dc0 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -97,7 +97,7 @@ struct arm {
/** Handle to the PC; valid in all core modes. */
struct reg *pc;
- /** Handle to the CPSR; valid in all core modes. */
+ /** Handle to the CPSR/xPSR; valid in all core modes. */
struct reg *cpsr;
/** Handle to the SPSR; valid only in core modes with an SPSR. */
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 1d08c95..fbe635b 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target)
arm->read_core_reg(target, r, i, ARM_MODE_ANY);
}
- r = arm->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
@@ -732,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int current,
r->valid = true;
/* Make sure we are in Thumb mode */
- r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
+ r = armv7m->arm.cpsr;
buf_set_u32(r->value, 24, 1, 1);
r->dirty = true;
r->valid = true;
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 41fe45e..078ac64 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -427,7 +427,7 @@ static int adapter_debug_entry(struct target *target)
/* make sure we clear the vector catch bit */
adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
- r = arm->core_cache->reg_list + ARMV7M_xPSR;
+ r = arm->cpsr;
xPSR = buf_get_u32(r->value, 0, 32);
/* Are we in an exception handler */