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| -rw-r--r-- | tcl/board/numato_mimas_a7.cfg | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tcl/board/numato_mimas_a7.cfg b/tcl/board/numato_mimas_a7.cfg new file mode 100644 index 0000000..1261fea --- /dev/null +++ b/tcl/board/numato_mimas_a7.cfg @@ -0,0 +1,36 @@ +# +# Numato Mimas A7 - Artix 7 FPGA Board +# +# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet +# +# Note: Connect external DC power supply if programming a heavy design onto FPGA. +# Programming while powering via USB may lead to programming failure. +# Therefore, prefer external power supply. + +interface ftdi +ftdi_device_desc "Mimas Artix 7 FPGA Module" +ftdi_vid_pid 0x2a19 0x1009 + +# channel 0 is for custom purpose by users (like uart, fifo etc) +# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers) +ftdi_channel 1 +ftdi_tdo_sample_edge falling + + +# FTDI Pin Layout +# +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# | DBUS7 | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 | +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# | PROG_B | OE_N | NC | NC | TMS | TDO | TDI | TCK | +# +--------+-------+-------+-------+-------+-------+-------+-------+ +# +# OE_N is JTAG buffer output enable signal (active-low) +# PROG_B is not used, so left as input to FTDI. +# +ftdi_layout_init 0x0008 0x004b +reset_config none +adapter_khz 30000 + +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] |