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| author | Walter Ji <walter.ji@oss.cipunited.com> | 2023-09-26 16:56:02 +0800 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-10-25 01:33:10 +0000 |
| commit | 18c64af13500342da5dc304cb3f2024078815bd4 (patch) | |
| tree | a5c69dbc6afa31790053b6848961f1f72abe80a3 /testing | |
| parent | c7d1f0ddabb301e00738686671b939bb92a06ed9 (diff) | |
| download | riscv-openocd-18c64af13500342da5dc304cb3f2024078815bd4.zip riscv-openocd-18c64af13500342da5dc304cb3f2024078815bd4.tar.gz riscv-openocd-18c64af13500342da5dc304cb3f2024078815bd4.tar.bz2 | |
target/mips32: rework mips core register related functions
Update mips core definitions.
Reworked mips core register structure and read/write function.
Add coprocessor0 register definitions for target configuration.
Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7864
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'testing')
0 files changed, 0 insertions, 0 deletions