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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-05-22 18:55:34 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-06-06 18:05:29 +0100 |
| commit | 6f88aa0fb3bb7a91b5327b75e8fb772ed6d3be2d (patch) | |
| tree | a7845631f2138ccc7f15e4aa32719b1156fd3870 /testing | |
| parent | 061cae171c9d2b6015a565dcc748dd04319e08cf (diff) | |
| download | riscv-openocd-6f88aa0fb3bb7a91b5327b75e8fb772ed6d3be2d.zip riscv-openocd-6f88aa0fb3bb7a91b5327b75e8fb772ed6d3be2d.tar.gz riscv-openocd-6f88aa0fb3bb7a91b5327b75e8fb772ed6d3be2d.tar.bz2 | |
target/cortex_a: fix memory leak of register cache
There is no method to free the register cache, allocated in
armv4_5, so we get a memory leak.
Issue identified by valgrind.
Implement the method arm_free_reg_cache() and call it in cortex_a
deinit and to exit for error during arm_dpm_setup().
Tested on dual cortex-A stm32mp15x.
This change is inspired from similar fix in commit b01b5fe13a67
("armv7m: Fix memory leak in register caching.").
The same allocation is also used by target types "arm7tdmi",
"arm9tdmi", "arm11" and "xscale" but they all lack the deinit
method and I do not have relevant HW to test the fix. For such
reasons they are not addressed in this patch.
Change-Id: I4da1e1f12e36ec245d1f3b11a4eafcbd9a1d2e25
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5693
Tested-by: jenkins
Diffstat (limited to 'testing')
0 files changed, 0 insertions, 0 deletions