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author | Tim Newsome <tim@sifive.com> | 2018-07-18 13:34:23 -0700 |
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committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-07-24 13:07:26 +0100 |
commit | a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20 (patch) | |
tree | 60cd18e3649cbc2700abfe7724954e97de640229 /tcl | |
parent | 9363705820d9552bd24a4e876041a90a881ede55 (diff) | |
download | riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.zip riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.tar.gz riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.tar.bz2 |
Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec.
Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.
Flash support for the SiFive boards will also come in a later commit.
Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/board/sifive-e31arty.cfg | 22 | ||||
-rw-r--r-- | tcl/board/sifive-e51arty.cfg | 22 | ||||
-rw-r--r-- | tcl/board/sifive-hifive1.cfg | 34 |
3 files changed, 78 insertions, 0 deletions
diff --git a/tcl/board/sifive-e31arty.cfg b/tcl/board/sifive-e31arty.cfg new file mode 100644 index 0000000..ec10b27 --- /dev/null +++ b/tcl/board/sifive-e31arty.cfg @@ -0,0 +1,22 @@ +# +# Be sure you include the speed and interface before this file +# Example: +# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg" + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/tcl/board/sifive-e51arty.cfg b/tcl/board/sifive-e51arty.cfg new file mode 100644 index 0000000..ffd83a0 --- /dev/null +++ b/tcl/board/sifive-e51arty.cfg @@ -0,0 +1,22 @@ +# +# Be sure you include the speed and interface before this file +# Example: +# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg" + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/tcl/board/sifive-hifive1.cfg b/tcl/board/sifive-hifive1.cfg new file mode 100644 index 0000000..9bc6670 --- /dev/null +++ b/tcl/board/sifive-hifive1.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off |