Merge branch 'master' into update

Change-Id: Icec244b174cc0c67ab58961649a369db7f344824

47 files changed, 729 insertions, 81 deletions

diff --git a/tcl/board/gti/espressobin.cfg b/tcl/board/gti/espressobin.cfg
new file mode 100644
index 0000000..20d0452
--- /dev/null
+++ b/tcl/board/gti/espressobin.cfg
@@ -0,0 +1,7 @@
+# config for ESPRESSObin from
+# Globalscale Technologies Inc.
+
+# srst is isolated through missing resistor
+reset_config trst_only
+
+source [find target/marvell/88f3720.cfg]
diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
index 1051c25..db3cb03 100644
--- a/tcl/board/openrd.cfg
+++ b/tcl/board/openrd.cfg
@@ -3,6 +3,8 @@
 source [find interface/ftdi/openrd.cfg]
 source [find target/feroceon.cfg]
 
+adapter_khz 2000
+
 $_TARGETNAME configure \
 	-work-area-phys 0x10000000 \
 	-work-area-size 65536 \
diff --git a/tcl/board/st_nucleo_f0.cfg b/tcl/board/st_nucleo_f0.cfg
index e9fda19..e6a03bb 100644
--- a/tcl/board/st_nucleo_f0.cfg
+++ b/tcl/board/st_nucleo_f0.cfg
@@ -6,7 +6,7 @@
 # STM32F091RC
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_f103rb.cfg b/tcl/board/st_nucleo_f103rb.cfg
index 71a92f7..e1990dc 100644
--- a/tcl/board/st_nucleo_f103rb.cfg
+++ b/tcl/board/st_nucleo_f103rb.cfg
@@ -1,7 +1,7 @@
 # This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_f3.cfg b/tcl/board/st_nucleo_f3.cfg
index 9dffdcb..fec612b 100644
--- a/tcl/board/st_nucleo_f3.cfg
+++ b/tcl/board/st_nucleo_f3.cfg
@@ -1,7 +1,7 @@
 # This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_f4.cfg b/tcl/board/st_nucleo_f4.cfg
index b5a78c1..11f6f87 100644
--- a/tcl/board/st_nucleo_f4.cfg
+++ b/tcl/board/st_nucleo_f4.cfg
@@ -4,7 +4,7 @@
 # STM32F411RET6
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg
new file mode 100644
index 0000000..baedeb6
--- /dev/null
+++ b/tcl/board/st_nucleo_h743zi.cfg
@@ -0,0 +1,10 @@
+# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
+# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
+
+source [find interface/stlink-v2-1.cfg]
+
+transport select hla_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st_nucleo_l1.cfg b/tcl/board/st_nucleo_l1.cfg
index 56e2756..d97eb7c 100644
--- a/tcl/board/st_nucleo_l1.cfg
+++ b/tcl/board/st_nucleo_l1.cfg
@@ -1,7 +1,7 @@
 # This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/st_nucleo_l476rg.cfg b/tcl/board/st_nucleo_l476rg.cfg
index 2baa34e..4426c3b 100644
--- a/tcl/board/st_nucleo_l476rg.cfg
+++ b/tcl/board/st_nucleo_l476rg.cfg
@@ -1,7 +1,7 @@
 # This is a ST NUCLEO L476RG board with a single STM32L476RGT6 chip.
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF261636
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm320518_eval_stlink.cfg b/tcl/board/stm320518_eval_stlink.cfg
index ce074cb..a7fef07 100644
--- a/tcl/board/stm320518_eval_stlink.cfg
+++ b/tcl/board/stm320518_eval_stlink.cfg
@@ -4,7 +4,7 @@
 #
 # This is for using the onboard STLINK/V2
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm3220g_eval_stlink.cfg b/tcl/board/stm3220g_eval_stlink.cfg
index 43a4df9..b58e42f 100644
--- a/tcl/board/stm3220g_eval_stlink.cfg
+++ b/tcl/board/stm3220g_eval_stlink.cfg
@@ -4,7 +4,7 @@
 #
 # This is for using the onboard STLINK/V2
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm3241g_eval_stlink.cfg b/tcl/board/stm3241g_eval_stlink.cfg
index 9c7ad5d..b1c54a2 100644
--- a/tcl/board/stm3241g_eval_stlink.cfg
+++ b/tcl/board/stm3241g_eval_stlink.cfg
@@ -4,7 +4,7 @@
 #
 # This is for using the onboard STLINK/V2
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32429i_eval_stlink.cfg b/tcl/board/stm32429i_eval_stlink.cfg
index 2b51cea..010d371 100644
--- a/tcl/board/stm32429i_eval_stlink.cfg
+++ b/tcl/board/stm32429i_eval_stlink.cfg
@@ -4,7 +4,7 @@
 #
 # This is for using the onboard STLINK/V2
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32439i_eval_stlink.cfg b/tcl/board/stm32439i_eval_stlink.cfg
index 5995fb1..b722ce6 100644
--- a/tcl/board/stm32439i_eval_stlink.cfg
+++ b/tcl/board/stm32439i_eval_stlink.cfg
@@ -4,7 +4,7 @@
 #
 # This is for using the onboard STLINK/V2
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f0discovery.cfg b/tcl/board/stm32f0discovery.cfg
index bae9a69..e2b5e38 100644
--- a/tcl/board/stm32f0discovery.cfg
+++ b/tcl/board/stm32f0discovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
 # http://www.st.com/internet/evalboard/product/253215.jsp
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f3discovery.cfg b/tcl/board/stm32f3discovery.cfg
index 5a17b4c..9bb62f5 100644
--- a/tcl/board/stm32f3discovery.cfg
+++ b/tcl/board/stm32f3discovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
 # http://www.st.com/internet/evalboard/product/254044.jsp
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f429disc1.cfg b/tcl/board/stm32f429disc1.cfg
index 9d3cdd7..c0bceba 100644
--- a/tcl/board/stm32f429disc1.cfg
+++ b/tcl/board/stm32f429disc1.cfg
@@ -3,7 +3,7 @@
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
 #
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f429discovery.cfg b/tcl/board/stm32f429discovery.cfg
index e06d2a5..7aef09d 100644
--- a/tcl/board/stm32f429discovery.cfg
+++ b/tcl/board/stm32f429discovery.cfg
@@ -3,7 +3,7 @@
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
 #
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f469discovery.cfg b/tcl/board/stm32f469discovery.cfg
index 63b1363..a9559a7 100644
--- a/tcl/board/stm32f469discovery.cfg
+++ b/tcl/board/stm32f469discovery.cfg
@@ -3,7 +3,7 @@
 # http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395
 #
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f4discovery.cfg b/tcl/board/stm32f4discovery.cfg
index 963e0f9..60b7f42 100644
--- a/tcl/board/stm32f4discovery.cfg
+++ b/tcl/board/stm32f4discovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
 # http://www.st.com/internet/evalboard/product/252419.jsp
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32f7discovery.cfg b/tcl/board/stm32f7discovery.cfg
index 085340f..7d1bc96 100755
--- a/tcl/board/stm32f7discovery.cfg
+++ b/tcl/board/stm32f7discovery.cfg
@@ -2,7 +2,7 @@
 # http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
 
 # This is for using the onboard STLINK/V2-1
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg
new file mode 100644
index 0000000..2949ded
--- /dev/null
+++ b/tcl/board/stm32h7x3i_eval.cfg
@@ -0,0 +1,13 @@
+# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards.
+# This is an ST EVAL-H743XI board with single STM32H743XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html
+# This is an ST EVAL-H753XI board with single STM32H753XI chip.
+# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
+
+source [find interface/stlink-v2-1.cfg]
+
+transport select hla_swd
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/stm32l0discovery.cfg b/tcl/board/stm32l0discovery.cfg
index a035062..aabbf81 100644
--- a/tcl/board/stm32l0discovery.cfg
+++ b/tcl/board/stm32l0discovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32L053 discovery board with a single STM32L053 chip.
 # http://www.st.com/web/en/catalog/tools/PF260319
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32l4discovery.cfg b/tcl/board/stm32l4discovery.cfg
index eb19331..8b79841 100644
--- a/tcl/board/stm32l4discovery.cfg
+++ b/tcl/board/stm32l4discovery.cfg
@@ -4,7 +4,7 @@
 # an stlink-v2-1 interface.
 # This is for STM32L4 boards that are connected via stlink-v2-1.
 
-source [find interface/stlink-v2-1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32ldiscovery.cfg b/tcl/board/stm32ldiscovery.cfg
index 8678d29..3e397cb 100644
--- a/tcl/board/stm32ldiscovery.cfg
+++ b/tcl/board/stm32ldiscovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32L discovery board with a single STM32L152RBT6 chip.
 # http://www.st.com/internet/evalboard/product/250990.jsp
 
-source [find interface/stlink-v2.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/stm32vldiscovery.cfg b/tcl/board/stm32vldiscovery.cfg
index 970b510..60805b3 100644
--- a/tcl/board/stm32vldiscovery.cfg
+++ b/tcl/board/stm32vldiscovery.cfg
@@ -1,7 +1,7 @@
 # This is an STM32VL discovery board with a single STM32F100RB chip.
 # http://www.st.com/internet/evalboard/product/250863.jsp
 
-source [find interface/stlink-v1.cfg]
+source [find interface/stlink.cfg]
 
 transport select hla_swd
 
diff --git a/tcl/board/tocoding_poplar.cfg b/tcl/board/tocoding_poplar.cfg
new file mode 100644
index 0000000..fd66156
--- /dev/null
+++ b/tcl/board/tocoding_poplar.cfg
@@ -0,0 +1,28 @@
+#
+# board configuration for Tocoding Poplar
+#
+
+# board does not feature anything but JTAG
+transport select jtag
+
+adapter_khz 10000
+
+# SRST-only reset configuration
+reset_config srst_only srst_push_pull
+
+source [find tcl/target/hi3798.cfg]
+
+# halt the cores when gdb attaches
+${_TARGETNAME}0 configure -event gdb-attach "halt"
+
+# make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# examine remaining cores
+	foreach _core [set args] {
+		${_TARGETNAME}$_core arp_examine
+	}
+}
diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
index b7d8d5b..7e040b3 100644
--- a/tcl/board/tp-link_tl-mr3020.cfg
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -42,3 +42,5 @@ $_TARGETNAME configure -event reset-init {
 
 set ram_boot_address 0xa0000000
 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
diff --git a/tcl/board/tp-link_wdr4300.cfg b/tcl/board/tp-link_wdr4300.cfg
new file mode 100644
index 0000000..c317916
--- /dev/null
+++ b/tcl/board/tp-link_wdr4300.cfg
@@ -0,0 +1,160 @@
+source [find target/atheros_ar9344.cfg]
+
+reset_config trst_only separate
+
+proc ar9344_40mhz_pll_init {} {
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x13210f00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x13210f00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_BB_DPLL_BASE_REG
+	mww 0xb8116188 0x03000000
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+	mww 0xb8050008 0x0130001C
+
+	# QCA_PLL_CPU_PLL_CFG_REG
+	mww 0xb8050000 0x40021380
+	# QCA_PLL_DDR_PLL_CFG_REG
+	mww 0xb8050004 0x40815800
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x0130801C
+
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0x10810F00
+	mww 0xb81161C0 0x41C00000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0810F00
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL2_REG
+	mww 0xb81161C4 0xD0800F00
+
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x03000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x43000000
+	# QCA_PLL_SRIF_CPU_DPLL3_REG
+	mww 0xb81161C8 0x030003E8
+
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0x10810F00
+	mww 0xb8116240 0x41680000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0810F00
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL2_REG
+	mww 0xb8116244 0xD0800F00
+
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x43000000
+	# QCA_PLL_SRIF_DDR_DPLL3_REG
+	mww 0xb8116248 0x03000718
+
+	# QCA_PLL_CPU_DDR_CLK_CTRL_REG
+	mww 0xb8050008 0x01308018
+	mww 0xb8050008 0x01308010
+	mww 0xb8050008 0x01308000
+
+	# QCA_PLL_DDR_PLL_DITHER_REG
+	mww 0xb8050044 0x78180200
+	# QCA_PLL_CPU_PLL_DITHER_REG
+	mww 0xb8050048 0x41C00000
+
+}
+
+proc ar9344_ddr_init {} {
+	# QCA_DDR_CTRL_CFG_REG
+	mww 0xb8000108 0x40
+	# QCA_DDR_RD_DATA_THIS_CYCLE_REG
+	mww 0xb8000018 0xFF
+	# QCA_DDR_BURST_REG
+	mww 0xb80000C4 0x74444444
+	# QCA_DDR_BURST2_REG
+	mww 0xb80000C8 0x0222
+	# QCA_AHB_MASTER_TOUT_MAX_REG
+	mww 0xb80000CC 0xFFFFF
+
+	# QCA_DDR_CFG_REG
+	mww 0xb8000000 0xC7D48CD0
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_DDR2_CFG_REG
+	mww 0xb80000B8 0x0E59
+	# QCA_DDR_CFG2_REG
+	mww 0xb8000004 0x9DD0E6A8
+
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x08
+	mww 0xb8000010 0x10
+	mww 0xb8000010 0x20
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x02
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x02
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x0133
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x8
+	mww 0xb8000010 0x4
+	mww 0xb8000010 0x4
+
+	# QCA_DDR_MR_REG
+	mww 0xb8000008 0x33
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x1
+
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0382
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+	# QCA_DDR_EMR_REG
+	mww 0xb800000C 0x0402
+	# QCA_DDR_CTRL_REG
+	mww 0xb8000010 0x2
+
+	# QCA_DDR_REFRESH_REG
+	mww 0xb8000014 0x4270
+
+	# QCA_DDR_TAP_CTRL_0_REG
+	mww 0xb800001C 0x0e
+	# QCA_DDR_TAP_CTRL_1_REG
+	mww 0xb8000020 0x0e
+	# QCA_DDR_TAP_CTRL_2_REG
+	mww 0xb8000024 0x0e
+	# QCA_DDR_TAP_CTRL_3_REG
+	mww 0xb8000028 0x0e
+}
+
+$_TARGETNAME configure -event reset-init {
+
+	# mww 0xb806001c 0x1000000
+	ar9344_40mhz_pll_init
+	sleep 100
+
+	# flash remap
+	# SPI_CONTROL_ADDR
+	mww 0xbF000004 0x43
+
+	ar9344_ddr_init
+	sleep 100
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
diff --git a/tcl/interface/ftdi/minimodule.cfg b/tcl/interface/ftdi/minimodule.cfg
index 57249df..7df096d 100644
--- a/tcl/interface/ftdi/minimodule.cfg
+++ b/tcl/interface/ftdi/minimodule.cfg
@@ -4,14 +4,13 @@
 # http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
 #
 
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
 interface ftdi
 ftdi_device_desc "FT2232H MiniModule"
 ftdi_vid_pid 0x0403 0x6010
 
-ftdi_layout_init 0x0018 0x05fb
-ftdi_layout_signal nSRST -data 0x0020
+# Every pin set as high impedance except TCK, TDI, TDO and TMS
+ftdi_layout_init 0x0008 0x000b
+
+# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
+# This choice is arbitrary. Use other GPIO pin if desired.
+ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/tcl/interface/ftdi/openrd.cfg b/tcl/interface/ftdi/openrd.cfg
index 8c1a805..9ec5b5f 100644
--- a/tcl/interface/ftdi/openrd.cfg
+++ b/tcl/interface/ftdi/openrd.cfg
@@ -4,15 +4,10 @@
 # http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
 #
 
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
 interface ftdi
-ftdi_device_desc "OpenRD JTAGKey FT2232D"
+ftdi_device_desc "OpenRD JTAGKey FT2232D B"
 ftdi_vid_pid 0x0403 0x9e90
-ftdi_channel 1
+ftdi_channel 0
 
 ftdi_layout_init 0x0608 0x0f1b
 ftdi_layout_signal nTRST -data 0x0200
diff --git a/tcl/interface/ftdi/sheevaplug.cfg b/tcl/interface/ftdi/sheevaplug.cfg
index f299f27..625aad3 100644
--- a/tcl/interface/ftdi/sheevaplug.cfg
+++ b/tcl/interface/ftdi/sheevaplug.cfg
@@ -7,7 +7,7 @@
 interface ftdi
 ftdi_device_desc "SheevaPlug JTAGKey FT2232D B"
 ftdi_vid_pid 0x9e88 0x9e8f
-ftdi_channel 1
+ftdi_channel 0
 
 ftdi_layout_init 0x0608 0x0f1b
 ftdi_layout_signal nTRST -data 0x0200
diff --git a/tcl/interface/stlink-v1.cfg b/tcl/interface/stlink-v1.cfg
index 13f207d..0004227 100644
--- a/tcl/interface/stlink-v1.cfg
+++ b/tcl/interface/stlink-v1.cfg
@@ -1,9 +1,2 @@
-#
-# STMicroelectronics ST-LINK/V1 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V1"
-hla_vid_pid 0x0483 0x3744
-
+echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink-v2-1.cfg b/tcl/interface/stlink-v2-1.cfg
index 093e801..62f37dc 100644
--- a/tcl/interface/stlink-v2-1.cfg
+++ b/tcl/interface/stlink-v2-1.cfg
@@ -1,16 +1,2 @@
-#
-# STMicroelectronics ST-LINK/V2-1 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V2-1"
-hla_vid_pid 0x0483 0x374b
-
-# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
-# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
-# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
-# number reset issues.
-# eg.
-#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
-
+echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink-v2.cfg b/tcl/interface/stlink-v2.cfg
index ae545a1..070e469 100644
--- a/tcl/interface/stlink-v2.cfg
+++ b/tcl/interface/stlink-v2.cfg
@@ -1,16 +1,2 @@
-#
-# STMicroelectronics ST-LINK/V2 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V2"
-hla_vid_pid 0x0483 0x3748
-
-# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
-# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
-# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
-# number reset issues.
-# eg.
-#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
-
+echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
+source [find interface/stlink.cfg]
diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg
new file mode 100644
index 0000000..d747d85
--- /dev/null
+++ b/tcl/interface/stlink.cfg
@@ -0,0 +1,17 @@
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1 in-circuit
+# debugger/programmer
+#
+
+interface hla
+hla_layout stlink
+hla_device_desc "ST-LINK"
+hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b
+
+# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
+# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
+# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
+# number reset issues.
+# eg.
+#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
+
diff --git a/tcl/target/atheros_ar9344.cfg b/tcl/target/atheros_ar9344.cfg
new file mode 100644
index 0000000..b698f25
--- /dev/null
+++ b/tcl/target/atheros_ar9344.cfg
@@ -0,0 +1,39 @@
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $_CHIPNAME
+} else {
+	set _CHIPNAME ar9344
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x00000001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+proc test_ar9344_uart0_tx {} {
+	echo "configuring uart0.."
+	mww 0xb802000c 0x87
+	mww 0xb8020000 0x15
+	mww 0xb8020004 0
+	mww 0xb802000c 7
+	mww 0xb8020004 0
+
+	echo "send message: hallo world"
+	mww 0xb8020000 0x68
+	mww 0xb8020000 0x65
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x20
+	mww 0xb8020000 0x77
+	mww 0xb8020000 0x6f
+	mww 0xb8020000 0x72
+	mww 0xb8020000 0x6c
+	mww 0xb8020000 0x64
+	mww 0xb8020000 0x0a
+}
diff --git a/tcl/target/hi3798.cfg b/tcl/target/hi3798.cfg
new file mode 100644
index 0000000..9eda150
--- /dev/null
+++ b/tcl/target/hi3798.cfg
@@ -0,0 +1,49 @@
+# Hisilicon Hi3798 Target
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME hi3798
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+
+# declare the 4 main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+set $_TARGETNAME.cti(0) 0x80020000
+set $_TARGETNAME.cti(1) 0x80120000
+set $_TARGETNAME.cti(2) 0x80220000
+set $_TARGETNAME.cti(3) 0x80320000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        #set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        # uncomment when "hawt" rtos is merged
+        # set _command "$_command -rtos hawt"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
diff --git a/tcl/target/marvell/88f3710.cfg b/tcl/target/marvell/88f3710.cfg
new file mode 100644
index 0000000..6e35f29
--- /dev/null
+++ b/tcl/target/marvell/88f3710.cfg
@@ -0,0 +1,5 @@
+# Marvell Armada 3710
+
+set CORES 1
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/tcl/target/marvell/88f3720.cfg b/tcl/target/marvell/88f3720.cfg
new file mode 100644
index 0000000..799d614
--- /dev/null
+++ b/tcl/target/marvell/88f3720.cfg
@@ -0,0 +1,5 @@
+# Marvell Armada 3720
+
+set CORES 2
+
+source [find target/marvell/88f37x0.cfg]
diff --git a/tcl/target/marvell/88f37x0.cfg b/tcl/target/marvell/88f37x0.cfg
new file mode 100644
index 0000000..dba7da2
--- /dev/null
+++ b/tcl/target/marvell/88f37x0.cfg
@@ -0,0 +1,68 @@
+# Main file for Marvell Armada 3700 series targets
+#
+# !!!!!!
+#
+# This file should not be included directly. Instead, please include
+# either marvell/88f3710.cfg or marvell/88f3720.cfg, which set the needed
+# variables to the appropriate values.
+#
+# !!!!!!
+
+# Armada 3700 supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    error "CORES not set. Please do not include marvell/88f37x0.cfg directly, but the specific chip configuration file (marvell/88f3710.cfg, marvell/88f3720.cfg, etc.)."
+}
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME [format a37%s0 $_cores]
+}
+
+set _ctis {0x80820000 0x80920000}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+    set _DAP_TAPID $DAP_TAPID
+} else {
+    set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG tap to access the DAP
+swj_newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+
+# declare the main application cores
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -chain-position $_CHIPNAME.dap -coreid $_core \
+                         -ctibase [lindex $_ctis $_core]"
+
+    if { $_core != 0 } {
+        # non-boot core examination may fail
+        set _command "$_command -defer-examine"
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        # uncomment when "hawt" rtos is merged
+        # set _command "$_command -rtos hawt"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+# declare the auxiliary Cortex-M3 core on AP #3
+target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+targets ${_TARGETNAME}0
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c1cbf1a..e730175 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -10,6 +10,14 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME nrf52
 }
 
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
@@ -21,8 +29,13 @@ swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
-adapter_khz 10000
+adapter_khz 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 if { ![using_hla] } {
 	cortex_m reset_config sysresetreq
 }
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
new file mode 100644
index 0000000..02dbed4
--- /dev/null
+++ b/tcl/target/stm32h7x.cfg
@@ -0,0 +1,93 @@
+# script for stm32h7x family
+
+#
+# stm32h7 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32h7x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+	  set _CPUTAPID 0x6ba00477
+   } {
+      set _CPUTAPID 0x6ba02477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
+
+# Clock after reset is HSI at 64 MHz, no need of PLL
+adapter_khz 1800
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+# use hardware reset, connect under reset
+reset_config srst_only srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable D3 and D1 DBG clocks
+	# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
+	mmw 0x5C001004 0x00600000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
+	mmw 0x5C001004 0x00000187 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB3FZ1 |= WWDG1
+	mmw 0x5C001034 0x00000040 0
+	# DBGMCU_APB4FZ1 |= WDGLSD1
+	mmw 0x5C001054 0x00040000 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0x5C001004 0x00100000 0
+}
+
+$_TARGETNAME configure -event reset-init {
+	# Clock after reset is HSI at 64 MHz, no need of PLL
+	adapter_khz 4000
+}
diff --git a/tcl/target/stm32h7x_dual_bank.cfg b/tcl/target/stm32h7x_dual_bank.cfg
new file mode 100644
index 0000000..7e342f9
--- /dev/null
+++ b/tcl/target/stm32h7x_dual_bank.cfg
@@ -0,0 +1,7 @@
+# script for stm32h7x family (dual flash bank)
+source [find target/stm32h7x.cfg]
+
+# STM32H7xxxI 2Mo have a dual bank flash.
+# Add the second flash bank.
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index 245213b..417b282 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -15,11 +15,11 @@ if { [info exists CHIPNAME] } {
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
-# By default use 8kB (max ram on smallest part)
+# By default use 2kB (max ram on smallest part)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x2000
+   set _WORKAREASIZE 0x800
 }
 
 # JTAG speed should be <= F_CPU/6.
diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg
new file mode 100644
index 0000000..5cc99e1
--- /dev/null
+++ b/tcl/target/stm8l.cfg
@@ -0,0 +1,87 @@
+# script for stm8l family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select stlink_swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8l
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# Set stm8l type
+$_TARGETNAME configure -enable_stm8l
+
+# The khz rate does not apply here, only slow <0> and fast <1>
+adapter_khz 1
+
+reset_config srst_only
+
+#uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst
diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg
new file mode 100644
index 0000000..d55e61b
--- /dev/null
+++ b/tcl/target/stm8s.cfg
@@ -0,0 +1,84 @@
+# script for stm8s family
+
+#
+# stm8 devices support SWIM transports only.
+#
+
+transport select stlink_swim
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm8s
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 1kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists FLASHSTART] } {
+   set _FLASHSTART $FLASHSTART
+} else {
+   set _FLASHSTART 0x8000
+}
+
+if { [info exists FLASHEND] } {
+   set _FLASHEND $FLASHEND
+} else {
+   set _FLASHEND 0xffff
+}
+
+if { [info exists EEPROMSTART] } {
+   set _EEPROMSTART $EEPROMSTART
+} else {
+   set _EEPROMSTART 0x4000
+}
+
+if { [info exists EEPROMEND] } {
+   set _EEPROMEND $EEPROMEND
+} else {
+   set _EEPROMEND 0x43ff
+}
+
+if { [info exists OPTIONSTART] } {
+   set _OPTIONSTART $OPTIONSTART
+} else {
+   set _OPTIONSTART 0x4800
+}
+
+if { [info exists OPTIONEND] } {
+   set _OPTIONEND $OPTIONEND
+} else {
+   set _OPTIONEND 0x487f
+}
+
+if { [info exists BLOCKSIZE] } {
+   set _BLOCKSIZE $BLOCKSIZE
+} else {
+   set _BLOCKSIZE 0x80
+}
+
+hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu
+
+$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1
+$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND
+$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE
+
+# Uncomment this line to enable interrupts while instruction step
+#$_TARGETNAME configure -enable_step_irq
+
+# The khz rate does not apply here, only slow <0> and fast <1>
+adapter_khz 1
+
+reset_config srst_only
+
+# uncomment this line to connect under reset
+#reset_config srst_nogate connect_assert_srst