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author | Oleksij Rempel <linux@rempel-privat.de> | 2018-02-19 15:49:31 +0100 |
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committer | Paul Fertser <fercerpav@gmail.com> | 2018-07-31 15:56:58 +0100 |
commit | bfdccf4c8a7a0b358991ca3b9dc91f526d39ac96 (patch) | |
tree | d9fddb6888aaeb5b6631d8c2231de16ab9dc3b93 /tcl | |
parent | dcf977c89a24b02fd8200af633be1fdd3add4ae7 (diff) | |
download | riscv-openocd-bfdccf4c8a7a0b358991ca3b9dc91f526d39ac96.zip riscv-openocd-bfdccf4c8a7a0b358991ca3b9dc91f526d39ac96.tar.gz riscv-openocd-bfdccf4c8a7a0b358991ca3b9dc91f526d39ac96.tar.bz2 |
tcl/target/atheros_ar9331: add DDR2 helper
this helper works on many different boards, so it is
good to have it in target config
Change-Id: I068deac36fdd73dbbcedffc87865cc5b9d992c1d
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4422
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/target/atheros_ar9331.cfg | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg index cd69183..290825f 100644 --- a/tcl/target/atheros_ar9331.cfg +++ b/tcl/target/atheros_ar9331.cfg @@ -48,3 +48,46 @@ proc ar9331_ddr1_init {} { mww 0xb8000018 0xff ;# DDR read and capture bit mask. ;# Each bit represents a cycle of valid data. } + +proc ar9331_ddr2_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb800008c 0x00000a59 + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000090 0x00000000 + mww 0xb8000010 0x00000010 ;# EMR2S update cycle + + mww 0xb8000094 0x00000000 + mww 0xb8000010 0x00000020 ;# EMR3S update cycle + + mww 0xb800000c 0x00000000 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000008 0x00000100 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000010 0x00000004 + mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle + + mww 0xb8000008 0x00000a33 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb800000c 0x00000382 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb800000c 0x00000402 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000014 0x00004186 ;# DDR_REFRESH + mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0 + mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1 + + ;# DDR read and capture bit mask. + ;# Each bit represents a cycle of valid data. + ;# 0xff: use 16-bit DDR + mww 0xb8000018 0x000000ff +} |