diff options
author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-02-09 15:05:44 +0100 |
---|---|---|
committer | Andreas Fritiofson <andreas.fritiofson@gmail.com> | 2016-08-14 00:13:16 +0100 |
commit | 9aabe0b58b15e6678199392e06117c06e0c0b19b (patch) | |
tree | 2a2ef2bcb65c0571e8243b49fc282653240e0b6c /tcl | |
parent | d080ea6cea53ebfc604382d88981c2446f684e4d (diff) | |
download | riscv-openocd-9aabe0b58b15e6678199392e06117c06e0c0b19b.zip riscv-openocd-9aabe0b58b15e6678199392e06117c06e0c0b19b.tar.gz riscv-openocd-9aabe0b58b15e6678199392e06117c06e0c0b19b.tar.bz2 |
board: add configuration for freescale imx6q sabresd board
This configuration file contains jtag, reset and init functions
for the Freescale SabreSD board variant with iMX6Q SoC.
Change-Id: I2366af6da1d82550eb485f36ad61469305c59ffb
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3357
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/board/fsl_imx6q_sabresd.cfg | 149 |
1 files changed, 149 insertions, 0 deletions
diff --git a/tcl/board/fsl_imx6q_sabresd.cfg b/tcl/board/fsl_imx6q_sabresd.cfg new file mode 100644 index 0000000..797e2de --- /dev/null +++ b/tcl/board/fsl_imx6q_sabresd.cfg @@ -0,0 +1,149 @@ +# +# Board configuration file for the Freescale IMX6Q Sabre SD EVM +# +# This board does not have an embedded JTAG adapter, you must source +# a suitable adapter configuration before sourcing this file. + +# Sabre SD has a standard ARM-20 JTAG connector with +# nTRST and nSRST available. +reset_config trst_and_srst + +# the only possible transport is JTAG +transport select jtag + +# iMX6Q POR gates JTAG and the chip is completely incommunicado +# over JTAG for at least 10ms after nSRST is deasserted +adapter_nsrst_delay 11 + +# Source generic iMX6Q target configuration +set CHIPNAME imx6q +source [find target/imx6.cfg] + +# function to apply initial configuration after a reset. It +# provides a basic pad configuration and also DDR memory and clocks +# sufficient to load and execute a boot loader (e.g. barebox) from +# DDR memory. This list is extracted from the barebox flash image +# header. +proc apply_dcd { } { + mww 0x020e05a8 0x00000030 + mww 0x020e05b0 0x00000030 + mww 0x020e0524 0x00000030 + mww 0x020e051c 0x00000030 + mww 0x020e0518 0x00000030 + mww 0x020e050c 0x00000030 + mww 0x020e05b8 0x00000030 + mww 0x020e05c0 0x00000030 + mww 0x020e05ac 0x00020030 + mww 0x020e05b4 0x00020030 + mww 0x020e0528 0x00020030 + mww 0x020e0520 0x00020030 + mww 0x020e0514 0x00020030 + mww 0x020e0510 0x00020030 + mww 0x020e05bc 0x00020030 + mww 0x020e05c4 0x00020030 + mww 0x020e056c 0x00020030 + mww 0x020e0578 0x00020030 + mww 0x020e0588 0x00020030 + mww 0x020e0594 0x00020030 + mww 0x020e057c 0x00020030 + mww 0x020e0590 0x00003000 + mww 0x020e0598 0x00003000 + mww 0x020e058c 0x00000000 + mww 0x020e059c 0x00003030 + mww 0x020e05a0 0x00003030 + mww 0x020e0784 0x00000030 + mww 0x020e0788 0x00000030 + mww 0x020e0794 0x00000030 + mww 0x020e079c 0x00000030 + mww 0x020e07a0 0x00000030 + mww 0x020e07a4 0x00000030 + mww 0x020e07a8 0x00000030 + mww 0x020e0748 0x00000030 + mww 0x020e074c 0x00000030 + mww 0x020e0750 0x00020000 + mww 0x020e0758 0x00000000 + mww 0x020e0774 0x00020000 + mww 0x020e078c 0x00000030 + mww 0x020e0798 0x000c0000 + mww 0x021b081c 0x33333333 + mww 0x021b0820 0x33333333 + mww 0x021b0824 0x33333333 + mww 0x021b0828 0x33333333 + mww 0x021b481c 0x33333333 + mww 0x021b4820 0x33333333 + mww 0x021b4824 0x33333333 + mww 0x021b4828 0x33333333 + mww 0x021b0018 0x00081740 + mww 0x021b001c 0x00008000 + mww 0x021b000c 0x555a7975 + mww 0x021b0010 0xff538e64 + mww 0x021b0014 0x01ff00db + mww 0x021b002c 0x000026d2 + mww 0x021b0030 0x005b0e21 + mww 0x021b0008 0x09444040 + mww 0x021b0004 0x00025576 + mww 0x021b0040 0x00000027 + mww 0x021b0000 0x831a0000 + mww 0x021b001c 0x04088032 + mww 0x021b001c 0x0408803a + mww 0x021b001c 0x00008033 + mww 0x021b001c 0x0000803b + mww 0x021b001c 0x00428031 + mww 0x021b001c 0x00428039 + mww 0x021b001c 0x09408030 + mww 0x021b001c 0x09408038 + mww 0x021b001c 0x04008040 + mww 0x021b001c 0x04008048 + mww 0x021b0800 0xa1380003 + mww 0x021b4800 0xa1380003 + mww 0x021b0020 0x00005800 + mww 0x021b0818 0x00022227 + mww 0x021b4818 0x00022227 + mww 0x021b083c 0x434b0350 + mww 0x021b0840 0x034c0359 + mww 0x021b483c 0x434b0350 + mww 0x021b4840 0x03650348 + mww 0x021b0848 0x4436383b + mww 0x021b4848 0x39393341 + mww 0x021b0850 0x35373933 + mww 0x021b4850 0x48254A36 + mww 0x021b080c 0x001f001f + mww 0x021b0810 0x001f001f + mww 0x021b480c 0x00440044 + mww 0x021b4810 0x00440044 + mww 0x021b08b8 0x00000800 + mww 0x021b48b8 0x00000800 + mww 0x021b001c 0x00000000 + mww 0x021b0404 0x00011006 + mww 0x020c4068 0x00c03f3f + mww 0x020c406c 0x0030fc03 + mww 0x020c4070 0x0fffc000 + mww 0x020c4074 0x3ff00000 + mww 0x020c4078 0x00fff300 + mww 0x020c407c 0x0f0000c3 + mww 0x020c4080 0x000003ff + mww 0x020e0010 0xf00000cf + mww 0x020e0018 0x007f007f + mww 0x020e001c 0x007f007f +} + +# disable watchdog +proc disable_wdog { } { + mwh 0x020bc000 0x30 +} + +# This function applies the initial configuration after a "reset init" +# command +proc imx6q_sabresd_init { } { + disable_wdog + apply_dcd +} + +# prevent cortex-a code from asserting SRST again +$_TARGETNAME.0 configure -event reset-assert { } +# hook the init function into the reset-init event +$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init } +# make sure target is halted when gdb attaches +$_TARGETNAME.0 configure -event gdb-attach { halt } +# set a slow default JTAG clock, can be overridden later +adapter_khz 1000 |