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| author | Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> | 2016-11-14 19:20:36 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2016-12-08 17:09:47 +0000 |
| commit | 49cac156bb23ef304e4a8520b1c5600846fac0cc (patch) | |
| tree | 759097bd1477ae335f281b434ac10d03fd4a35af /tcl | |
| parent | a033a27f6e2b2a8d3207e7d95ba13d3956ecdfbf (diff) | |
| download | riscv-openocd-49cac156bb23ef304e4a8520b1c5600846fac0cc.zip riscv-openocd-49cac156bb23ef304e4a8520b1c5600846fac0cc.tar.gz riscv-openocd-49cac156bb23ef304e4a8520b1c5600846fac0cc.tar.bz2 | |
stm32l0.cfg: Add examine-end event like on other STM32 targets.
Enable debug in standby/stop/sleep.
Stop watchdogs during halt.
Change-Id: I8383a191cd897118bd88bf78528d05943f3a368e
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-on: http://openocd.zylin.com/3882
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/stm32l0.cfg | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg index fd8f951..245213b 100644 --- a/tcl/target/stm32l0.cfg +++ b/tcl/target/stm32l0.cfg @@ -4,6 +4,7 @@ # source [find target/swj-dp.tcl] +source [find mem_helper.tcl] if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -75,3 +76,12 @@ $_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-start { adapter_khz 300 } + +$_TARGETNAME configure -event examine-end { + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0x40015804 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} |