diff options
| author | Megan Wachs <megan@sifive.com> | 2018-08-29 15:45:11 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2018-08-29 15:47:54 -0700 |
| commit | 34ee883aef314f45b563b28b630a2b0b81086aea (patch) | |
| tree | afddabad461e5299c2084788a6a32766a24715ae /tcl | |
| parent | bdc43554934b12a340c82ceb6ce3eb0d1e61681b (diff) | |
| parent | b4b2ec7d2d143146226e7b2f06e1399ee560148d (diff) | |
| download | riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.zip riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.tar.gz riscv-openocd-34ee883aef314f45b563b28b630a2b0b81086aea.tar.bz2 | |
Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase
Diffstat (limited to 'tcl')
41 files changed, 973 insertions, 128 deletions
diff --git a/tcl/board/8devices-lima.cfg b/tcl/board/8devices-lima.cfg new file mode 100644 index 0000000..136f861 --- /dev/null +++ b/tcl/board/8devices-lima.cfg @@ -0,0 +1,30 @@ +# Product page: +# https://www.8devices.com/products/lima +# +# Location of JTAG pins: +# J2 GPIO0 JTAG TCK +# J2 GPIO1 JTAG TDI +# J2 GPIO2 JTAG TDO +# J2 GPIO3 JTAG TMS +# J2 RST directly connected to RESET_L of the SoC and can be used as +# JTAG SRST. Note: this pin will also reset the debug engine. +# J1 +3,3V Can be use as JTAG Vref +# J1 or J2 GND Can be used for JTAG GND +# +# This board is powered from mini USB connecter which is also used +# as USB to UART converted based on FTDI FT230XQ chip + +source [find target/qualcomm_qca4531.cfg] + +proc board_init { } { + qca4531_ddr2_550_550_init +} + +$_TARGETNAME configure -event reset-init { + board_init +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 diff --git a/tcl/board/atmel_samd10_xplained_mini.cfg b/tcl/board/atmel_samd10_xplained_mini.cfg new file mode 100644 index 0000000..64ae11e --- /dev/null +++ b/tcl/board/atmel_samd10_xplained_mini.cfg @@ -0,0 +1,10 @@ +# +# Atmel SAMD10 Xplained mini evaluation kit. +# http://www.atmel.com/tools/atsamd10-xmini.aspx + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd10d14 + +source [find target/at91samdXX.cfg] diff --git a/tcl/board/atmel_samd11_xplained_pro.cfg b/tcl/board/atmel_samd11_xplained_pro.cfg new file mode 100644 index 0000000..8ce9751 --- /dev/null +++ b/tcl/board/atmel_samd11_xplained_pro.cfg @@ -0,0 +1,10 @@ +# +# Atmel SAMD11 Xplained Pro evaluation kit. +# + +source [find interface/cmsis-dap.cfg] + +# chip name +set CHIPNAME at91samd11d14 + +source [find target/at91samdXX.cfg] diff --git a/tcl/board/dptechnics_dpt-board-v1.cfg b/tcl/board/dptechnics_dpt-board-v1.cfg new file mode 100644 index 0000000..de31c7c --- /dev/null +++ b/tcl/board/dptechnics_dpt-board-v1.cfg @@ -0,0 +1,32 @@ +# Product page: +# https://www.dptechnics.com/en/products/dpt-board-v1.html +# +# JTAG is a 5 pin array located close to main module in following order: +# 1. JTAG TCK +# 2. JTAG TDO +# 3. JTAG TDI +# 4. JTAG TMS +# 5. GND The GND is located near letter G of word JTAG on board. +# +# Two RST pins are connected to: +# 1. GND +# 2. GPIO11 this pin is located near letter R of word RST. +# +# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example +# with 10K resistor connected to V3.3 pin. +# +# This board is powered from micro USB connector. No real reset pin or button, for +# example RESET_L is available. + +source [find target/atheros_ar9331.cfg] + +$_TARGETNAME configure -event reset-init { + ar9331_25mhz_pll_init + sleep 1 + ar9331_ddr2_init +} + +set ram_boot_address 0xa0000000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 + +flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 diff --git a/tcl/board/nxp_frdm-ls1012a.cfg b/tcl/board/nxp_frdm-ls1012a.cfg new file mode 100644 index 0000000..3973b3c --- /dev/null +++ b/tcl/board/nxp_frdm-ls1012a.cfg @@ -0,0 +1,15 @@ +# +# NXP FRDM-LS1012A (Freedom) +# + +# +# NXP Kinetis K20 +# +source [find interface/cmsis-dap.cfg] +transport select jtag + +# Also offers a 10-pin 0.05" CoreSight JTAG connector. + +source [find target/ls1012a.cfg] + +reset_config srst_only diff --git a/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg new file mode 100644 index 0000000..a6e8065 --- /dev/null +++ b/tcl/board/reflexces_achilles_i-dev_kit_arria10.cfg @@ -0,0 +1,13 @@ +# Achilles Instant-Development Kit Arria 10 SoC SoM +# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som +# + +if { [info exists USE_EXTERNAL_DEBUGGER] } { + echo "Using external debugger" +} else { + source [find interface/altera-usb-blaster2.cfg] + usb_blaster_device_desc "Arria10 IDK" +} + +source [find fpga/altera-10m50.cfg] +source [find target/altera_fpgasoc_arria10.cfg] diff --git a/tcl/board/renesas_gen2_common.cfg b/tcl/board/renesas_gen2_common.cfg new file mode 100644 index 0000000..00fa777 --- /dev/null +++ b/tcl/board/renesas_gen2_common.cfg @@ -0,0 +1,14 @@ +# Renesas R-Car Gen2 Evaluation Board common settings + +reset_config trst_and_srst srst_nogate + +proc init_reset {mode} { + # Assert both resets: equivalent to a power-on reset + jtag_reset 1 1 + + # Deassert TRST to begin TAP communication + jtag_reset 0 1 + + # TAP should now be responsive, validate the scan-chain + jtag arp_init +} diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg new file mode 100644 index 0000000..c8032f5 --- /dev/null +++ b/tcl/board/renesas_porter.cfg @@ -0,0 +1,4 @@ +# Renesas R-Car M2 Evaluation Board + +source [find target/renesas_r8a7791.cfg] +source [find board/renesas_gen2_common.cfg] diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg new file mode 100644 index 0000000..a026537 --- /dev/null +++ b/tcl/board/renesas_silk.cfg @@ -0,0 +1,4 @@ +# Renesas R-Car E2 Evaluation Board + +source [find target/renesas_r8a7794.cfg] +source [find board/renesas_gen2_common.cfg] diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg new file mode 100644 index 0000000..d35f874 --- /dev/null +++ b/tcl/board/renesas_stout.cfg @@ -0,0 +1,4 @@ +# Renesas R-Car H2 Evaluation Board + +source [find target/renesas_r8a7790.cfg] +source [find board/renesas_gen2_common.cfg] diff --git a/tcl/board/st_nucleo_f7.cfg b/tcl/board/st_nucleo_f7.cfg index 88a8a30..f94679b 100644 --- a/tcl/board/st_nucleo_f7.cfg +++ b/tcl/board/st_nucleo_f7.cfg @@ -1,7 +1,7 @@ # STMicroelectronics STM32F7 Nucleo development board # Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_h743zi.cfg b/tcl/board/st_nucleo_h743zi.cfg index baedeb6..cfe2cda 100644 --- a/tcl/board/st_nucleo_h743zi.cfg +++ b/tcl/board/st_nucleo_h743zi.cfg @@ -1,7 +1,7 @@ # This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip. # http://www.st.com/en/evaluation-tools/nucleo-h743zi.html -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/st_nucleo_l073rz.cfg b/tcl/board/st_nucleo_l073rz.cfg index fa9dc87..b32f8d5 100644 --- a/tcl/board/st_nucleo_l073rz.cfg +++ b/tcl/board/st_nucleo_l073rz.cfg @@ -1,6 +1,6 @@ # This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip. # http://www.st.com/en/evaluation-tools/nucleo-l073rz.html -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/stm32h7x3i_eval.cfg b/tcl/board/stm32h7x3i_eval.cfg index 2949ded..caf68b6 100644 --- a/tcl/board/stm32h7x3i_eval.cfg +++ b/tcl/board/stm32h7x3i_eval.cfg @@ -4,7 +4,7 @@ # This is an ST EVAL-H753XI board with single STM32H753XI chip. # http://www.st.com/en/evaluation-tools/stm32h753i-eval.html -source [find interface/stlink-v2-1.cfg] +source [find interface/stlink.cfg] transport select hla_swd diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg new file mode 100644 index 0000000..9e1c1ea --- /dev/null +++ b/tcl/board/ti_cc13x0_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC13x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +transport select jtag +adapter_khz 2500 +source [find target/ti_cc13x0.cfg] diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg new file mode 100644 index 0000000..18c5ce5 --- /dev/null +++ b/tcl/board/ti_cc13x2_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC13x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc13x2.cfg] diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg new file mode 100644 index 0000000..3613a47 --- /dev/null +++ b/tcl/board/ti_cc26x0_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC26x0 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc26x0.cfg] diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg new file mode 100644 index 0000000..2f2b34b --- /dev/null +++ b/tcl/board/ti_cc26x2_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC26x2 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select jtag +source [find target/ti_cc26x2.cfg] diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg new file mode 100644 index 0000000..a3dac62 --- /dev/null +++ b/tcl/board/ti_cc3220sf_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select swd +source [find target/ti_cc3220sf.cfg] diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg new file mode 100644 index 0000000..f657bdf --- /dev/null +++ b/tcl/board/ti_cc32xx_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI CC32xx-LaunchXL LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select swd +source [find target/ti_cc32xx.cfg] diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg new file mode 100644 index 0000000..bfad322 --- /dev/null +++ b/tcl/board/ti_msp432_launchpad.cfg @@ -0,0 +1,7 @@ +# +# TI MSP432 LaunchPad Evaluation Kit +# +source [find interface/xds110.cfg] +adapter_khz 2500 +transport select swd +source [find target/ti_msp432.cfg] diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg index 7e040b3..48fb698 100644 --- a/tcl/board/tp-link_tl-mr3020.cfg +++ b/tcl/board/tp-link_tl-mr3020.cfg @@ -1,39 +1,5 @@ source [find target/atheros_ar9331.cfg] -proc ar9331_25mhz_pll_init {} { - mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4 - mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850) - mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL - ;# OUTDIV | REFDIV | DIV_INT - mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register - ;# (disabled?) - mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT - mww 0xb8050008 0x00008000 ;# remove bypass; - ;# AHB_POST_DIV - ratio 2 -} - -proc ar9331_ddr1_init {} { - mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs - mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs - - mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle - mww 0xb8000008 0x133 ;# mode reg: 0x133 - default - mww 0xb8000010 0x1 ;# Forces an MRS update cycl - mww 0xb800000c 0x2 ;# Extended mode register value. - ;# default 0x2 - Reset to weak driver, DLL on - mww 0xb8000010 0x2 ;# Forces an EMRS update cycle - mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle - mww 0xb8000008 0x33 ;# mode reg: remove some bit? - mww 0xb8000010 0x1 ;# Forces an MRS update cycl - mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate - mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0, - ;# DQ[7:0], DQS_0 - mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1, - ;# DQ[15:8], DQS_1. - mww 0xb8000018 0xff ;# DDR read and capture bit mask. - ;# Each bit represents a cycle of valid data. -} - $_TARGETNAME configure -event reset-init { ar9331_25mhz_pll_init sleep 1 diff --git a/tcl/fpga/altera-10m50.cfg b/tcl/fpga/altera-10m50.cfg index 9d00daa..d5af710 100644 --- a/tcl/fpga/altera-10m50.cfg +++ b/tcl/fpga/altera-10m50.cfg @@ -1,6 +1,22 @@ -# Altera MAX10 10M50SAE144C8GES FPGA # see MAX 10 FPGA Device Architecture # Table 3-1: IDCODE Information for MAX 10 Devices -# Version Part Number Manuf. ID LSB -# 0000 0011 0001 1000 0101 000 0110 1110 1 -jtag newtap 10m50 tap -expected-id 0x031850dd -irlen 10 +# Intel MAX 10M02 0x31810dd +# Intel MAX 10M04 0x318a0dd +# Intel MAX 10M08 0x31820dd +# Intel MAX 10M16 0x31830dd +# Intel MAX 10M25 0x31840dd +# Intel MAX 10M40 0x318d0dd +# Intel MAX 10M50 0x31850dd +# Intel MAX 10M02 0x31010dd +# Intel MAX 10M04 0x310a0dd +# Intel MAX 10M08 0x31020dd +# Intel MAX 10M16 0x31030dd +# Intel MAX 10M25 0x31040dd +# Intel MAX 10M40 0x310d0dd +# Intel MAX 10M50 0x31050dd + +jtag newtap 10m50 tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \ + -expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \ + -expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \ + -expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \ + -expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd diff --git a/tcl/interface/xds110.cfg b/tcl/interface/xds110.cfg new file mode 100644 index 0000000..495e202 --- /dev/null +++ b/tcl/interface/xds110.cfg @@ -0,0 +1,12 @@ +# +# Texas Instruments XDS110 +# +# http://processors.wiki.ti.com/index.php/XDS110 +# http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities +# + +interface xds110 + +# Use serial number option to use a specific XDS110 +# when more than one are connected to the host. +#xds110_serial 00000000 diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg new file mode 100644 index 0000000..32fd188 --- /dev/null +++ b/tcl/target/allwinner_v3s.cfg @@ -0,0 +1,71 @@ +# This is the config for an Allwinner V3/V3s (sun8iw8). +# +# Notes: +# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz. +# - Thumb-2 Technology +# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction +# for acceleration of media and signal processing functions +# - Support Large Physical Address Extensions(LPAE) +# - VFPv4 Floating Point Unit +# - 32KB L1 Instruction cache and 32KB L1 Data cache +# - 128KB L2 cache +# - has some integrated DDR2 RAM. +# +# Pins related for debug and bootstrap: +# JTAG +# JTAG_TMS PF0, SDC0_D1 +# JTAG_TDI PF1, SDC0_D0 +# JTAG_TDO PF3, SDC0_CMD +# JTAG_TCK PF5, SDC0_D2 +# UART +# None of UART ports seems to be enabled by ROM. +# UART0_TX PF2, SDC0_CLK Per default disabled +# UART0_RX PF4, SDC0_D3 Per default disabled +# UART1_TX PE21 Per default disabled +# UART1_RX PE22 Per default disabled +# UART2_TX PB0 Per default disabled +# UART2_RX PB1 Per default disabled +# +# JTAG is enabled by default after power on on listed JTAG_* pins. So far the +# boot sequence is: +# Time Action +# 0000ms Power ON +# 0200ms JTAG enabled +# 0220ms JTAG pins switched to SD mode +# +# The time frame of 20ms can be not enough to init and halt the CPU. In this +# case I would recommend to set: "adapter_khz 15000" +# To get more or less precise timings, the board should provide reset pin, +# or some bench power supply with remote function. In my case I used +# EEZ H24005 with this command to power on and halt the target: +# "exec echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt" +# After this it is possible to enable JTAG mode again from boot loader or OS. +# Following DAPs are available: +# dap[0]->MEM-AP AHB +# dap[1]->MEM-AP APB->CA7[0] +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME v3s +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +# No NRST or SRST is present on the SoC. Boards may provide +# some sort of Power cycle reset for complete board or SoC. +# For this case we provide srst_pulls_trst so the board config +# only needs to set srst_only. +reset_config none srst_pulls_trst + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +# Add Cortex A7 core +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap diff --git a/tcl/target/altera_fpgasoc_arria10.cfg b/tcl/target/altera_fpgasoc_arria10.cfg new file mode 100644 index 0000000..c9c5ab6 --- /dev/null +++ b/tcl/target/altera_fpgasoc_arria10.cfg @@ -0,0 +1,56 @@ +# Intel (Altera) Arria10 FPGA SoC + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME arria10 +} + +# ARM CoreSight Debug Access Port (dap HPS) +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID + +# Subsidiary TAP: fpga (tap) +# See Intel Arria 10 Handbook +# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf +# Intel Arria 10 GX 160 0x02ee20dd +# Intel Arria 10 GX 220 0x02e220dd +# Intel Arria 10 GX 270 0x02ee30dd +# Intel Arria 10 GX 320 0x02e230dd +# Intel Arria 10 GX 480 0x02e240dd +# Intel Arria 10 GX 570 0x02ee50dd +# Intel Arria 10 GX 660 0x02e250dd +# Intel Arria 10 GX 900 0x02ee60dd +# Intel Arria 10 GX 1150 0x02e660dd +# Intel Arria 10 GT 900 0x02e260dd +# Intel Arria 10 GT 1150 0x02e060dd +# Intel Arria 10 SX 160 0x02e620dd +# Intel Arria 10 SX 220 0x02e020dd +# Intel Arria 10 SX 270 0x02e630dd +# Intel Arria 10 SX 320 0x02e030dd +# Intel Arria 10 SX 480 0x02e040dd +# Intel Arria 10 SX 570 0x02e650dd +# Intel Arria 10 SX 660 0x02e050dd +jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \ + -expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \ + -expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \ + -expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \ + -expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \ + -expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \ + -expected-id 0x02e050dd + +set _TARGETNAME $_CHIPNAME.cpu + +# +# Cortex-A9 target + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0 +target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \ + -defer-examine +target smp $_TARGETNAME.0 $_TARGETNAME.1 diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg index c5609bb..bea37ed 100644 --- a/tcl/target/atheros_ar9331.cfg +++ b/tcl/target/atheros_ar9331.cfg @@ -1,16 +1,171 @@ +# The Atheros AR9331 is a highly integrated and cost effective +# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless +# local area network (WLAN) AP and router platforms. +# +# Notes: +# - MIPS Processor ID (PRId): 0x00019374 +# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, +# operating at up to 400 MHz +# - External 16-bit DDR1, DDR2, or SDRAM memory interface +# - TRST is not available. +# - EJTAG PrRst signal is not supported +# - RESET_L pin A72 on the SoC will reset internal JTAG logic. +# + +# Pins related for debug and bootstrap: +# Name Pin Description +# JTAG +# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG +# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG +# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG +# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG +# Reset +# RESET_L -, (A72) Input only +# SYS_RST_L ???????? Output reset request or GPIO +# Bootstrap +# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM +# MEM_TYPE[0] GPIO12, (A56) +# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB +# 1 - boot from MDIO. +# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG +# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot +# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz +# UART +# UART0_SOUT GPIO10, (A79) +# UART0_SIN GPIO9, (B68) + +# Per default we need to use "none" variant to be able properly "reset init" +# or "reset halt" the CPU. +reset_config none srst_pulls_trst + +# For SRST based variant we still need proper timings. +# For ETH part the reset should be asserted at least for 10ms +# Since there is no other information let's take 100ms to be sure. +adapter_nsrst_assert_width 100 + +# according to the SoC documentation it should take at least 5ms from +# reset end till bootstrap end. In the practice we need 8ms to get JTAG back +# to live. +adapter_nsrst_delay 8 + if { [info exists CHIPNAME] } { set _CHIPNAME $_CHIPNAME } else { set _CHIPNAME ar9331 } -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x00000001 -} - -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +# provide watchdog helper. +proc disable_watchdog { } { + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event halted { disable_watchdog } + +# Since PrRst is not supported and SRST will reset complete chip +# with JTAG engine, we need to reset CPU from CPU itself. +$_TARGETNAME configure -event reset-assert-pre { + halt +} + +$_TARGETNAME configure -event reset-assert { + catch "mww 0xb806001C 0x01000000" +} + +# To be able to trigger complete chip reset, in case JTAG is blocked +# or CPU not responding, we still can use this helper. +proc full_reset { } { + reset_config srst_only + reset + halt + reset_config none +} + +proc disable_watchdog { } { + ;# disable watchdog + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event reset-end { disable_watchdog } + +# Section with helpers which can be used by boards +proc ar9331_25mhz_pll_init {} { + mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4 + mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850) + mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL + ;# OUTDIV | REFDIV | DIV_INT + mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register + ;# (disabled?) + mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT + mww 0xb8050008 0x00008000 ;# remove bypass; + ;# AHB_POST_DIV - ratio 2 +} + +proc ar9331_ddr1_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle + mww 0xb8000008 0x133 ;# mode reg: 0x133 - default + mww 0xb8000010 0x1 ;# Forces an MRS update cycl + mww 0xb800000c 0x2 ;# Extended mode register value. + ;# default 0x2 - Reset to weak driver, DLL on + mww 0xb8000010 0x2 ;# Forces an EMRS update cycle + mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle + mww 0xb8000008 0x33 ;# mode reg: remove some bit? + mww 0xb8000010 0x1 ;# Forces an MRS update cycl + mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate + mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0, + ;# DQ[7:0], DQS_0 + mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1, + ;# DQ[15:8], DQS_1. + mww 0xb8000018 0xff ;# DDR read and capture bit mask. + ;# Each bit represents a cycle of valid data. +} + +proc ar9331_ddr2_init {} { + mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs + mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs + + mww 0xb800008c 0x00000a59 + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000090 0x00000000 + mww 0xb8000010 0x00000010 ;# EMR2S update cycle + + mww 0xb8000094 0x00000000 + mww 0xb8000010 0x00000020 ;# EMR3S update cycle + + mww 0xb800000c 0x00000000 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000008 0x00000100 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle + + mww 0xb8000010 0x00000004 + mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle + + mww 0xb8000008 0x00000a33 + mww 0xb8000010 0x00000001 ;# MRS update cycle + + mww 0xb800000c 0x00000382 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb800000c 0x00000402 + mww 0xb8000010 0x00000002 ;# EMRS update cycle + + mww 0xb8000014 0x00004186 ;# DDR_REFRESH + mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0 + mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1 + + ;# DDR read and capture bit mask. + ;# Each bit represents a cycle of valid data. + ;# 0xff: use 16-bit DDR + mww 0xb8000018 0x000000ff +} diff --git a/tcl/target/cc32xx.cfg b/tcl/target/cc32xx.cfg deleted file mode 100755 index dfc4c17..0000000 --- a/tcl/target/cc32xx.cfg +++ /dev/null @@ -1,54 +0,0 @@ -# Config for Texas Instruments SoC CC32xx family - -source [find target/swj-dp.tcl] - -adapter_khz 100 - -source [find target/icepick.cfg] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME cc32xx -} - -# -# Main DAP -# -if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID -} else { - if {[using_jtag]} { - set _DAP_TAPID 0x4BA00477 - } else { - set _DAP_TAPID 0x2BA01477 - } -} - -if {[using_jtag]} { - jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable - jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" -} else { - swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -} - -# -# ICEpick-C (JTAG route controller) -# -if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID -} else { - set _JRC_TAPID 0x0B97C02F -} - -if {[using_jtag]} { - jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version - jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap" -} - -# -# Cortex-M3 target -# -set _TARGETNAME $_CHIPNAME.cpu -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg new file mode 100644 index 0000000..9a9e684 --- /dev/null +++ b/tcl/target/ls1012a.cfg @@ -0,0 +1,35 @@ +# +# NXP LS1012A +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ls1012a +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x5ba00477 +} + +if { [info exists SAP_TAPID] } { + set _SAP_TAPID $SAP_TAPID +} else { + set _SAP_TAPID 0x06b2001d +} + +jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID +jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80420000 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti + +target smp $_TARGETNAME + +adapter_khz 2000 diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg index 230ca07..b4e8d05 100644 --- a/tcl/target/psoc5lp.cfg +++ b/tcl/target/psoc5lp.cfg @@ -28,6 +28,38 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE / 2] \ + -work-area-size $_WORKAREASIZE -work-area-backup 0 + +source [find mem_helper.tcl] + +$_TARGETNAME configure -event reset-init { + # Configure Target Device (PSoC 5LP Device Programming Specification 5.2) + + set PANTHER_DBG_CFG 0x4008000C + set PANTHER_DBG_CFG_BYPASS [expr 1 << 1] + mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0 + + set PM_ACT_CFG0 0x400043A0 + mww $PM_ACT_CFG0 0xBF + + set FASTCLK_IMO_CR 0x40004200 + set FASTCLK_IMO_CR_F_RANGE_2 [expr 2 << 0] + set FASTCLK_IMO_CR_F_RANGE_MASK [expr 7 << 0] + mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME + if {![using_hla]} { cortex_m reset_config sysresetreq } diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg new file mode 100644 index 0000000..3d21578 --- /dev/null +++ b/tcl/target/qualcomm_qca4531.cfg @@ -0,0 +1,154 @@ +# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable +# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT). +# +# Product page: +# https://www.qualcomm.com/products/qca4531 +# +# Notes: +# - MIPS Processor ID (PRId): 0x00019374 +# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache, +# operating at up to 650 MHz +# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up +# to 300 MHz +# - TRST is not available. +# - EJTAG PrRst signal is not supported +# - RESET_L pin B56 on the SoC will reset internal JTAG logic. +# +# Pins related for debug and bootstrap: +# Name Pin Description +# JTAG +# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG +# JTAG_TDI GPIO1, (B23) Software configurable, default JTAG +# JTAG_TDO GPIO2, (A28) Software configurable, default JTAG +# JTAG_TMS GPIO3, (A29) Software configurable, default JTAG +# Reset +# RESET_L -, (B56) Input only +# SYS_RST_L GPIO17, (A79) Output reset request or GPIO +# Bootstrap +# JTAG_MODE GPIO16, (A78) 0 - JTAG (Default); 1 - EJTAG +# DDR_SELECT GPIO10, (A57) 0 - DDR2; 1 - DDR1 +# UART +# UART0_SOUT GPIO10, (A57) +# UART0_SIN GPIO9, (B49) + +# Per default we need to use "none" variant to be able properly "reset init" +# or "reset halt" the CPU. +reset_config none srst_pulls_trst + +# For SRST based variant we still need proper timings. +# For ETH part the reset should be asserted at least for 10ms +# Since there is no other information let's take 100ms to be sure. +adapter_nsrst_assert_width 100 + +# according to the SoC documentation it should take at least 5ms from +# reset end till bootstrap end. In the practice we need 8ms to get JTAG back +# to live. +adapter_nsrst_delay 8 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $_CHIPNAME +} else { + set _CHIPNAME qca4531 +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME + +# provide watchdog helper. +proc disable_watchdog { } { + mww 0xb8060008 0x0 +} + +$_TARGETNAME configure -event halted { disable_watchdog } + +# Since PrRst is not supported and SRST will reset complete chip +# with JTAG engine, we need to reset CPU from CPU itself. +$_TARGETNAME configure -event reset-assert-pre { + halt +} + +$_TARGETNAME configure -event reset-assert { + catch "mww 0xb806001C 0x01000000" +} + +# To be able to trigger complete chip reset, in case JTAG is blocked +# or CPU not responding, we still can use this helper. +proc full_reset { } { + reset_config srst_only + reset + halt + reset_config none +} + +# Section with helpers which can be used by boards +proc qca4531_ddr2_550_550_init {} { + # Clear reset flags for different SoC components + mww 0xb806001c 0xfeceffff + mww 0xb806001c 0xeeceffff + mww 0xb806001c 0xe6ceffff + + # PMU configurations + # Internal Switcher + mww 0xb8116c40 0x633c8176 + # Increase the DDR voltage + mww 0xb8116c44 0x10200000 + # XTAL Configurations + mww 0xb81162c0 0x4b962100 + mww 0xb81162c4 0x480 + mww 0xb81162c8 0x04000144 + # Recommended PLL configurations + mww 0xb81161c4 0x54086000 + mww 0xb8116244 0x54086000 + + # PLL init + mww 0xb8050008 0x0131001c + mww 0xb8050000 0x40001580 + mww 0xb8050004 0x40015800 + mww 0xb8050008 0x0131001c + mww 0xb8050000 0x00001580 + mww 0xb8050004 0x00015800 + mww 0xb8050008 0x01310000 + mww 0xb8050044 0x781003ff + mww 0xb8050048 0x003c103f + + # DDR2 init + mww 0xb8000108 0x401f0042 + mww 0xb80000b8 0x0000166d + mww 0xb8000000 0xcfaaf33b + mww 0xb800015c 0x0000000f + mww 0xb8000004 0xa272efa8 + mww 0xb8000018 0x0000ffff + mww 0xb80000c4 0x74444444 + mww 0xb80000c8 0x00000444 + mww 0xb8000004 0xa210ee28 + mww 0xb8000004 0xa2b2e1a8 + mww 0xb8000010 0x8 + mww 0xb80000bc 0x0 + mww 0xb8000010 0x10 + mww 0xb80000c0 0x0 + mww 0xb8000010 0x40 + mww 0xb800000c 0x2 + mww 0xb8000010 0x2 + mww 0xb8000008 0xb43 + mww 0xb8000010 0x1 + mww 0xb8000010 0x8 + mww 0xb8000010 0x4 + mww 0xb8000010 0x4 + mww 0xb8000008 0xa43 + mww 0xb8000010 0x1 + mww 0xb800000c 0x382 + mww 0xb8000010 0x2 + mww 0xb800000c 0x402 + mww 0xb8000010 0x2 + mww 0xb8000014 0x40be + mww 0xb800001C 0x20 + mww 0xb8000020 0x20 + mww 0xb80000cc 0xfffff + + # UART GPIO programming + mww 0xb8040000 0xff30b + mww 0xb8040044 0x908 + mww 0xb8040034 0x160000 +} diff --git a/tcl/target/renesas_r8a7794.cfg b/tcl/target/renesas_r8a7794.cfg new file mode 100644 index 0000000..e3e2724 --- /dev/null +++ b/tcl/target/renesas_r8a7794.cfg @@ -0,0 +1,27 @@ +# Renesas R-Car E2 +# https://www.renesas.com/en-us/solutions/automotive/products/rcar-e2.html + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x4ba00477 +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME r8a7794 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID + +# Configuring only one core using DAP. +# Base addresses of cores: +# core 0 - 0x800F0000 +# core 1 - 0x800F2000 +set _TARGETNAME $_CHIPNAME.ca7. +dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu +target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800F0000 +target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800F2000 -defer-examine + +targets ${_TARGETNAME}0 diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg index b8c0de9..baac9b6 100644 --- a/tcl/target/stm32f0x.cfg +++ b/tcl/target/stm32f0x.cfg @@ -22,6 +22,14 @@ if { [info exists WORKAREASIZE] } { set _WORKAREASIZE 0x1000 } +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + #jtag scan chain if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID @@ -41,7 +49,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE # flash size will be probed set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME # adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz adapter_khz 1000 diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index dc310da..562de30 100755 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -82,3 +82,66 @@ $_TARGETNAME configure -event trace-config { # assignment mmw 0xE0042004 0x00000020 0 } + +$_TARGETNAME configure -event reset-init { + # If the HSE was previously enabled and the external clock source + # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be + # properly switched back to HSI. This situation persists even over a system + # reset, including a pin reset via SRST. However, activating the clock + # security system will detect the problem and clear HSERDY to 0, which in + # turn allows the PLL to switch back to HSI properly. Since we just came + # out of reset, HSEON should be 0. If HSERDY is 1, then this situation must + # have happened; in that case, activate the clock security system to clear + # HSERDY. + if {[mrw 0x40023800] & 0x00020000} { + mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON + sleep 10 ;# Wait for CSS to fire, if it wants to + mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON + mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC + sleep 1 ;# Wait for CSSF to clear + } + + # If the clock security system fired, it will pend an NMI. A pending NMI + # will cause a bad time for any subsequent executing code, such as a + # programming algorithm. + if {[mrw 0xE000ED04] & 0x80000000} { + # ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be + # cleared by any normal means (such as ICSR or NVIC). It can only be + # cleared by entering the NMI handler or by resetting the processor. + echo "[target current]: Clock security system generated NMI. Clearing." + + # Keep the old DEMCR value. + set old [mrw 0xE000EDFC] + + # Enable vector catch on reset. + mww 0xE000EDFC 0x01000001 + + # Issue local reset via AIRCR. + mww 0xE000ED0C 0x05FA0001 + + # Restore old DEMCR value. + mww 0xE000EDFC $old + } + + # Configure PLL to boost clock to HSI x 10 (160 MHz) + mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) + mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency) + mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON + sleep 10 ;# Wait for PLL to lock + mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2) + mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL + + # Boost SWD frequency + # Do not boost JTAG frequency and slow down JTAG memory access or flash write algo + # suffers from DAP WAITs + if {[using_jtag]} { + [[target current] cget -dap] memaccess 16 + } { + adapter_khz 8000 + } +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed since CPU speed will slow down to 16MHz with the reset + adapter_khz 2000 +} diff --git a/tcl/target/ti_cc13x0.cfg b/tcl/target/ti_cc13x0.cfg new file mode 100644 index 0000000..6ea9bd8 --- /dev/null +++ b/tcl/target/ti_cc13x0.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC13x0 - ARM Cortex-M3 +# +# http://www.ti.com +# + +set CHIPNAME cc13x0 +set JRC_TAPID 0x0B9BE02F +set WORKAREASIZE 0x4000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/ti_cc13x2.cfg b/tcl/target/ti_cc13x2.cfg new file mode 100644 index 0000000..280eef4 --- /dev/null +++ b/tcl/target/ti_cc13x2.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC13x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc13x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/cc26xx.cfg b/tcl/target/ti_cc26x0.cfg index c3ac847..7efecb6 100755..100644 --- a/tcl/target/cc26xx.cfg +++ b/tcl/target/ti_cc26x0.cfg @@ -1,23 +1,25 @@ -# Config for Texas Instruments low power SoC CC26xx family - -adapter_khz 100 +# +# Texas Instruments CC26x0 - ARM Cortex-M3 +# +# http://www.ti.com +# source [find target/icepick.cfg] source [find target/ti-cjtag.cfg] if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME + set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME cc26xx + set _CHIPNAME cc26x0 } # # Main DAP # if { [info exists DAP_TAPID] } { - set _DAP_TAPID $DAP_TAPID + set _DAP_TAPID $DAP_TAPID } else { - set _DAP_TAPID 0x4BA00477 + set _DAP_TAPID 0x4BA00477 } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" @@ -26,19 +28,29 @@ jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME. # ICEpick-C (JTAG route controller) # if { [info exists JRC_TAPID] } { - set _JRC_TAPID $JRC_TAPID + set _JRC_TAPID $JRC_TAPID } else { - set _JRC_TAPID 0x1B99A02F + set _JRC_TAPID 0x0B99A02F } jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version -# A start sequence is needed to change from cJTAG (Compact JTAG) to -# 4-pin JTAG before talking via JTAG commands jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc" -# -# Cortex-M3 target -# set _TARGETNAME $_CHIPNAME.cpu dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME + +reset_config srst_only +adapter_nsrst_delay 100 diff --git a/tcl/target/ti_cc26x2.cfg b/tcl/target/ti_cc26x2.cfg new file mode 100644 index 0000000..ecee3fa --- /dev/null +++ b/tcl/target/ti_cc26x2.cfg @@ -0,0 +1,11 @@ +# +# Texas Instruments CC26x2 - ARM Cortex-M4 +# +# http://www.ti.com +# + +set CHIPNAME cc26x2 +set JRC_TAPID 0x0BB4102F +set WORKAREASIZE 0x7000 + +source [find target/ti_cc26x0.cfg] diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg new file mode 100644 index 0000000..f7d9bfe --- /dev/null +++ b/tcl/target/ti_cc3220sf.cfg @@ -0,0 +1,12 @@ +# +# Texas Instruments CC3220SF - ARM Cortex-M4 +# +# http://www.ti.com/CC3220SF +# + +source [find target/swj-dp.tcl] +source [find target/icepick.cfg] +source [find target/ti_cc32xx.cfg] + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg new file mode 100644 index 0000000..bc3038d --- /dev/null +++ b/tcl/target/ti_cc32xx.cfg @@ -0,0 +1,64 @@ +# +# Texas Instruments CC32xx - ARM Cortex-M4 +# +# http://www.ti.com/product/CC3200 +# http://www.ti.com/product/CC3220 +# + +source [find target/swj-dp.tcl] +source [find target/icepick.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME cc32xx +} + +# +# Main DAP +# +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + if {[using_jtag]} { + set _DAP_TAPID 0x4BA00477 + } else { + set _DAP_TAPID 0x2BA01477 + } +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable + jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0" +} else { + swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +} + +# +# ICEpick-C (JTAG route controller) +# +if { [info exists JRC_TAPID] } { + set _JRC_TAPID $JRC_TAPID +} else { + set _JRC_TAPID 0x0B97C02F +} + +if {[using_jtag]} { + jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version + jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu" +} + +set _TARGETNAME $_CHIPNAME.cpu +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x2000 +} + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +reset_config srst_only +adapter_nsrst_delay 1100 diff --git a/tcl/target/ti_msp432p4xx.cfg b/tcl/target/ti_msp432.cfg index 461b595..3407f75 100644 --- a/tcl/target/ti_msp432p4xx.cfg +++ b/tcl/target/ti_msp432.cfg @@ -1,5 +1,5 @@ # -# Texas Instruments MSP432P4xx - ARM Cortex-M4F @ up to 48 MHz +# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz # # http://www.ti.com/MSP432 # @@ -7,7 +7,7 @@ if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { - set _CHIPNAME msp432p4xx + set _CHIPNAME msp432 } if { [info exists CPUTAPID] } { @@ -39,15 +39,13 @@ target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { - # On MSP432P401x Bank0 (8k) is always powered - set _WORKAREASIZE 0x2000 + set _WORKAREASIZE 0x4000 } -$_TARGETNAME configure -work-area-phys 0x20000000 \ - -work-area-size $_WORKAREASIZE -work-area-backup 0 +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 -if { ![using_hla] } { - cortex_m reset_config sysresetreq -} +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME -adapter_khz 500 +reset_config srst_only +adapter_nsrst_delay 100 |